diff mbox series

[06/21,crypto] : add machine description for Zknh

Message ID 20211031093445.1414518-7-siyu@isrc.iscas.ac.cn
State New
Headers show
Series RISC-V: add gcc support for Scalar Cryptography v1.0.0-rc5 | expand

Commit Message

siyu@isrc.iscas.ac.cn Oct. 31, 2021, 9:34 a.m. UTC
From: SiYu Wu <siyu@isrc.iscas.ac.cn>

---
 gcc/common/config/riscv/riscv-common.c |   2 +
 gcc/config/riscv/crypto.md             | 123 +++++++++++++++++++++++++
 gcc/config/riscv/riscv-opts.h          |   2 +
 3 files changed, 127 insertions(+)
diff mbox series

Patch

diff --git a/gcc/common/config/riscv/riscv-common.c b/gcc/common/config/riscv/riscv-common.c
index 1e81847ee5c..c0432c93dd3 100644
--- a/gcc/common/config/riscv/riscv-common.c
+++ b/gcc/common/config/riscv/riscv-common.c
@@ -108,6 +108,7 @@  static const struct riscv_ext_version riscv_ext_version_table[] =
 
   {"zkne",  ISA_SPEC_CLASS_NONE, 1, 0},
   {"zknd",  ISA_SPEC_CLASS_NONE, 1, 0},
+  {"zknh",  ISA_SPEC_CLASS_NONE, 1, 0},
 
   /* Terminate the list.  */
   {NULL, ISA_SPEC_CLASS_NONE, 0, 0}
@@ -921,6 +922,7 @@  static const riscv_ext_flag_table_t riscv_ext_flag_table[] =
 
   {"zknd",   &gcc_options::x_riscv_zk_subext, MASK_ZKND},
   {"zkne",   &gcc_options::x_riscv_zk_subext, MASK_ZKNE},
+  {"zknh",   &gcc_options::x_riscv_zk_subext, MASK_ZKNH},
 
   {NULL, NULL, 0}
 };
diff --git a/gcc/config/riscv/crypto.md b/gcc/config/riscv/crypto.md
index 170be7ff56c..243a77ef528 100644
--- a/gcc/config/riscv/crypto.md
+++ b/gcc/config/riscv/crypto.md
@@ -28,6 +28,16 @@  (define_c_enum "unspec" [
   UNSPEC_AES_IM
   UNSPEC_AES_KS1
   UNSPEC_AES_KS2
+  UNSPEC_SHA_256_SIG0
+  UNSPEC_SHA_256_SIG1
+  UNSPEC_SHA_256_SUM0
+  UNSPEC_SHA_256_SUM1
+  UNSPEC_SHA_512_SIG0
+  UNSPEC_SHA_512_SIG0_2
+  UNSPEC_SHA_512_SIG1
+  UNSPEC_SHA_512_SIG1_2
+  UNSPEC_SHA_512_SUM0
+  UNSPEC_SHA_512_SUM1
 ])
 
 
@@ -127,3 +137,116 @@  (define_insn "riscv_aes64ks2"
   "TARGET_ZKNE && TARGET_64BIT"
   "aes64ks2\t%0,%1,%2")
 
+
+;; Zknh - SHA256
+
+(define_insn "riscv_sha256sig0_<mode>"
+  [(set (match_operand:X 0 "register_operand" "=r")
+        (unspec:X [(match_operand:X 1 "register_operand" "r")]
+                  UNSPEC_SHA_256_SIG0))]
+  "TARGET_ZKNH"
+  "sha256sig0\t%0,%1")
+
+(define_insn "riscv_sha256sig1_<mode>"
+  [(set (match_operand:X 0 "register_operand" "=r")
+        (unspec:X [(match_operand:X 1 "register_operand" "r")]
+                  UNSPEC_SHA_256_SIG1))]
+  "TARGET_ZKNH"
+  "sha256sig1\t%0,%1")
+
+(define_insn "riscv_sha256sum0_<mode>"
+  [(set (match_operand:X 0 "register_operand" "=r")
+        (unspec:X [(match_operand:X 1 "register_operand" "r")]
+                  UNSPEC_SHA_256_SUM0))]
+  "TARGET_ZKNH"
+  "sha256sum0\t%0,%1")
+
+(define_insn "riscv_sha256sum1_<mode>"
+  [(set (match_operand:X 0 "register_operand" "=r")
+        (unspec:X [(match_operand:X 1 "register_operand" "r")]
+                  UNSPEC_SHA_256_SUM1))]
+  "TARGET_ZKNH"
+  "sha256sum1\t%0,%1")
+
+
+;; Zknh - SHA512 (RV32)
+
+(define_insn "riscv_sha512sig0h"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+        (unspec:SI [(match_operand:SI 1 "register_operand" "r")
+                   (match_operand:SI 2 "register_operand" "r")]
+                   UNSPEC_SHA_512_SIG0))]
+  "TARGET_ZKNH && !TARGET_64BIT"
+  "sha512sig0h\t%0,%1,%2")
+
+(define_insn "riscv_sha512sig0l"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+        (unspec:SI [(match_operand:SI 1 "register_operand" "r")
+                   (match_operand:SI 2 "register_operand" "r")]
+                   UNSPEC_SHA_512_SIG0_2))]
+  "TARGET_ZKNH && !TARGET_64BIT"
+  "sha512sig0l\t%0,%1,%2")
+
+(define_insn "riscv_sha512sig1h"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+        (unspec:SI [(match_operand:SI 1 "register_operand" "r")
+                   (match_operand:SI 2 "register_operand" "r")]
+                   UNSPEC_SHA_512_SIG1))]
+  "TARGET_ZKNH && !TARGET_64BIT"
+  "sha512sig1h\t%0,%1,%2")
+
+(define_insn "riscv_sha512sig1l"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+        (unspec:SI [(match_operand:SI 1 "register_operand" "r")
+                   (match_operand:SI 2 "register_operand" "r")]
+                   UNSPEC_SHA_512_SIG1_2))]
+  "TARGET_ZKNH && !TARGET_64BIT"
+  "sha512sig1l\t%0,%1,%2")
+
+(define_insn "riscv_sha512sum0r"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+        (unspec:SI [(match_operand:SI 1 "register_operand" "r")
+                   (match_operand:SI 2 "register_operand" "r")]
+                   UNSPEC_SHA_512_SUM0))]
+  "TARGET_ZKNH && !TARGET_64BIT"
+  "sha512sum0r\t%0,%1,%2")
+
+(define_insn "riscv_sha512sum1r"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+        (unspec:SI [(match_operand:SI 1 "register_operand" "r")
+                   (match_operand:SI 2 "register_operand" "r")]
+                   UNSPEC_SHA_512_SUM1))]
+  "TARGET_ZKNH && !TARGET_64BIT"
+  "sha512sum1r\t%0,%1,%2")
+
+
+;; Zknh - SHA512 (RV64)
+
+(define_insn "riscv_sha512sig0"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+        (unspec:DI [(match_operand:DI 1 "register_operand" "r")]
+                   UNSPEC_SHA_512_SIG0))]
+  "TARGET_ZKNH && TARGET_64BIT"
+  "sha512sig0\t%0,%1")
+
+(define_insn "riscv_sha512sig1"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+        (unspec:DI [(match_operand:DI 1 "register_operand" "r")]
+                   UNSPEC_SHA_512_SIG1))]
+  "TARGET_ZKNH && TARGET_64BIT"
+  "sha512sig1\t%0,%1")
+
+(define_insn "riscv_sha512sum0"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+        (unspec:DI [(match_operand:DI 1 "register_operand" "r")]
+                   UNSPEC_SHA_512_SUM0))]
+  "TARGET_ZKNH && TARGET_64BIT"
+  "sha512sum0\t%0,%1")
+
+(define_insn "riscv_sha512sum1"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+        (unspec:DI [(match_operand:DI 1 "register_operand" "r")]
+                   UNSPEC_SHA_512_SUM1))]
+  "TARGET_ZKNH && TARGET_64BIT"
+  "sha512sum1\t%0,%1")
+
diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h
index b0226335c4f..9d8e560c4ba 100644
--- a/gcc/config/riscv/riscv-opts.h
+++ b/gcc/config/riscv/riscv-opts.h
@@ -85,8 +85,10 @@  enum stack_protector_guard {
 
 #define MASK_ZKNE     (1 << 5)
 #define MASK_ZKND     (1 << 6)
+#define MASK_ZKNH     (1 << 7)
 
 #define TARGET_ZKNE   ((riscv_zk_subext & MASK_ZKNE) != 0)
 #define TARGET_ZKND   ((riscv_zk_subext & MASK_ZKND) != 0)
+#define TARGET_ZKNH   ((riscv_zk_subext & MASK_ZKNH) != 0)
 
 #endif /* ! GCC_RISCV_OPTS_H */