diff mbox series

[05/21,crypto] : add testcases for Zknd and Zkne

Message ID 20211031093445.1414518-6-siyu@isrc.iscas.ac.cn
State New
Headers show
Series RISC-V: add gcc support for Scalar Cryptography v1.0.0-rc5 | expand

Commit Message

siyu@isrc.iscas.ac.cn Oct. 31, 2021, 9:34 a.m. UTC
From: SiYu Wu <siyu@isrc.iscas.ac.cn>

Co-authored-by: Shihua Liao <shihua@iscas.ac.cn>
---
 gcc/testsuite/gcc.target/riscv/Zknd-aes-01.c | 15 +++++++++++
 gcc/testsuite/gcc.target/riscv/Zknd-aes-02.c | 21 +++++++++++++++
 gcc/testsuite/gcc.target/riscv/Zkne-aes-01.c | 15 +++++++++++
 gcc/testsuite/gcc.target/riscv/Zkne-aes-02.c | 27 ++++++++++++++++++++
 4 files changed, 78 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/Zknd-aes-01.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/Zknd-aes-02.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/Zkne-aes-01.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/Zkne-aes-02.c
diff mbox series

Patch

diff --git a/gcc/testsuite/gcc.target/riscv/Zknd-aes-01.c b/gcc/testsuite/gcc.target/riscv/Zknd-aes-01.c
new file mode 100644
index 00000000000..87d0b490476
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/Zknd-aes-01.c
@@ -0,0 +1,15 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc_zknd -mabi=ilp32 -O2" } */
+
+int foo1(int rs1, int rs2)
+{
+    return __builtin_riscv_aes32dsi(rs1, rs2, 1);
+}
+
+int foo2(int rs1, int rs2)
+{
+    return __builtin_riscv_aes32dsmi(rs1, rs2, 0);
+}
+
+/* { dg-final { scan-assembler-times "aes32dsi" 1 } } */
+/* { dg-final { scan-assembler-times "aes32dsmi" 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/Zknd-aes-02.c b/gcc/testsuite/gcc.target/riscv/Zknd-aes-02.c
new file mode 100644
index 00000000000..3abe8342f9f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/Zknd-aes-02.c
@@ -0,0 +1,21 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zknd -mabi=lp64 -O2" } */
+
+long foo1(long rs1, long rs2)
+{
+    return __builtin_riscv_aes64ds(rs1, rs2);
+}
+
+long foo2(long rs1, long rs2)
+{
+    return __builtin_riscv_aes64dsm(rs1, rs2);
+}
+
+long foo3(long rs1)
+{
+    return __builtin_riscv_aes64im(rs1);
+}
+
+/* { dg-final { scan-assembler-times "aes64ds" 2 } } */
+/* { dg-final { scan-assembler-times "aes64dsm" 1 } } */
+/* { dg-final { scan-assembler-times "aes64im" 1 } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/riscv/Zkne-aes-01.c b/gcc/testsuite/gcc.target/riscv/Zkne-aes-01.c
new file mode 100644
index 00000000000..06848166f07
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/Zkne-aes-01.c
@@ -0,0 +1,15 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc_zkne -mabi=ilp32 -O2" } */
+
+int foo1(int rs1, int rs2)
+{
+    return __builtin_riscv_aes32esi(rs1, rs2, 1);
+}
+
+int foo2(int rs1, int rs2)
+{
+    return __builtin_riscv_aes32esmi(rs1, rs2, 1);
+}
+
+/* { dg-final { scan-assembler-times "aes32esi" 1 } } */
+/* { dg-final { scan-assembler-times "aes32esmi" 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/Zkne-aes-02.c b/gcc/testsuite/gcc.target/riscv/Zkne-aes-02.c
new file mode 100644
index 00000000000..8c8bf43b680
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/Zkne-aes-02.c
@@ -0,0 +1,27 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zkne -mabi=lp64 -O2" } */
+
+long foo1(long rs1, long rs2)
+{
+    return __builtin_riscv_aes64es(rs1, rs2);
+}
+
+long foo2(long rs1, long rs2)
+{
+    return __builtin_riscv_aes64esm(rs1, rs2);
+}
+
+long foo3(long rs1)
+{
+    return __builtin_riscv_aes64ks1i(rs1, 1);
+}
+
+long foo4(long rs1, long rs2)
+{
+    return __builtin_riscv_aes64ks2(rs1, rs2);
+}
+
+/* { dg-final { scan-assembler-times "aes64es" 2 } } */
+/* { dg-final { scan-assembler-times "aes64esm" 1 } } */
+/* { dg-final { scan-assembler-times "aes64ks1i" 1 } } */
+/* { dg-final { scan-assembler-times "aes64ks2" 1 } } */
\ No newline at end of file