diff mbox series

[02/21] Fix attribute bugs due to zicsr/zifencei

Message ID 20211031093445.1414518-3-siyu@isrc.iscas.ac.cn
State New
Headers
Series RISC-V: add gcc support for Scalar Cryptography v1.0.0-rc5 |

Commit Message

siyu@isrc.iscas.ac.cn Oct. 31, 2021, 9:34 a.m. UTC 
  From: jiawei <jiawei@iscas.ac.cn>

---
 gcc/config/riscv/arch-canonicalize | 2 ++
 gcc/config/riscv/riscv.md          | 2 +-
 2 files changed, 3 insertions(+), 1 deletion(-)

Comments

Kito Cheng Nov. 2, 2021, 10:42 a.m. UTC | #1 
> diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
> index 225e5b259c1..1a786f31258 100644
> --- a/gcc/config/riscv/riscv.md
> +++ b/gcc/config/riscv/riscv.md
> @@ -1812,7 +1812,7 @@ (define_expand "clear_cache"
>
>  (define_insn "fence"
>    [(unspec_volatile [(const_int 0)] UNSPECV_FENCE)]
> -  ""
> +  "TARGET_ZIFENCEI"
   "%|fence%-")

fence instruction is included in baseline ISA.
https://github.com/riscv/riscv-isa-manual/blob/master/src/rv32.tex#L1206
diff mbox series

Patch

diff --git a/gcc/config/riscv/arch-canonicalize b/gcc/config/riscv/arch-canonicalize
index c7df3c8a313..e2feb7e85cd 100755
--- a/gcc/config/riscv/arch-canonicalize
+++ b/gcc/config/riscv/arch-canonicalize
@@ -36,6 +36,8 @@  LONG_EXT_PREFIXES = ['z', 's', 'h', 'x']
 #
 IMPLIED_EXT = {
   "d" : ["f"],
+  "f" : ["zicsr"],
+  "f" : ["zifencei"],
 }
 
 def arch_canonicalize(arch):
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index 225e5b259c1..1a786f31258 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -1812,7 +1812,7 @@  (define_expand "clear_cache"
 
 (define_insn "fence"
   [(unspec_volatile [(const_int 0)] UNSPECV_FENCE)]
-  ""
+  "TARGET_ZIFENCEI"
   "%|fence%-")
 
 (define_insn "fence_i"