diff mbox series

[12/21,crypto] : add machine description for Zksh

Message ID 20211031093445.1414518-13-siyu@isrc.iscas.ac.cn
State New
Headers show
Series RISC-V: add gcc support for Scalar Cryptography v1.0.0-rc5 | expand

Commit Message

siyu@isrc.iscas.ac.cn Oct. 31, 2021, 9:34 a.m. UTC
From: SiYu Wu <siyu@isrc.iscas.ac.cn>

---
 gcc/common/config/riscv/riscv-common.c |  2 ++
 gcc/config/riscv/crypto.md             | 19 +++++++++++++++++++
 gcc/config/riscv/riscv-opts.h          |  2 ++
 3 files changed, 23 insertions(+)
diff mbox series

Patch

diff --git a/gcc/common/config/riscv/riscv-common.c b/gcc/common/config/riscv/riscv-common.c
index d4d61bd765d..8f4f4472690 100644
--- a/gcc/common/config/riscv/riscv-common.c
+++ b/gcc/common/config/riscv/riscv-common.c
@@ -110,6 +110,7 @@  static const struct riscv_ext_version riscv_ext_version_table[] =
   {"zknd",  ISA_SPEC_CLASS_NONE, 1, 0},
   {"zknh",  ISA_SPEC_CLASS_NONE, 1, 0},
   {"zksed", ISA_SPEC_CLASS_NONE, 1, 0},
+  {"zksh",  ISA_SPEC_CLASS_NONE, 1, 0},
 
   /* Terminate the list.  */
   {NULL, ISA_SPEC_CLASS_NONE, 0, 0}
@@ -925,6 +926,7 @@  static const riscv_ext_flag_table_t riscv_ext_flag_table[] =
   {"zkne",   &gcc_options::x_riscv_zk_subext, MASK_ZKNE},
   {"zknh",   &gcc_options::x_riscv_zk_subext, MASK_ZKNH},
   {"zksed",  &gcc_options::x_riscv_zk_subext, MASK_ZKSED},
+  {"zksh",   &gcc_options::x_riscv_zk_subext, MASK_ZKSH},
 
   {NULL, NULL, 0}
 };
diff --git a/gcc/config/riscv/crypto.md b/gcc/config/riscv/crypto.md
index ac0107f43c2..79ca2ec2696 100644
--- a/gcc/config/riscv/crypto.md
+++ b/gcc/config/riscv/crypto.md
@@ -38,6 +38,8 @@  (define_c_enum "unspec" [
   UNSPEC_SHA_512_SIG1_2
   UNSPEC_SHA_512_SUM0
   UNSPEC_SHA_512_SUM1
+  UNSPEC_SM3_P0
+  UNSPEC_SM3_P1
   UNSPEC_SM4_ED
   UNSPEC_SM4_KS
 ])
@@ -253,6 +255,23 @@  (define_insn "riscv_sha512sum1"
   "sha512sum1\t%0,%1")
 
 
+;; Zksh - SM3
+
+(define_insn "riscv_sm3p0_<mode>"
+  [(set (match_operand:X 0 "register_operand" "=r")
+        (unspec:X [(match_operand:X 1 "register_operand" "r")]
+                  UNSPEC_SM3_P0))]
+  "TARGET_ZKSH"
+  "sm3p0\t%0,%1")
+
+(define_insn "riscv_sm3p1_<mode>"
+  [(set (match_operand:X 0 "register_operand" "=r")
+        (unspec:X [(match_operand:X 1 "register_operand" "r")]
+                  UNSPEC_SM3_P1))]
+  "TARGET_ZKSH"
+  "sm3p1\t%0,%1")
+
+
 ;; Zksed - SM4
 
 (define_insn "riscv_sm4ed_<mode>"
diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h
index 6ad89db42f5..dafcf1f591f 100644
--- a/gcc/config/riscv/riscv-opts.h
+++ b/gcc/config/riscv/riscv-opts.h
@@ -87,10 +87,12 @@  enum stack_protector_guard {
 #define MASK_ZKND     (1 << 6)
 #define MASK_ZKNH     (1 << 7)
 #define MASK_ZKSED    (1 << 9)
+#define MASK_ZKSH     (1 << 10)
 
 #define TARGET_ZKNE   ((riscv_zk_subext & MASK_ZKNE) != 0)
 #define TARGET_ZKND   ((riscv_zk_subext & MASK_ZKND) != 0)
 #define TARGET_ZKNH   ((riscv_zk_subext & MASK_ZKNH) != 0)
 #define TARGET_ZKSED  ((riscv_zk_subext & MASK_ZKSED) != 0)
+#define TARGET_ZKSH   ((riscv_zk_subext & MASK_ZKSH) != 0)
 
 #endif /* ! GCC_RISCV_OPTS_H */