diff mbox series

[19/21,crypto] : add machine description for Zbkx

Message ID 20211031093445.1414518-20-siyu@isrc.iscas.ac.cn
State New
Headers show
Series RISC-V: add gcc support for Scalar Cryptography v1.0.0-rc5 | expand

Commit Message

siyu@isrc.iscas.ac.cn Oct. 31, 2021, 9:34 a.m. UTC
From: SiYu Wu <siyu@isrc.iscas.ac.cn>

NOTE: The Zbkx should be implemented in bitmanip's Zbp, but since zbp is not
included in the bitmanip spec v1.0, and crypto's v1.0 release will earlier
than bitmanip's next release, so for now we implementing it here.
---
 gcc/config/riscv/crypto.md | 27 +++++++++++++++++++++++++++
 1 file changed, 27 insertions(+)
diff mbox series

Patch

diff --git a/gcc/config/riscv/crypto.md b/gcc/config/riscv/crypto.md
index 79ca2ec2696..8753f2f585c 100644
--- a/gcc/config/riscv/crypto.md
+++ b/gcc/config/riscv/crypto.md
@@ -42,6 +42,10 @@  (define_c_enum "unspec" [
   UNSPEC_SM3_P1
   UNSPEC_SM4_ED
   UNSPEC_SM4_KS
+
+  ;; Zbkx unspecs, see below
+  UNSPEC_XPERM8
+  UNSPEC_XPERM4
 ])
 
 
@@ -290,3 +294,26 @@  (define_insn "riscv_sm4ks_<mode>"
   "TARGET_ZKSED"
   "sm4ks\t%0,%1,%2")
 
+;; Zbkx
+
+;; The Zbkx should be implemented in bitmanip's Zbp, but since zbp is not
+;; included in the bitmanip spec v1.0, and crypto's v1.0 release will earlier
+;; than bitmanip's next release, so for now we implementing it here.
+;;                                                                   2021/10/24
+
+(define_insn "riscv_xperm8_<mode>"
+  [(set (match_operand:X 0 "register_operand" "=r")
+        (unspec:X [(match_operand:X 1 "register_operand" "r")
+                  (match_operand:X 2 "register_operand" "r")]
+                  UNSPEC_XPERM8))]
+  "TARGET_ZBKX"
+  "xperm8\t%0,%1,%2")
+
+(define_insn "riscv_xperm4_<mode>"
+  [(set (match_operand:X 0 "register_operand" "=r")
+        (unspec:X [(match_operand:X 1 "register_operand" "r")
+                  (match_operand:X 2 "register_operand" "r")]
+                  UNSPEC_XPERM4))]
+  "TARGET_ZBKX"
+  "xperm4\t%0,%1,%2")
+