diff mbox series

[08/21,crypto] : add testcases for Zknh

Message ID 20211031093445.1414518-9-siyu@isrc.iscas.ac.cn
State New
Headers show
Series RISC-V: add gcc support for Scalar Cryptography v1.0.0-rc5 | expand

Commit Message

siyu@isrc.iscas.ac.cn Oct. 31, 2021, 9:34 a.m. UTC
From: SiYu Wu <siyu@isrc.iscas.ac.cn>

Co-authored-by: Shihua Liao <shihua@iscas.ac.cn>
---
 gcc/testsuite/gcc.target/riscv/Zknh-sha256.c  | 27 +++++++++++++
 .../gcc.target/riscv/Zknh-sha512-01.c         | 40 +++++++++++++++++++
 .../gcc.target/riscv/Zknh-sha512-02.c         | 28 +++++++++++++
 3 files changed, 95 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/Zknh-sha256.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/Zknh-sha512-01.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/Zknh-sha512-02.c
diff mbox series

Patch

diff --git a/gcc/testsuite/gcc.target/riscv/Zknh-sha256.c b/gcc/testsuite/gcc.target/riscv/Zknh-sha256.c
new file mode 100644
index 00000000000..1c1cb7be5d0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/Zknh-sha256.c
@@ -0,0 +1,27 @@ 
+/* { dg-do compile { target { riscv64*-*-* } } } */
+/* { dg-options "-march=rv64gc_zknh -mabi=lp64 -O2" } */
+
+long foo1(long rs1)
+{
+    return __builtin_riscv_sha256sig0(rs1);
+}
+
+long foo2(long rs1)
+{
+    return __builtin_riscv_sha256sig1(rs1);
+}
+
+long foo3(long rs1)
+{
+    return __builtin_riscv_sha256sum0(rs1);
+}
+
+long foo4(long rs1)
+{
+    return __builtin_riscv_sha256sum1(rs1);
+}
+
+/* { dg-final { scan-assembler-times "sha256sig0" 1 } } */
+/* { dg-final { scan-assembler-times "sha256sig1" 1 } } */
+/* { dg-final { scan-assembler-times "sha256sum0" 1 } } */
+/* { dg-final { scan-assembler-times "sha256sum1" 1 } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/riscv/Zknh-sha512-01.c b/gcc/testsuite/gcc.target/riscv/Zknh-sha512-01.c
new file mode 100644
index 00000000000..ef1f6dafe60
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/Zknh-sha512-01.c
@@ -0,0 +1,40 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc_zknh -mabi=ilp32 -O2" } */
+
+int foo1(int rs1, int rs2)
+{
+    return __builtin_riscv_sha512sig0h(rs1, rs2);
+}
+
+int foo2(int rs1, int rs2)
+{
+    return __builtin_riscv_sha512sig0l(rs1, rs2);
+}
+
+int foo3(int rs1, int rs2)
+{
+    return __builtin_riscv_sha512sig1h(rs1, rs2);
+}
+
+int foo4(int rs1, int rs2)
+{
+    return __builtin_riscv_sha512sig1l(rs1, rs2);
+}
+
+int foo5(int rs1, int rs2)
+{
+    return __builtin_riscv_sha512sum0r(rs1, rs2);
+}
+
+int foo6(int rs1, int rs2)
+{
+    return __builtin_riscv_sha512sum1r(rs1, rs2);
+}
+
+/* { dg-final { scan-assembler-times "sha512sig0h" 1 } } */
+/* { dg-final { scan-assembler-times "sha512sig0l" 1 } } */
+/* { dg-final { scan-assembler-times "sha512sig1h" 1 } } */
+/* { dg-final { scan-assembler-times "sha512sig1l" 1 } } */
+/* { dg-final { scan-assembler-times "sha512sum0r" 1 } } */
+/* { dg-final { scan-assembler-times "sha512sum1r" 1 } } */
+
diff --git a/gcc/testsuite/gcc.target/riscv/Zknh-sha512-02.c b/gcc/testsuite/gcc.target/riscv/Zknh-sha512-02.c
new file mode 100644
index 00000000000..f25cbcfb75b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/Zknh-sha512-02.c
@@ -0,0 +1,28 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64i_zknh -mabi=lp64 -O2" } */
+
+long foo1(long rs1)
+{
+    return __builtin_riscv_sha512sig0(rs1);
+}
+
+long foo2(long rs1)
+{
+    return __builtin_riscv_sha512sig1(rs1);
+}
+
+
+long foo3(long rs1)
+{
+    return __builtin_riscv_sha512sum0(rs1);
+}
+
+long foo4(long rs1)
+{
+    return __builtin_riscv_sha512sum1(rs1);
+}
+
+/* { dg-final { scan-assembler-times "sha512sig0" 1 } } */
+/* { dg-final { scan-assembler-times "sha512sig1" 1 } } */
+/* { dg-final { scan-assembler-times "sha512sum0" 1 } } */
+/* { dg-final { scan-assembler-times "sha512sum1" 1 } } */
\ No newline at end of file