[01/21] Fix riscv_expand_block_move

Message ID 20211031093445.1414518-2-siyu@isrc.iscas.ac.cn
State New
Headers
Series RISC-V: add gcc support for Scalar Cryptography v1.0.0-rc5 |

Commit Message

siyu@isrc.iscas.ac.cn Oct. 31, 2021, 9:34 a.m. UTC
  From: linsinan1995 <47880367+linsinan1995@users.noreply.github.com>

---
 gcc/config/riscv/riscv.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
  

Comments

Kito Cheng Nov. 2, 2021, 10:45 a.m. UTC | #1
IIRC this issue should be resolved?

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99314

On Sun, Oct 31, 2021 at 5:34 PM <siyu@isrc.iscas.ac.cn> wrote:
>
> From: linsinan1995 <47880367+linsinan1995@users.noreply.github.com>
>
> ---
>  gcc/config/riscv/riscv.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/gcc/config/riscv/riscv.c b/gcc/config/riscv/riscv.c
> index 6aef3d3a6cf..0529b6d60cd 100644
> --- a/gcc/config/riscv/riscv.c
> +++ b/gcc/config/riscv/riscv.c
> @@ -3491,7 +3491,7 @@ riscv_block_move_loop (rtx dest, rtx src, unsigned HOST_WIDE_INT length,
>  bool
>  riscv_expand_block_move (rtx dest, rtx src, rtx length)
>  {
> -  if (CONST_INT_P (length))
> +  if (CONST_INT_P (length) && INTVAL (length) >= 0)
>      {
>        unsigned HOST_WIDE_INT hwi_length = UINTVAL (length);
>        unsigned HOST_WIDE_INT factor, align;
> --
> 2.25.1
>
  

Patch

diff --git a/gcc/config/riscv/riscv.c b/gcc/config/riscv/riscv.c
index 6aef3d3a6cf..0529b6d60cd 100644
--- a/gcc/config/riscv/riscv.c
+++ b/gcc/config/riscv/riscv.c
@@ -3491,7 +3491,7 @@  riscv_block_move_loop (rtx dest, rtx src, unsigned HOST_WIDE_INT length,
 bool
 riscv_expand_block_move (rtx dest, rtx src, rtx length)
 {
-  if (CONST_INT_P (length))
+  if (CONST_INT_P (length) && INTVAL (length) >= 0)
     {
       unsigned HOST_WIDE_INT hwi_length = UINTVAL (length);
       unsigned HOST_WIDE_INT factor, align;