Show patches with: Search = RISC-V       |    Archived = No       |   3475 patches
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Patch Series rb/tb S/W/F Date Submitter Delegate State
RISC-V: Adjust testcases for AVL=REG support RISC-V: Adjust testcases for AVL=REG support - - --- 2023-01-09 钟居哲 Committed
RISC-V: Fix bugs of supporting AVL=REG (single-real-def) in VSETVL PASS RISC-V: Fix bugs of supporting AVL=REG (single-real-def) in VSETVL PASS - - --- 2023-01-09 钟居哲 Committed
RISC-V: Call DCE to remove redundant instructions created by the PASS RISC-V: Call DCE to remove redundant instructions created by the PASS - - --- 2023-01-09 钟居哲 Dropped
RISC-V: Add probability model of each block to prevent endless loop of Phase 3 RISC-V: Add probability model of each block to prevent endless loop of Phase 3 - - --- 2023-01-09 钟居哲 Committed
RISC-V: Remove dirty_pat since it is redundant RISC-V: Remove dirty_pat since it is redundant - - --- 2023-01-09 钟居哲 Committed
RISC-V: Rename insn into rinsn for rtx_insn * RISC-V: Rename insn into rinsn for rtx_insn * - - --- 2023-01-09 钟居哲 Committed
RISC-V: Avoid redundant flow in backward fusion RISC-V: Avoid redundant flow in backward fusion - - --- 2023-01-09 钟居哲 Dropped
RISC-V: Refine codes in backward fusion RISC-V: Refine codes in backward fusion - - --- 2023-01-09 钟居哲 Committed
RISC-V: Avoid redundant flow in forward fusion RISC-V: Avoid redundant flow in forward fusion - - --- 2023-01-09 钟居哲 Committed
RISC-V: Cleanup the codes of bitmap create and free [NFC] RISC-V: Cleanup the codes of bitmap create and free [NFC] - - --- 2023-01-09 钟居哲 Committed
RISC-V: Fix bugs of available condition. RISC-V: Fix bugs of available condition. - - --- 2023-01-03 钟居哲 Committed
RISC-V: Simplify codes of changing vsetvl instruction RISC-V: Simplify codes of changing vsetvl instruction - - --- 2023-01-03 钟居哲 Committed
RISC-V: Fix backward_propagate_worthwhile_p RISC-V: Fix backward_propagate_worthwhile_p - - --- 2023-01-03 钟居哲 Committed
RISC-V: Fix wrong in_group flag in validate_change call function RISC-V: Fix wrong in_group flag in validate_change call function - - --- 2023-01-03 钟居哲 Committed
RISC-V: Fix bugs for refine vsetvl a5, zero into vsetvl zero, zero incorrectly RISC-V: Fix bugs for refine vsetvl a5, zero into vsetvl zero, zero incorrectly - - --- 2023-01-03 钟居哲 Committed
RISC-V: Fix vsetivli instruction asm for IMM AVL RISC-V: Fix vsetivli instruction asm for IMM AVL - - --- 2023-01-03 钟居哲 Committed
RISC-V: Fix inferior codegen for vse intrinsics. RISC-V: Fix inferior codegen for vse intrinsics. - - --- 2022-12-29 钟居哲 Committed
RISC-V: Fix pointer tree type for store pointer. RISC-V: Fix pointer tree type for store pointer. - - --- 2022-12-28 钟居哲 Committed
[committed] RISC-V: Add riscv_vector.h wrapper [committed] RISC-V: Add riscv_vector.h wrapper - - --- 2022-12-27 Kito Cheng Committed
RISC-V: Return const ref. for vl_vtype_info::get_avl_info RISC-V: Return const ref. for vl_vtype_info::get_avl_info - - --- 2022-12-27 Kito Cheng Committed
RISC-V: Fix ICE of visiting non-existing block in CFG. RISC-V: Fix ICE of visiting non-existing block in CFG. - - --- 2022-12-24 钟居哲 Committed
RISC-V: Fix ICE for avl_info deprecated copy and pp_print error. RISC-V: Fix ICE for avl_info deprecated copy and pp_print error. - - --- 2022-12-23 钟居哲 Committed
RISC-V: Fix vle constraints RISC-V: Fix vle constraints - - --- 2022-12-23 钟居哲 Committed
RISC-V: Support vle.v/vse.v intrinsics RISC-V: Support vle.v/vse.v intrinsics - - --- 2022-12-23 钟居哲 Committed
RISC-V: Update vsetvl/vsetvlmax intrinsics to the latest api name. RISC-V: Update vsetvl/vsetvlmax intrinsics to the latest api name. - - --- 2022-12-20 钟居哲 Committed
RISC-V: Remove side effects of vsetvl pattern in RTL. RISC-V: Remove side effects of vsetvl pattern in RTL. - - --- 2022-12-20 钟居哲 Committed
RISC-V: Remove side effects of vsetvl/vsetvlmax intriniscs in properties RISC-V: Remove side effects of vsetvl/vsetvlmax intriniscs in properties - - --- 2022-12-20 钟居哲 Committed
RISC-V: Fix incorrect annotation RISC-V: Fix incorrect annotation - - --- 2022-12-19 钟居哲 Committed
RISC-V: Fix muti-line condition format RISC-V: Fix muti-line condition format - - --- 2022-12-19 钟居哲 Committed
RISC-V: Remove unit-stride store from ta attribute RISC-V: Remove unit-stride store from ta attribute - - --- 2022-12-14 钟居哲 Committed
RISC-V: Fix RVV machine mode attribute configuration RISC-V: Fix RVV machine mode attribute configuration - - --- 2022-12-14 钟居哲 Committed
RISC-V: Change vlmul printing rule RISC-V: Change vlmul printing rule - - --- 2022-12-14 钟居哲 Committed
[3/3] RISC-V: make the stack manipulation codes more readable. RISC-V: optimize stack manipulation in save-restore - - --- 2022-12-01 Fei Gao Committed
RISC-V: Remove tail && mask policy operand for vmclr, vmset, vmld, vmst RISC-V: Remove tail && mask policy operand for vmclr, vmset, vmld, vmst - - --- 2022-11-29 钟居哲 Committed
RISC-V: Fix up some wording in the mcpu/mtune comment RISC-V: Fix up some wording in the mcpu/mtune comment - - --- 2022-11-28 Palmer Dabbelt Committed
[1/1] RISC-V: fix stack access before allocation. RISC-V: fix stack access before allocation. - - --- 2022-11-28 Fei Gao Committed
[1/1] RISC-V: fix stack access before allocation. RISC-V: fix stack access before allocation. - - --- 2022-11-28 Fei Gao Committed
[committed,RISC-V] Fix recent rvv/base/spill testcase failures [committed,RISC-V] Fix recent rvv/base/spill testcase failures - - --- 2022-11-22 Jeff Law Committed
[PR107786,COMMITTED] RISC-V: Fix ICE in branch<ANYI:mode>_shiftedarith_equals_zero [PR107786,COMMITTED] RISC-V: Fix ICE in branch<ANYI:mode>_shiftedarith_equals_zero - - --- 2022-11-21 Philipp Tomsich Committed
[v2,2/2] RISC-V: Handle "(a & twobits) == singlebit" in branches using Zbs Use Zbs with xori/ori/andi and polarity-reversed twobit-tests - - --- 2022-11-18 Philipp Tomsich Committed
RISC-V: Note that __builtin_riscv_pause() implies Xgnuzihintpausestate RISC-V: Note that __builtin_riscv_pause() implies Xgnuzihintpausestate - - --- 2022-11-18 Palmer Dabbelt Committed
[v3] Enable shrink wrapping for the RISC-V target. [v3] Enable shrink wrapping for the RISC-V target. - - --- 2022-11-17 Manolis Tsamis Committed
[v2] RISC-V: costs: support shift-and-add in strength-reduction [v2] RISC-V: costs: support shift-and-add in strength-reduction - - --- 2022-11-10 Philipp Tomsich Committed
RISC-V: Fix selection of pipeline model for sifive-7-series RISC-V: Fix selection of pipeline model for sifive-7-series - - --- 2022-11-09 Philipp Tomsich Committed
[v2] RISC-V: No extensions for SImode min/max against safe constant [v2] RISC-V: No extensions for SImode min/max against safe constant - - --- 2022-11-09 Philipp Tomsich Committed
RISC-V: allow bseti on SImode without sign-extension RISC-V: allow bseti on SImode without sign-extension - - --- 2022-11-08 Philipp Tomsich Committed
RISC-V: split to allow formation of sh[123]add before divw RISC-V: split to allow formation of sh[123]add before divw - - --- 2022-11-08 Philipp Tomsich Committed
RISC-V: optimize '(a >= 0) ? b : 0' to srai + andn, if compiling for Zbb RISC-V: optimize '(a >= 0) ? b : 0' to srai + andn, if compiling for Zbb - - --- 2022-11-08 Philipp Tomsich Committed
RISC-V: costs: handle BSWAP RISC-V: costs: handle BSWAP - - --- 2022-11-08 Philipp Tomsich Committed
RISC-V: Fix RVV related testsuite RISC-V: Fix RVV related testsuite - - --- 2022-11-06 Kito Cheng Committed
[v5] RISC-V: Libitm add RISC-V support. [v5] RISC-V: Libitm add RISC-V support. 1 - --- 2022-10-29 Xiongchuan Tan Committed
RISC-V: Add Zawrs ISA extension support RISC-V: Add Zawrs ISA extension support - - --- 2022-10-27 Christoph Müllner Committed
RISC-V: Change constexpr back to CONSTEXPR RISC-V: Change constexpr back to CONSTEXPR - - --- 2022-10-27 钟居哲 Committed
RISC-V: ADJUST_NUNITS according to -march. RISC-V: ADJUST_NUNITS according to -march. - - --- 2022-10-25 钟居哲 Committed
RISC-V: Fix typo. RISC-V: Fix typo. - - --- 2022-10-24 钟居哲 Committed
RISC-V: Replace CONSTEXPR with constexpr RISC-V: Replace CONSTEXPR with constexpr - - --- 2022-10-24 钟居哲 Committed
RISC-V: Remove unused TI/TF vector modes. RISC-V: Remove unused TI/TF vector modes. - - --- 2022-10-24 钟居哲 Committed
RISC-V: Fix REG_CLASS_CONTENTS. RISC-V: Fix REG_CLASS_CONTENTS. - - --- 2022-10-24 钟居哲 Committed
RISC-V: Add type attribute for atomic instructions. RISC-V: Add type attribute for atomic instructions. - - --- 2022-10-21 Monk Chiang Committed
[v4,4/4] RISC-V: Add zhinx/zhinxmin testcases. RISC-V: Support z*inx extensions. - - --- 2022-10-20 Jiawei Committed
[v4,2/4] RISC-V: Target support for z*inx extension. RISC-V: Support z*inx extensions. - - --- 2022-10-20 Jiawei Committed
[v4,1/4] RISC-V: Minimal support of z*inx extension. RISC-V: Support z*inx extensions. - - --- 2022-10-20 Jiawei Committed
RISC-V: Add RVV vsetvl/vsetvlmax intrinsics and tests. RISC-V: Add RVV vsetvl/vsetvlmax intrinsics and tests. - - --- 2022-10-17 钟居哲 Committed
RISC-V: Fix format[NFC] RISC-V: Fix format[NFC] - - --- 2022-10-17 钟居哲 Committed
RISC-V: Reorganize mangle_builtin_type.[NFC] RISC-V: Reorganize mangle_builtin_type.[NFC] - - --- 2022-10-14 钟居哲 Committed
RISC-V: Remove TUPLE size macro define. RISC-V: Remove TUPLE size macro define. - - --- 2022-10-11 钟居哲 Committed
RISC-V: move struct vector_type_info from *.h to *.cc and change "user_name" into "name". RISC-V: move struct vector_type_info from *.h to *.cc and change "user_name" into "name". - - --- 2022-10-10 钟居哲 Committed
RISC-V: Add missing vsetvl instruction type. RISC-V: Add missing vsetvl instruction type. - - --- 2022-10-10 钟居哲 Committed
[committed] RISC-V: Add riscv_vector.h wrapper in testsuite to prevent pull in stdint.h from C libr… [committed] RISC-V: Add riscv_vector.h wrapper in testsuite to prevent pull in stdint.h from C libr… 1 1 --- 2022-10-10 钟居哲 Committed
[committed] RISC-V: Adjust testcase for rvv/base/user-1.c [committed] RISC-V: Adjust testcase for rvv/base/user-1.c 1 1 --- 2022-10-10 钟居哲 Committed
[committed] RISC-V: Add riscv_vector.h wrapper in testsuite to prevent pull in stdint.h from C libr… [committed] RISC-V: Add riscv_vector.h wrapper in testsuite to prevent pull in stdint.h from C libr… 2 2 --- 2022-10-10 Kito Cheng Committed
[committed] RISC-V: Adjust testcase for rvv/base/user-1.c [committed] RISC-V: Adjust testcase for rvv/base/user-1.c 2 2 --- 2022-10-10 Kito Cheng Committed
[committed] RISC-V: Add newline to the end of file [NFC] [committed] RISC-V: Add newline to the end of file [NFC] - - --- 2022-10-10 Kito Cheng Committed
RISC-V: Introduce RVV header to enable builtin types RISC-V: Introduce RVV header to enable builtin types - - --- 2022-09-30 钟居哲 Committed
RISC-V: Support --target-help for -mcpu/-mtune RISC-V: Support --target-help for -mcpu/-mtune - - --- 2022-09-30 Kito Cheng Committed
Fix typo in chapter level for RISC-V attributes Fix typo in chapter level for RISC-V attributes - - --- 2022-09-23 Torbjorn SVENSSON Committed
RISC-V: Add RVV machine modes. RISC-V: Add RVV machine modes. - - --- 2022-09-15 钟居哲 Committed
[committed] RISC-V: Suppress build warnings [committed] RISC-V: Suppress build warnings - - --- 2022-09-09 Kito Cheng Committed
RISC-V: Support -fexcess-precision=16 RISC-V: Support -fexcess-precision=16 - - --- 2022-09-09 Palmer Dabbelt Committed
RISC-V: Don't try to vectorize tree-ssa/gen-vect-34.c RISC-V: Don't try to vectorize tree-ssa/gen-vect-34.c - - --- 2022-09-03 Palmer Dabbelt Committed
[v3] RISC-V: remove deprecate pic code model macro [v3] RISC-V: remove deprecate pic code model macro - - --- 2022-09-02 Vineet Gupta Committed
RISC-V: Add RVV registers in TARGET_CONDITION_AL_REGISTER_USAGE RISC-V: Add RVV registers in TARGET_CONDITION_AL_REGISTER_USAGE - - --- 2022-08-30 钟居哲 Committed
RISC-V: Add RVV constraints. RISC-V: Add RVV constraints. - - --- 2022-08-30 钟居哲 Committed
RISC-V: Fix annotation RISC-V: Fix annotation - - --- 2022-08-30 钟居哲 Committed
[committed] RISC-V: Suppress -Wclass-memaccess warning [committed] RISC-V: Suppress -Wclass-memaccess warning - - --- 2022-08-29 Kito Cheng Committed
RISC-V: Add RVV instructions classification RISC-V: Add RVV instructions classification - - --- 2022-08-27 钟居哲 Committed
[v2,2/2] RISC-V: Support zfh and zfhmin extension [v2,1/2] RISC-V: Support _Float16 type. - - --- 2022-08-10 Kito Cheng Committed
[v2,1/2] RISC-V: Support _Float16 type. [v2,1/2] RISC-V: Support _Float16 type. - - --- 2022-08-10 Kito Cheng Committed
RISC-V/testsuite: Restrict remaining `fmin'/`fmax' tests to hard float RISC-V/testsuite: Restrict remaining `fmin'/`fmax' tests to hard float - - --- 2022-07-28 Maciej W. Rozycki Committed
RISC-V: Standardize formatting of SFB ALU conditional move RISC-V: Standardize formatting of SFB ALU conditional move - - --- 2022-07-26 Maciej W. Rozycki Committed
RISC-V: Remove duplicate backslashes from `stack_protect_set_<mode>' RISC-V: Remove duplicate backslashes from `stack_protect_set_<mode>' - - --- 2022-07-26 Maciej W. Rozycki Committed
RISC-V: Add RTX costs for `if_then_else' expressions RISC-V: Add RTX costs for `if_then_else' expressions - - --- 2022-07-18 Maciej W. Rozycki Committed
[committed] RISC-V/doc: Add index references for `mrelax' and `mriscv-attribute' [committed] RISC-V/doc: Add index references for `mrelax' and `mriscv-attribute' - - --- 2022-07-18 Maciej W. Rozycki Committed
[committed] RISC-V/doc: Correct the formatting of `-mstack-protector-guard-reg=' [committed] RISC-V/doc: Correct the formatting of `-mstack-protector-guard-reg=' - - --- 2022-07-18 Maciej W. Rozycki Committed
[committed] RISC-V/doc: Correct the name of `-mriscv-attribute' [committed] RISC-V/doc: Correct the name of `-mriscv-attribute' - - --- 2022-07-18 Maciej W. Rozycki Committed
RISC-V: Reset the length to the default of 4 for FP comparisons RISC-V: Reset the length to the default of 4 for FP comparisons - - --- 2022-06-09 Maciej W. Rozycki Committed
[committed] RISC-V: Use a tab rather than space with FSFLAGS [committed] RISC-V: Use a tab rather than space with FSFLAGS - - --- 2022-06-09 Maciej W. Rozycki Committed
RISC-V/testsuite: Fix pr105666.c under rv32 RISC-V/testsuite: Fix pr105666.c under rv32 - - --- 2022-06-08 Jiawei Committed
[RFC] RISC-V: Add Zawrs ISA extension support [RFC] RISC-V: Add Zawrs ISA extension support - - --- 2022-06-01 Christoph Müllner Committed
[00/34] RISC-V: Add RVV (RISC-V 'V' Extension) support - - --- 2022-06-01 钟居哲 None
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