RISC-V: Add RVV registers in TARGET_CONDITION_AL_REGISTER_USAGE
Commit Message
From: zhongjuzhe <juzhe.zhong@rivai.ai>
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_conditional_register_usage): Add RVV registers.
---
gcc/config/riscv/riscv.cc | 9 +++++++++
1 file changed, 9 insertions(+)
Comments
Committed with title fix, that should be TARGET_CONDITIONAL_REGISTER_USAGE
On Tue, Aug 30, 2022 at 2:28 PM <juzhe.zhong@rivai.ai> wrote:
>
> From: zhongjuzhe <juzhe.zhong@rivai.ai>
>
> gcc/ChangeLog:
>
> * config/riscv/riscv.cc (riscv_conditional_register_usage): Add RVV registers.
>
> ---
> gcc/config/riscv/riscv.cc | 9 +++++++++
> 1 file changed, 9 insertions(+)
>
> diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
> index 50de6a83cba..aebe3c0ab6b 100644
> --- a/gcc/config/riscv/riscv.cc
> +++ b/gcc/config/riscv/riscv.cc
> @@ -5439,6 +5439,15 @@ riscv_conditional_register_usage (void)
> for (int regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno++)
> call_used_regs[regno] = 1;
> }
> +
> + if (!TARGET_VECTOR)
> + {
> + for (int regno = V_REG_FIRST; regno <= V_REG_LAST; regno++)
> + fixed_regs[regno] = call_used_regs[regno] = 1;
> +
> + fixed_regs[VTYPE_REGNUM] = call_used_regs[VTYPE_REGNUM] = 1;
> + fixed_regs[VL_REGNUM] = call_used_regs[VL_REGNUM] = 1;
> + }
> }
>
> /* Return a register priority for hard reg REGNO. */
> --
> 2.36.1
>
@@ -5439,6 +5439,15 @@ riscv_conditional_register_usage (void)
for (int regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno++)
call_used_regs[regno] = 1;
}
+
+ if (!TARGET_VECTOR)
+ {
+ for (int regno = V_REG_FIRST; regno <= V_REG_LAST; regno++)
+ fixed_regs[regno] = call_used_regs[regno] = 1;
+
+ fixed_regs[VTYPE_REGNUM] = call_used_regs[VTYPE_REGNUM] = 1;
+ fixed_regs[VL_REGNUM] = call_used_regs[VL_REGNUM] = 1;
+ }
}
/* Return a register priority for hard reg REGNO. */