Show patches with: Submitter = Philipp Tomsich       |    State = Action Required       |    Archived = No       |   72 patches
Patch Series rb/tb S/W/F Date Submitter Delegate State
aarch64: update ampere1 vectorization cost aarch64: update ampere1 vectorization cost - - --- 2023-03-27 Philipp Tomsich New
[RFC,v1,10/10] RISC-V: Support XVentanaCondOps extension RISC-V: Support the Zicond (conditional-operations) extension - - --- 2023-02-10 Philipp Tomsich New
[RFC,v1,09/10] RISC-V: Recognize xventanacondops extension RISC-V: Support the Zicond (conditional-operations) extension - - --- 2023-02-10 Philipp Tomsich New
[RFC,v1,08/10] ifcvt: add if-conversion to conditional-zero instructions RISC-V: Support the Zicond (conditional-operations) extension - - --- 2023-02-10 Philipp Tomsich New
[RFC,v1,07/10] RISC-V: Recognize bexti in negated if-conversion RISC-V: Support the Zicond (conditional-operations) extension - - --- 2023-02-10 Philipp Tomsich New
[RFC,v1,06/10] RISC-V: Recognize sign-extract + and cases for czero.eqz/nez RISC-V: Support the Zicond (conditional-operations) extension - - --- 2023-02-10 Philipp Tomsich New
[RFC,v1,05/10] RISC-V: Support noce_try_store_flag_mask as czero.eqz/czero.nez RISC-V: Support the Zicond (conditional-operations) extension - - --- 2023-02-10 Philipp Tomsich New
[RFC,v1,04/10] RISC-V: Support immediates in Zicond RISC-V: Support the Zicond (conditional-operations) extension - - --- 2023-02-10 Philipp Tomsich New
[RFC,v1,03/10] RISC-V: Generate czero.eqz/nez on noce_try_store_flag_mask if-conversion RISC-V: Support the Zicond (conditional-operations) extension - - --- 2023-02-10 Philipp Tomsich New
[RFC,v1,02/10] RISC-V: Recognize Zicond (conditional operations) extension RISC-V: Support the Zicond (conditional-operations) extension - - --- 2023-02-10 Philipp Tomsich New
[RFC,v1,01/10] docs: Document a canonical RTL for a conditional-zero insns RISC-V: Support the Zicond (conditional-operations) extension - - --- 2023-02-10 Philipp Tomsich New
[v2,1/2] RISC-V: Use bseti/bclri/binvi to extend reach of ori/andi/xori Use Zbs with xori/ori/andi and polarity-reversed twobit-tests - - --- 2022-11-18 Philipp Tomsich New
[v2,8/8] ifcvt: add if-conversion to conditional-zero instructions RISC-V: Backend support for XVentanaCondOps/ZiCondops - - --- 2022-11-13 Philipp Tomsich New
[v2,7/8] RISC-V: Ventana-VT1 supports XVentanaCondOps RISC-V: Backend support for XVentanaCondOps/ZiCondops - - --- 2022-11-13 Philipp Tomsich New
[v2,6/8] RISC-V: Support immediates in XVentanaCondOps RISC-V: Backend support for XVentanaCondOps/ZiCondops 1 - --- 2022-11-13 Philipp Tomsich New
[v2,5/8] RISC-V: Recognize bexti in negated if-conversion RISC-V: Backend support for XVentanaCondOps/ZiCondops - - --- 2022-11-13 Philipp Tomsich New
[v2,4/8] RISC-V: Recognize sign-extract + and cases for XVentanaCondOps RISC-V: Backend support for XVentanaCondOps/ZiCondops - - --- 2022-11-13 Philipp Tomsich New
[v2,3/8] RISC-V: Support noce_try_store_flag_mask as vt.maskc<n> RISC-V: Backend support for XVentanaCondOps/ZiCondops - - --- 2022-11-13 Philipp Tomsich New
[v2,2/8] RISC-V: Generate vt.maskc<n> on noce_try_store_flag_mask if-conversion RISC-V: Backend support for XVentanaCondOps/ZiCondops - - --- 2022-11-13 Philipp Tomsich New
[v2,1/8] RISC-V: Recognize xventanacondops extension RISC-V: Backend support for XVentanaCondOps/ZiCondops - - --- 2022-11-13 Philipp Tomsich New
RISC-V: Handle "(a & twobits) == singlebit" in branches using Zbs RISC-V: Handle "(a & twobits) == singlebit" in branches using Zbs - - --- 2022-11-13 Philipp Tomsich New
RISC-V: Split "(a & (1UL << bitno)) ? 0 : 1" to bext + xori RISC-V: Split "(a & (1UL << bitno)) ? 0 : 1" to bext + xori - - --- 2022-11-13 Philipp Tomsich New
RISC-V: Split "(a & (1UL << bitno)) ? 0 : -1" to bext + addi RISC-V: Split "(a & (1UL << bitno)) ? 0 : -1" to bext + addi - - --- 2022-11-13 Philipp Tomsich New
[v2,2/2] RISC-V: Add instruction fusion (for ventana-vt1) Basic support for the Ventana VT1 w/ instruction fusion - - --- 2022-11-13 Philipp Tomsich New
[v2,1/2] RISC-V: Add basic support for the Ventana-VT1 core Basic support for the Ventana VT1 w/ instruction fusion - - --- 2022-11-13 Philipp Tomsich New
RISC-V: Zihintpause: add __builtin_riscv_pause RISC-V: Zihintpause: add __builtin_riscv_pause - - --- 2022-11-13 Philipp Tomsich New
RISC-V: Use .p2align for code-alignment RISC-V: Use .p2align for code-alignment - - --- 2022-11-13 Philipp Tomsich New
[7/7] ifcvt: add if-conversion to conditional-zero instructions RISC-V: Backend support for XVentanaCondOps/ZiCondops - - --- 2022-11-12 Philipp Tomsich New
[6/7] RISC-V: Support immediates in XVentanaCondOps RISC-V: Backend support for XVentanaCondOps/ZiCondops 1 - --- 2022-11-12 Philipp Tomsich New
[5/7] RISC-V: Recognize bexti in negated if-conversion RISC-V: Backend support for XVentanaCondOps/ZiCondops - - --- 2022-11-12 Philipp Tomsich New
[4/7] RISC-V: Recognize sign-extract + and cases for XVentanaCondOps RISC-V: Backend support for XVentanaCondOps/ZiCondops - - --- 2022-11-12 Philipp Tomsich New
[3/7] RISC-V: Support noce_try_store_flag_mask as vt.maskc<n> RISC-V: Backend support for XVentanaCondOps/ZiCondops - - --- 2022-11-12 Philipp Tomsich New
[2/7] RISC-V: Generate vt.maskc<n> on noce_try_store_flag_mask if-conversion RISC-V: Backend support for XVentanaCondOps/ZiCondops - - --- 2022-11-12 Philipp Tomsich New
[1/7] RISC-V: Recognize xventanacondops extension RISC-V: Backend support for XVentanaCondOps/ZiCondops - - --- 2022-11-12 Philipp Tomsich New
RISC-V: Optimize masking with two clear bits not a SMALL_OPERAND RISC-V: Optimize masking with two clear bits not a SMALL_OPERAND - - --- 2022-11-10 Philipp Tomsich New
RISC-V: Use binvi to cover more immediates than with xori alone RISC-V: Use binvi to cover more immediates than with xori alone - - --- 2022-11-10 Philipp Tomsich New
RISC-V: Use bseti to cover more immediates than with ori alone RISC-V: Use bseti to cover more immediates than with ori alone - - --- 2022-11-10 Philipp Tomsich New
[v3] RISC-V: Replace zero_extendsidi2_shifted with generalized split [v3] RISC-V: Replace zero_extendsidi2_shifted with generalized split - - --- 2022-11-09 Philipp Tomsich New
[v2,WIP] RISC-V: Replace zero_extendsidi2_shifted with generalized split [v2,WIP] RISC-V: Replace zero_extendsidi2_shifted with generalized split - - --- 2022-11-09 Philipp Tomsich New
ifcombine: fold two bit tests with different polarity ifcombine: fold two bit tests with different polarity - - --- 2022-11-09 Philipp Tomsich New
ifcombine: recognize single bit test of sign-bit ifcombine: recognize single bit test of sign-bit - - --- 2022-11-09 Philipp Tomsich New
RISC-V: Implement movmisalign<mode> to enable SLP RISC-V: Implement movmisalign<mode> to enable SLP - - --- 2022-11-09 Philipp Tomsich New
RISC-V: Optimise adding a (larger than simm12) constant RISC-V: Optimise adding a (larger than simm12) constant - - --- 2022-11-09 Philipp Tomsich New
RISC-V: No extensions for SImode min/max against safe constant RISC-V: No extensions for SImode min/max against safe constant - - --- 2022-11-08 Philipp Tomsich New
RISC-V: Optimize branches testing a bit-range or a shifted immediate RISC-V: Optimize branches testing a bit-range or a shifted immediate - - --- 2022-11-08 Philipp Tomsich New
RISC-V: Optimize slli(.uw)? + addw + zext.w into sh[123]add + zext.w RISC-V: Optimize slli(.uw)? + addw + zext.w into sh[123]add + zext.w - - --- 2022-11-08 Philipp Tomsich New
RISC-V: bitmanip: use bexti for "(a & (1 << BIT_NO)) ? 0 : -1" RISC-V: bitmanip: use bexti for "(a & (1 << BIT_NO)) ? 0 : -1" - - --- 2022-11-08 Philipp Tomsich New
RISC-V: branch-(not)equals-zero compares against $zero RISC-V: branch-(not)equals-zero compares against $zero - - --- 2022-11-08 Philipp Tomsich New
RISC-V: costs: support shift-and-add in strength-reduction RISC-V: costs: support shift-and-add in strength-reduction - - --- 2022-11-08 Philipp Tomsich New
[v2] aarch64: fix off-by-one in reading cpuinfo [v2] aarch64: fix off-by-one in reading cpuinfo - - --- 2022-10-06 Philipp Tomsich New
aarch64: fix off-by-one in reading cpuinfo aarch64: fix off-by-one in reading cpuinfo - - --- 2022-10-03 Philipp Tomsich New
aarch64: update Ampere-1 core definition aarch64: update Ampere-1 core definition - - --- 2022-10-03 Philipp Tomsich New
riscv: implement TARGET_MODE_REP_EXTENDED riscv: implement TARGET_MODE_REP_EXTENDED - - --- 2022-09-05 Philipp Tomsich New
[v1] RISC-V: bitmanip: improve constant-loading for (1ULL << 31) in DImode [v1] RISC-V: bitmanip: improve constant-loading for (1ULL << 31) in DImode - - --- 2022-05-24 Philipp Tomsich New
[v1,3/3] RISC-V: Split "(a & (1UL << bitno)) ? 0 : 1" to bext + xori [v1,1/3] RISC-V: Split "(a & (1 << BIT_NO)) ? 0 : -1" to bexti + addi - - --- 2022-05-24 Philipp Tomsich New
[v1,2/3] RISC-V: Split "(a & (1UL << bitno)) ? 0 : -1" to bext + addi [v1,1/3] RISC-V: Split "(a & (1 << BIT_NO)) ? 0 : -1" to bexti + addi - - --- 2022-05-24 Philipp Tomsich New
[v1,1/3] RISC-V: Split "(a & (1 << BIT_NO)) ? 0 : -1" to bexti + addi [v1,1/3] RISC-V: Split "(a & (1 << BIT_NO)) ? 0 : -1" to bexti + addi - - --- 2022-05-24 Philipp Tomsich New
[v1,3/3] RISC-V: Replace zero_extendsidi2_shifted with generalized split RISC-V: Improve sequences with shifted zero-extended operands - - --- 2022-05-24 Philipp Tomsich New
[v2] RISC-V: Implement C[LT]Z_DEFINED_VALUE_AT_ZERO [v2] RISC-V: Implement C[LT]Z_DEFINED_VALUE_AT_ZERO 1 - --- 2022-05-12 Philipp Tomsich New
[v1] RISC-V: Implement C[LT]Z_DEFINED_VALUE_AT_ZERO [v1] RISC-V: Implement C[LT]Z_DEFINED_VALUE_AT_ZERO - - --- 2022-04-23 Philipp Tomsich New
[GCC-10] aarch64: enable Ampere-1 CPU [GCC-10] aarch64: enable Ampere-1 CPU - - --- 2021-12-16 Philipp Tomsich New
[GCC-11] aarch64: enable Ampere-1 CPU (backport to GCC11) [GCC-11] aarch64: enable Ampere-1 CPU (backport to GCC11) - - --- 2021-11-15 Philipp Tomsich New
[v1,2/2] RISC-V: Add instruction fusion (for ventana-vt1) Basic support for the Ventana VT1 w/ instruction fusion - - --- 2021-11-14 Philipp Tomsich New
[v1,1/2] RISC-V: Add basic support for the Ventana-VT1 core Basic support for the Ventana VT1 w/ instruction fusion - - --- 2021-11-14 Philipp Tomsich New
[v1,8/8] RISC-V: bitmanip: relax minmax to operate on GPR Improvements to bitmanip-1.0 (Zb[abcs]) support - - --- 2021-11-11 Philipp Tomsich New
[v1,7/8] RISC-V: bitmanip: add orc.b as an unspec Improvements to bitmanip-1.0 (Zb[abcs]) support - - --- 2021-11-11 Philipp Tomsich New
[v1,6/8] RISC-V: bitmanip: add splitter to use bexti for "(a & (1 << BIT_NO)) ? 0 : -1" Improvements to bitmanip-1.0 (Zb[abcs]) support - - --- 2021-11-11 Philipp Tomsich New
[v1,5/8] RISC-V: bitmanip: improvements to rotate instructions Improvements to bitmanip-1.0 (Zb[abcs]) support - - --- 2021-11-11 Philipp Tomsich New
[v1,4/8] RISC-V: bitmanip: fix constant-loading for (1ULL << 31) in DImode Improvements to bitmanip-1.0 (Zb[abcs]) support - - --- 2021-11-11 Philipp Tomsich New
[v1,3/8] RISC-V: costs: support shift-and-add in strength-reduction Improvements to bitmanip-1.0 (Zb[abcs]) support - - --- 2021-11-11 Philipp Tomsich New
[v1,2/8] RISC-V: costs: handle BSWAP Improvements to bitmanip-1.0 (Zb[abcs]) support - - --- 2021-11-11 Philipp Tomsich New
[v1,1/8] bswap: synthesize HImode bswap from SImode or DImode Improvements to bitmanip-1.0 (Zb[abcs]) support - - --- 2021-11-11 Philipp Tomsich New