RISC-V: Adjust testcases for AVL=REG support

  From: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>

gcc/testsuite/ChangeLog:

        * gcc.target/riscv/rvv/vsetvl/imm_bb_prop-3.c: Adjust testcase.
        * gcc.target/riscv/rvv/vsetvl/imm_bb_prop-4.c: Ditto.
        * gcc.target/riscv/rvv/vsetvl/imm_conflict-4.c: Ditto.
        * gcc.target/riscv/rvv/vsetvl/imm_conflict-5.c: Ditto.
        * gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-17.c: Ditto.
        * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-27.c: Ditto.
        * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-28.c: Ditto.
        * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-45.c: Ditto.
        * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-25.c: Ditto.
        * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-26.c: Ditto.
        * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-27.c: Ditto.
        * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-28.c: Ditto.
        * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-3.c: Ditto.
        * gcc.target/riscv/rvv/vsetvl/vlmax_conflict-7.c: Ditto.
        * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-12.c: Ditto.

---
 .../gcc.target/riscv/rvv/vsetvl/imm_bb_prop-3.c    |  2 +-
 .../gcc.target/riscv/rvv/vsetvl/imm_bb_prop-4.c    |  2 +-
 .../gcc.target/riscv/rvv/vsetvl/imm_conflict-4.c   | 12 ++++++------
 .../gcc.target/riscv/rvv/vsetvl/imm_conflict-5.c   | 12 ++++++------
 .../riscv/rvv/vsetvl/imm_loop_invariant-17.c       |  3 +--
 .../riscv/rvv/vsetvl/vlmax_back_prop-27.c          |  4 ++--
 .../riscv/rvv/vsetvl/vlmax_back_prop-28.c          |  4 ++--
 .../riscv/rvv/vsetvl/vlmax_back_prop-45.c          |  2 +-
 .../gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-25.c | 14 +++++++-------
 .../gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-26.c | 12 ++++++------
 .../gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-27.c | 12 ++++++------
 .../gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-28.c |  2 +-
 .../gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-3.c  |  2 +-
 .../gcc.target/riscv/rvv/vsetvl/vlmax_conflict-7.c |  1 -
 .../riscv/rvv/vsetvl/vlmax_switch_vtype-12.c       |  2 +-
 15 files changed, 42 insertions(+), 44 deletions(-)
  

committed, thanks.

On Tue, Jan 10, 2023 at 7:36 AM <juzhe.zhong@rivai.ai> wrote:

> From: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
>
> gcc/testsuite/ChangeLog:
>
>         * gcc.target/riscv/rvv/vsetvl/imm_bb_prop-3.c: Adjust testcase.
>         * gcc.target/riscv/rvv/vsetvl/imm_bb_prop-4.c: Ditto.
>         * gcc.target/riscv/rvv/vsetvl/imm_conflict-4.c: Ditto.
>         * gcc.target/riscv/rvv/vsetvl/imm_conflict-5.c: Ditto.
>         * gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-17.c: Ditto.
>         * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-27.c: Ditto.
>         * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-28.c: Ditto.
>         * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-45.c: Ditto.
>         * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-25.c: Ditto.
>         * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-26.c: Ditto.
>         * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-27.c: Ditto.
>         * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-28.c: Ditto.
>         * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-3.c: Ditto.
>         * gcc.target/riscv/rvv/vsetvl/vlmax_conflict-7.c: Ditto.
>         * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-12.c: Ditto.
>
> ---
>  .../gcc.target/riscv/rvv/vsetvl/imm_bb_prop-3.c    |  2 +-
>  .../gcc.target/riscv/rvv/vsetvl/imm_bb_prop-4.c    |  2 +-
>  .../gcc.target/riscv/rvv/vsetvl/imm_conflict-4.c   | 12 ++++++------
>  .../gcc.target/riscv/rvv/vsetvl/imm_conflict-5.c   | 12 ++++++------
>  .../riscv/rvv/vsetvl/imm_loop_invariant-17.c       |  3 +--
>  .../riscv/rvv/vsetvl/vlmax_back_prop-27.c          |  4 ++--
>  .../riscv/rvv/vsetvl/vlmax_back_prop-28.c          |  4 ++--
>  .../riscv/rvv/vsetvl/vlmax_back_prop-45.c          |  2 +-
>  .../gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-25.c | 14 +++++++-------
>  .../gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-26.c | 12 ++++++------
>  .../gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-27.c | 12 ++++++------
>  .../gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-28.c |  2 +-
>  .../gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-3.c  |  2 +-
>  .../gcc.target/riscv/rvv/vsetvl/vlmax_conflict-7.c |  1 -
>  .../riscv/rvv/vsetvl/vlmax_switch_vtype-12.c       |  2 +-
>  15 files changed, 42 insertions(+), 44 deletions(-)
>
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-3.c
> b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-3.c
> index 3da7b8722c2..20a1cd27c43 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-3.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-3.c
> @@ -19,4 +19,4 @@ void f(void *base, void *out, void *mask_in, size_t vl,
> size_t m) {
>    }
>  }
>
> -/* { dg-final { scan-assembler-times
> {vsetivli\s+zero,\s*4,\s*e8,\s*mf8,\s*tu,\s*mu} 1 { target { no-opts "-O0"
> no-opts "-O1" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */
> +/* { dg-final { scan-assembler-times
> {vsetivli\s+zero,\s*4,\s*e16,\s*mf4,\s*tu,\s*mu} 1 { target { no-opts "-O0"
> no-opts "-O1" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-4.c
> b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-4.c
> index 2a9616eb7ea..58aecb0a219 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-4.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-4.c
> @@ -21,5 +21,5 @@ void f(void *base, void *out, void *mask_in, size_t vl,
> size_t m, size_t n) {
>    }
>  }
>
> -/* { dg-final { scan-assembler-times
> {vsetivli\s+zero,\s*4,\s*e8,\s*mf8,\s*tu,\s*mu} 1 { target { no-opts "-O0"
> no-opts "-O1" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */
> +/* { dg-final { scan-assembler-times
> {vsetivli\s+zero,\s*4,\s*e16,\s*mf4,\s*tu,\s*mu} 1 { target { no-opts "-O0"
> no-opts "-O1" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */
>
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_conflict-4.c
> b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_conflict-4.c
> index f24e129b4dc..fdfcb07a63d 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_conflict-4.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_conflict-4.c
> @@ -30,9 +30,9 @@ void f (void * restrict in, void * restrict out, int n,
> int cond)
>    }
>  }
>
> -/* { dg-final { scan-assembler-times
> {vsetivli\s+zero,\s*5,\s*e8,\s*mf8,\s*tu,\s*m[au]} 1 { target { no-opts
> "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
> -/* { dg-final { scan-assembler-times
> {vsetivli\s+zero,\s*19,\s*e32,\s*m1,\s*t[au],\s*m[au]} 1 { target { no-opts
> "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
> -/* { dg-final { scan-assembler-times
> {vsetivli\s+zero,\s*8,\s*e32,\s*m1,\s*t[au],\s*m[au]} 1 { target { no-opts
> "-O0" no-opts "-O1" no-opts "-g" no-opts "-funroll-loops" } } } } */
> -/* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 1 { target {
> no-opts "-O0"  no-opts "-funroll-loops" no-opts "-g" } } } } */
> -/* { dg-final { scan-assembler-times {vsetivli} 3 { target { no-opts
> "-O0" no-opts "-O1" no-opts "-funroll-loops" no-opts "-g" } } } } */
> -/* { dg-final { scan-assembler-times {vsetvli} 1 { target { no-opts
> "-O0"  no-opts "-funroll-loops" no-opts "-g" } } } } */
> +/* { dg-final { scan-assembler-times
> {vsetivli\s+zero,\s*5,\s*e8,\s*mf8,\s*tu,\s*m[au]} 1 { target { no-opts
> "-O0" no-opts "-O1" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } }
> } } */
> +/* { dg-final { scan-assembler-times
> {vsetivli\s+zero,\s*19,\s*e32,\s*m1,\s*t[au],\s*m[au]} 2 { target { no-opts
> "-O0" no-opts "-O1" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } }
> } } */
> +/* { dg-final { scan-assembler-times
> {vsetivli\s+zero,\s*8,\s*e32,\s*m1,\s*t[au],\s*m[au]} 2 { target { no-opts
> "-O0" no-opts "-O1" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } }
> } } */
> +/* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 1 { target {
> no-opts "-O0" no-opts "-O1" no-opts "-Os"  no-opts "-funroll-loops" no-opts
> "-g" } } } } */
> +/* { dg-final { scan-assembler-times {vsetivli} 5 { target { no-opts
> "-O0" no-opts "-O1" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } }
> } } */
> +/* { dg-final { scan-assembler-times {vsetvli} 1 { target { no-opts "-O0"
> no-opts "-O1" no-opts "-Os"  no-opts "-funroll-loops" no-opts "-g" } } } }
> */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_conflict-5.c
> b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_conflict-5.c
> index 02bc648cc34..3e109c0c86a 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_conflict-5.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_conflict-5.c
> @@ -37,9 +37,9 @@ void f (void * restrict in, void * restrict out, int n,
> int cond)
>    }
>  }
>
> -/* { dg-final { scan-assembler-times
> {vsetivli\s+zero,\s*5,\s*e8,\s*mf8,\s*tu,\s*m[au]} 1 { target { no-opts
> "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
> -/* { dg-final { scan-assembler-times
> {vsetivli\s+zero,\s*19,\s*e32,\s*m1,\s*t[au],\s*m[au]} 1 { target { no-opts
> "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
> -/* { dg-final { scan-assembler-times
> {vsetivli\s+zero,\s*8,\s*e32,\s*m1,\s*t[au],\s*m[au]} 1 { target { no-opts
> "-O0" no-opts "-O1" no-opts "-g" no-opts "-funroll-loops" } } } } */
> -/* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 1 { target {
> no-opts "-O0"  no-opts "-funroll-loops" no-opts "-g" } } } } */
> -/* { dg-final { scan-assembler-times {vsetivli} 3 { target { no-opts
> "-O0" no-opts "-O1" no-opts "-funroll-loops" no-opts "-g" } } } } */
> -/* { dg-final { scan-assembler-times {vsetvli} 1 { target { no-opts
> "-O0"  no-opts "-funroll-loops" no-opts "-g" } } } } */
> +/* { dg-final { scan-assembler-times
> {vsetivli\s+zero,\s*5,\s*e8,\s*mf8,\s*tu,\s*m[au]} 1 { target { no-opts
> "-O0" no-opts "-O1" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } }
> } } */
> +/* { dg-final { scan-assembler-times
> {vsetivli\s+zero,\s*19,\s*e32,\s*m1,\s*t[au],\s*m[au]} 2 { target { no-opts
> "-O0" no-opts "-O1" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } }
> } } */
> +/* { dg-final { scan-assembler-times
> {vsetivli\s+zero,\s*8,\s*e32,\s*m1,\s*t[au],\s*m[au]} 2 { target { no-opts
> "-O0" no-opts "-O1" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } }
> } } */
> +/* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 1 { target {
> no-opts "-O0" no-opts "-O1" no-opts "-Os"  no-opts "-funroll-loops" no-opts
> "-g" } } } } */
> +/* { dg-final { scan-assembler-times {vsetivli} 5 { target { no-opts
> "-O0" no-opts "-O1" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } }
> } } */
> +/* { dg-final { scan-assembler-times {vsetvli} 1 { target { no-opts "-O0"
> no-opts "-O1" no-opts "-Os"  no-opts "-funroll-loops" no-opts "-g" } } } }
> */
> diff --git
> a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-17.c
> b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-17.c
> index fcf0a8c4aeb..a8c19a24fe5 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-17.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-17.c
> @@ -19,5 +19,4 @@ void f (void * restrict in, void * restrict out, int l,
> int n, int m)
>  }
>
>  /* { dg-final { scan-assembler-times
> {vsetivli\s+zero,\s*8,\s*e8,\s*mf2,\s*t[au],\s*m[au]} 2 { target { no-opts
> "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
> -/* { dg-final { scan-assembler-times
> {vsetivli\s+zero,\s*8,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+\.L[0-9]+} 1 {
> target { no-opts "-O0" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops"
> } } } } */
> -/* { dg-final { scan-assembler-times
> {vsetivli\s+zero,\s*17,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+\.L[0-9]+} 1 {
> target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
> +/* { dg-final { scan-assembler-times
> {vsetivli\s+zero,\s*17,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 1 { target { no-opts
> "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
> diff --git
> a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-27.c
> b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-27.c
> index e148a1cc859..52e16d6a109 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-27.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-27.c
> @@ -38,7 +38,7 @@ void f (void * restrict in, void * restrict out, void *
> restrict in2, void * res
>    }
>  }
>
> -/* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 1 { target {
> no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts
> "-g" } } } } */
> +/* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 2 { target {
> no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts
> "-g" } } } } */
>  /* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]} 1 { target {
> no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts
> "-g" } } } } */
>  /* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]} 1 { target {
> no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts
> "-g" } } } } */
>  /* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m8,\s*t[au],\s*m[au]} 1 { target {
> no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts
> "-g" } } } } */
> @@ -48,4 +48,4 @@ void f (void * restrict in, void * restrict out, void *
> restrict in2, void * res
>
>  /* { dg-final { scan-assembler-times
> {vsetvli\s+zero,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 1 { target {
> no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts
> "-g" } } } } */
>  /* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 1 { target {
> no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts
> "-g" } } } } */
> -/* { dg-final { scan-assembler-times {vsetvli} 9 { target { no-opts
> "-O0"  no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" }
> } } } */
> +/* { dg-final { scan-assembler-times {vsetvli} 10 { target { no-opts
> "-O0"  no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" }
> } } } */
> diff --git
> a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-28.c
> b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-28.c
> index e8340a63ee2..98df1fc7dab 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-28.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-28.c
> @@ -40,7 +40,7 @@ void f (void * restrict in, void * restrict out, void *
> restrict in2, void * res
>    }
>  }
>
> -/* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 1 { target {
> no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts
> "-g" } } } } */
> +/* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 2 { target {
> no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts
> "-g" } } } } */
>  /* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]} 1 { target {
> no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts
> "-g" } } } } */
>  /* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]} 1 { target {
> no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts
> "-g" } } } } */
>  /* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m8,\s*t[au],\s*m[au]} 1 { target {
> no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts
> "-g" } } } } */
> @@ -51,4 +51,4 @@ void f (void * restrict in, void * restrict out, void *
> restrict in2, void * res
>  /* { dg-final { scan-assembler-times
> {vsetvli\s+zero,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 1 { target {
> no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts
> "-g" } } } } */
>  /* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 1 { target {
> no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts
> "-g" } } } } */
>  /* { dg-final { scan-assembler-times
> {vsetvli\s+zero,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 1 { target {
> no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts
> "-g" } } } } */
> -/* { dg-final { scan-assembler-times {vsetvli} 10 { target { no-opts
> "-O0"  no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" }
> } } } */
> +/* { dg-final { scan-assembler-times {vsetvli} 11 { target { no-opts
> "-O0"  no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" }
> } } } */
> diff --git
> a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-45.c
> b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-45.c
> index 0f6b96e6db6..3c2b5271e0c 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-45.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-45.c
> @@ -30,5 +30,5 @@ void foo5_5 (int32_t * restrict in, int32_t * restrict
> out, size_t n, size_t m,
>      }
>  }
>
> -/* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+j\s+\.L[0-9]+}
> 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts
> "-funroll-loops" no-opts "-g" } } } } */
> +/* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+j\s+\.L[0-9]+}
> 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts
> "-funroll-loops" no-opts "-g" } } } } */
>  /* { dg-final { scan-assembler-times {vsetvli} 1 { target { no-opts
> "-O0"  no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" }
> } } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-25.c
> b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-25.c
> index f87a8ccfad5..13aa25ec6b3 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-25.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-25.c
> @@ -563,10 +563,10 @@ void f7 (int8_t * restrict in, int8_t * restrict
> out, int n)
>    }
>  }
>
> -/* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 2 { target {
> no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts
> "-g" } } } } */
> -/* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]} 2 { target {
> no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts
> "-g" } } } } */
> -/* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]} 2 { target {
> no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts
> "-g" } } } } */
> -/* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m1,\s*t[au],\s*m[au]} 2 { target {
> no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts
> "-g" } } } } */
> -/* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m2,\s*t[au],\s*m[au]} 2 { target {
> no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts
> "-g" } } } } */
> -/* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m4,\s*t[au],\s*m[au]} 2 { target {
> no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts
> "-g" } } } } */
> -/* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m8,\s*t[au],\s*m[au]} 2 { target {
> no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts
> "-g" } } } } */
> +/* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 3 { target {
> no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts
> "-g" } } } } */
> +/* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]} 3 { target {
> no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts
> "-g" } } } } */
> +/* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]} 3 { target {
> no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts
> "-g" } } } } */
> +/* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m1,\s*t[au],\s*m[au]} 3 { target {
> no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts
> "-g" } } } } */
> +/* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m2,\s*t[au],\s*m[au]} 3 { target {
> no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts
> "-g" } } } } */
> +/* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m4,\s*t[au],\s*m[au]} 3 { target {
> no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts
> "-g" } } } } */
> +/* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m8,\s*t[au],\s*m[au]} 3 { target {
> no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts
> "-g" } } } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-26.c
> b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-26.c
> index c12385576cb..a5e065d012a 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-26.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-26.c
> @@ -483,10 +483,10 @@ void f6 (int8_t * restrict in, int8_t * restrict
> out, int n)
>    }
>  }
>
> -/* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 2 { target {
> no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts
> "-g" } } } } */
> -/* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]} 2 { target {
> no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts
> "-g" } } } } */
> -/* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]} 2 { target {
> no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts
> "-g" } } } } */
> -/* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 2 { target {
> no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts
> "-g" } } } } */
> -/* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]} 2 { target {
> no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts
> "-g" } } } } */
> -/* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 2 { target {
> no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts
> "-g" } } } } */
> +/* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 3 { target {
> no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts
> "-g" } } } } */
> +/* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]} 3 { target {
> no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts
> "-g" } } } } */
> +/* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]} 3 { target {
> no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts
> "-g" } } } } */
> +/* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 3 { target {
> no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts
> "-g" } } } } */
> +/* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]} 3 { target {
> no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts
> "-g" } } } } */
> +/* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 3 { target {
> no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts
> "-g" } } } } */
>
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-27.c
> b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-27.c
> index 6265000a6e1..927595144ab 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-27.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-27.c
> @@ -483,9 +483,9 @@ void f6 (int8_t * restrict in, int8_t * restrict out,
> int n)
>    }
>  }
>
> -/* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 2 { target {
> no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts
> "-g" } } } } */
> -/* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]} 2 { target {
> no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts
> "-g" } } } } */
> -/* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]} 2 { target {
> no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts
> "-g" } } } } */
> -/* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 2 { target {
> no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts
> "-g" } } } } */
> -/* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]} 2 { target {
> no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts
> "-g" } } } } */
> -/* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 2 { target {
> no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts
> "-g" } } } } */
> +/* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 3 { target {
> no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts
> "-g" } } } } */
> +/* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]} 3 { target {
> no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts
> "-g" } } } } */
> +/* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]} 3 { target {
> no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts
> "-g" } } } } */
> +/* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 3 { target {
> no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts
> "-g" } } } } */
> +/* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]} 3 { target {
> no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts
> "-g" } } } } */
> +/* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 3 { target {
> no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts
> "-g" } } } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-28.c
> b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-28.c
> index de7c5f95491..cbb4501605b 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-28.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-28.c
> @@ -83,4 +83,4 @@ void f6 (int8_t * restrict in, int8_t * restrict out,
> int n)
>    }
>  }
>
> -/* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 2 { target {
> no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts
> "-g" } } } } */
> +/* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 3 { target {
> no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts
> "-g" } } } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-3.c
> b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-3.c
> index f920017747b..ad89899f65c 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-3.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-3.c
> @@ -31,5 +31,5 @@ void f (int8_t * restrict in, int8_t * restrict out, int
> n)
>    }
>  }
>
> -/* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 2 { target {
> no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts
> "-g" } } } } */
> +/* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 3 { target {
> no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts
> "-g" } } } } */
>  /* { dg-final { scan-assembler-times
> {add\ta[0-7],a[0-7],a[0-7]\s+\.L[0-9][0-9]\:\s+vle32\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)}
> 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts
> "-g" } } } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-7.c
> b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-7.c
> index 05058b8c076..46f62927d0c 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-7.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-7.c
> @@ -23,4 +23,3 @@ void f (int32_t * restrict in, int32_t * restrict out,
> size_t n, size_t cond, si
>  /* { dg-final { scan-assembler-times {vsetvli} 4 { target { no-opts
> "-O0"  no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" }
> } } } */
>  /* { dg-final { scan-assembler-times
> {j\s+\.L[0-9]+\s+\.L[0-9]+:\s+vlm\.v} 1 { target { no-opts "-O0" no-opts
> "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
>  /* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m8,\s*t[au],\s*m[au]} 3 { target {
> no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts
> "-g" } } } } */
> -/* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 1 { target {
> no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts
> "-g" } } } } */
> diff --git
> a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-12.c
> b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-12.c
> index eaf69928d44..66c36ab24f8 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-12.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-12.c
> @@ -52,4 +52,4 @@ void foo (int8_t * restrict in, int8_t * restrict out,
> int n, int cond1, int con
>      }
>  }
>  /* { dg-final { scan-assembler-times {vsetvli} 9 { target { no-opts "-O0"
> no-opts "-O1" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
> -/* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+j\s+\.L[0-9]+}
> 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts
> "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */
> +
> --
> 2.36.1
>
>