Message ID | alpine.DEB.2.20.2206082325030.10833@tpp.orcam.me.uk |
---|---|
State | Committed |
Commit | 72b185189f914a412ae39776cd284dfaeaf2213b |
Headers |
Return-Path: <gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org> X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 9ADA73834E6B for <patchwork@sourceware.org>; Thu, 9 Jun 2022 13:36:27 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-wr1-x431.google.com (mail-wr1-x431.google.com [IPv6:2a00:1450:4864:20::431]) by sourceware.org (Postfix) with ESMTPS id 641003852777 for <gcc-patches@gcc.gnu.org>; Thu, 9 Jun 2022 13:36:10 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 641003852777 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=embecosm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=embecosm.com Received: by mail-wr1-x431.google.com with SMTP id d14so23464254wra.10 for <gcc-patches@gcc.gnu.org>; Thu, 09 Jun 2022 06:36:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=embecosm.com; s=google; h=date:from:to:cc:subject:message-id:user-agent:mime-version; bh=9kypZqVj6E2rUZSYkZ2Z0cg/PE0EKafK4E+kuHAbJeQ=; b=gBSswB7gM5RAK9ALw0RcFwJz/tez8hgfgXbhW+wUcj9F91Q6l8Bdp6F7zN9GQbdyFN aqeVqy6tqFthAcK6l6rvL4QRqdFWkJpI/lKQVWJ6jCrVjwMmzuvlGAp8sP2/cxNez+Ln zTRDk2IPATrkv5jscWfIvKX0D+gWrNoNuxoBwfTkGGRplf8BI27z0Ge80WCrqPoxvyaZ I6zxtA07lzUAJPeesLkjC4mYG5QC1HK8xGAthrlUWzkoEBGTql9DvzE91M4yI/JyU5Z0 xTQtgAte9JPzWBC7ZT57cMyaSBZA1MCLXmixZXv2+87s1Fh7ssvDuGSECblNm96kvB+n jLcg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:from:to:cc:subject:message-id:user-agent :mime-version; bh=9kypZqVj6E2rUZSYkZ2Z0cg/PE0EKafK4E+kuHAbJeQ=; b=wjfmcZ6UC/oJjbbW3xTHXeKDx83PqMLjV6aewHQL84n2ULqR71gE2eC/nS5NwJVA34 ldwkVKkQo4/9aoazMjW4ObKVmfPXZNEmIc5ltJtPfRf86RZ5lSY/Mtb3kwocVXtlWBEA n9NMErSTW0W7/sVjtmrip1xTtjAN/PdmLz9BwK2frIlGb9WFHDq4XUFJ81OxildaP2fz 07G/LIyDpy54jTzHU3r6p8xRNVZBt1KcOMplVxv6TT/CJSsENC7hmf2dHXnt26dabcWg I1tHqDqpbqiVYwy3PXxI16srBYR4Xf+6UIUUWsjX8pUFj9goR2uUtCr0BSfNzL8WdfTq XanQ== X-Gm-Message-State: AOAM531vQFSzpA4rxbpHNvuJKw70W8erRZ/OQcns2v6DWFp/+qO3ziHf ndhvI0AlcBrlRSpHBor6JEpcdO1BQ6PBVw== X-Google-Smtp-Source: ABdhPJydCX/oeCcc2E9uP1N3c1xwbOiTunn9U83Bb5ko5JsHOQ0KrnYxMlqAsx82SBh/I4jAjytZig== X-Received: by 2002:a5d:6c64:0:b0:20f:f2ad:6623 with SMTP id r4-20020a5d6c64000000b0020ff2ad6623mr39342061wrz.28.1654781769139; Thu, 09 Jun 2022 06:36:09 -0700 (PDT) Received: from tpp.orcam.me.uk (tpp.orcam.me.uk. [2001:8b0:154:0:ea6a:64ff:fe24:f2fc]) by smtp.gmail.com with ESMTPSA id b18-20020adfde12000000b0020d0f111241sm24577303wrm.24.2022.06.09.06.36.08 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Thu, 09 Jun 2022 06:36:08 -0700 (PDT) Date: Thu, 9 Jun 2022 14:36:06 +0100 (BST) From: "Maciej W. Rozycki" <macro@embecosm.com> To: gcc-patches@gcc.gnu.org Subject: [PATCH] RISC-V: Reset the length to the default of 4 for FP comparisons Message-ID: <alpine.DEB.2.20.2206082325030.10833@tpp.orcam.me.uk> User-Agent: Alpine 2.20 (DEB 67 2015-01-07) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII X-Spam-Status: No, score=-2.6 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list <gcc-patches.gcc.gnu.org> List-Unsubscribe: <https://gcc.gnu.org/mailman/options/gcc-patches>, <mailto:gcc-patches-request@gcc.gnu.org?subject=unsubscribe> List-Archive: <https://gcc.gnu.org/pipermail/gcc-patches/> List-Post: <mailto:gcc-patches@gcc.gnu.org> List-Help: <mailto:gcc-patches-request@gcc.gnu.org?subject=help> List-Subscribe: <https://gcc.gnu.org/mailman/listinfo/gcc-patches>, <mailto:gcc-patches-request@gcc.gnu.org?subject=subscribe> Cc: Andrew Waterman <andrew@sifive.com>, Kito Cheng <kito.cheng@gmail.com> Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" <gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org> |
Series |
RISC-V: Reset the length to the default of 4 for FP comparisons
|
|
Commit Message
Maciej W. Rozycki
June 9, 2022, 1:36 p.m. UTC
The default length for floating-point compare operations is overridden to 8, however the FEQ.fmt, FLT.fmt, FLE.fmt machine instructions and FGE.fmt, FGT.fmt assembly idioms the relevant RTL insns produce are all 4 bytes long each. And all the floating-point compare RTL insns that produce multiple machine instructions explicitly set their lengths. Remove the override then, letting the default of 4 apply for the single instruction case. gcc/ * config/riscv/riscv.md (length): Remove the explicit setting for "fcmp". --- Hi, So for: int feq (float x, float y) { return x == y; } we get: .globl feq .type feq, @function feq: feq.s a0,fa0,fa1 # 15 [c=4 l=8] *cstoresfdi4 ret # 24 [c=0 l=4] simple_return .size feq, .-feq which is obviously wrong given: Disassembly of section .text: 0000000000000000 <feq>: 0: a0b52553 feq.s a0,fa0,fa1 4: 8082 ret (hmm tabs are odd here too, but that's a binutils issue). I note that the override has always been there since the RISC-V port landed, so I take it it's a missed leftover from an earlier situation. With the change in place we instead get: .globl feq .type feq, @function feq: feq.s a0,fa0,fa1 # 15 [c=4 l=4] *cstoresfdi4 ret # 24 [c=0 l=4] simple_return .size feq, .-feq which I find so relieving. No regressions in the testsuite (and I haven't checked how it affects instruction scheduling, especially with `-Os', but I think it's obviously correct really). OK to apply? Maciej --- gcc/config/riscv/riscv.md | 2 -- 1 file changed, 2 deletions(-) gcc-riscv-fcmp-length.diff
Comments
LGTM, *f<quiet_pattern>_quiet<ANYF:mode><X:mode>4_default and *f<quiet_pattern>_quiet<ANYF:mode><X:mode>4_snan has set their own length and the only user of this setting is *cstore<ANYF:mode><X:mode>4, but apparently the length if 4 for that not 8. Thanks! On Thu, Jun 9, 2022 at 9:36 PM Maciej W. Rozycki <macro@embecosm.com> wrote: > > The default length for floating-point compare operations is overridden > to 8, however the FEQ.fmt, FLT.fmt, FLE.fmt machine instructions and > FGE.fmt, FGT.fmt assembly idioms the relevant RTL insns produce are all > 4 bytes long each. And all the floating-point compare RTL insns that > produce multiple machine instructions explicitly set their lengths. > > Remove the override then, letting the default of 4 apply for the single > instruction case. > > gcc/ > * config/riscv/riscv.md (length): Remove the explicit setting > for "fcmp". > --- > Hi, > > So for: > > int > feq (float x, float y) > { > return x == y; > } > > we get: > > .globl feq > .type feq, @function > feq: > feq.s a0,fa0,fa1 # 15 [c=4 l=8] *cstoresfdi4 > ret # 24 [c=0 l=4] simple_return > .size feq, .-feq > > which is obviously wrong given: > > Disassembly of section .text: > > 0000000000000000 <feq>: > 0: a0b52553 feq.s a0,fa0,fa1 > 4: 8082 ret > > (hmm tabs are odd here too, but that's a binutils issue). I note that the > override has always been there since the RISC-V port landed, so I take it > it's a missed leftover from an earlier situation. > > With the change in place we instead get: > > .globl feq > .type feq, @function > feq: > feq.s a0,fa0,fa1 # 15 [c=4 l=4] *cstoresfdi4 > ret # 24 [c=0 l=4] simple_return > .size feq, .-feq > > which I find so relieving. > > No regressions in the testsuite (and I haven't checked how it affects > instruction scheduling, especially with `-Os', but I think it's obviously > correct really). OK to apply? > > Maciej > --- > gcc/config/riscv/riscv.md | 2 -- > 1 file changed, 2 deletions(-) > > gcc-riscv-fcmp-length.diff > Index: gcc/gcc/config/riscv/riscv.md > =================================================================== > --- gcc.orig/gcc/config/riscv/riscv.md > +++ gcc/gcc/config/riscv/riscv.md > @@ -231,8 +231,6 @@ > > (eq_attr "got" "load") (const_int 8) > > - (eq_attr "type" "fcmp") (const_int 8) > - > ;; SHIFT_SHIFTs are decomposed into two separate instructions. > (eq_attr "move_type" "shift_shift") > (const_int 8)
On Thu, 9 Jun 2022, Kito Cheng wrote: > LGTM, *f<quiet_pattern>_quiet<ANYF:mode><X:mode>4_default and > *f<quiet_pattern>_quiet<ANYF:mode><X:mode>4_snan has set their own > length and the only user of this setting is > *cstore<ANYF:mode><X:mode>4, but apparently the length if 4 for that > not 8. I have committed this change now, thank you for your review. Maciej
Index: gcc/gcc/config/riscv/riscv.md =================================================================== --- gcc.orig/gcc/config/riscv/riscv.md +++ gcc/gcc/config/riscv/riscv.md @@ -231,8 +231,6 @@ (eq_attr "got" "load") (const_int 8) - (eq_attr "type" "fcmp") (const_int 8) - ;; SHIFT_SHIFTs are decomposed into two separate instructions. (eq_attr "move_type" "shift_shift") (const_int 8)