RISC-V: Don't try to vectorize tree-ssa/gen-vect-34.c

Message ID 20220903012810.23834-1-palmer@rivosinc.com
State Committed
Commit e3c4a86e6b98b334b1a20f2529e6c59f6e19f73d
Headers
Series RISC-V: Don't try to vectorize tree-ssa/gen-vect-34.c |

Commit Message

Palmer Dabbelt Sept. 3, 2022, 1:28 a.m. UTC
  We don't yet support vectorization on RISC-V.

gcc/testsuite/ChangeLog

	* gcc.dg/tree-ssa/gen-vect-34.c: Skip RISC-V targets.
---
 gcc/testsuite/gcc.dg/tree-ssa/gen-vect-34.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
  

Comments

Palmer Dabbelt Sept. 18, 2022, 8:47 a.m. UTC | #1
On Fri, 02 Sep 2022 18:28:10 PDT (-0700), Palmer Dabbelt wrote:
> We don't yet support vectorization on RISC-V.
>
> gcc/testsuite/ChangeLog
>
> 	* gcc.dg/tree-ssa/gen-vect-34.c: Skip RISC-V targets.
> ---
>  gcc/testsuite/gcc.dg/tree-ssa/gen-vect-34.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/gcc/testsuite/gcc.dg/tree-ssa/gen-vect-34.c b/gcc/testsuite/gcc.dg/tree-ssa/gen-vect-34.c
> index 8d2d36401fe..41877e05efd 100644
> --- a/gcc/testsuite/gcc.dg/tree-ssa/gen-vect-34.c
> +++ b/gcc/testsuite/gcc.dg/tree-ssa/gen-vect-34.c
> @@ -13,4 +13,4 @@ float summul(int n, float *arg1, float *arg2)
>      return res1;
>  }
>
> -/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { ! { avr-*-* pru-*-* } } } } } */
> +/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { ! { avr-*-* pru-*-* riscv*-*-* } } } } } */

Committed.
  

Patch

diff --git a/gcc/testsuite/gcc.dg/tree-ssa/gen-vect-34.c b/gcc/testsuite/gcc.dg/tree-ssa/gen-vect-34.c
index 8d2d36401fe..41877e05efd 100644
--- a/gcc/testsuite/gcc.dg/tree-ssa/gen-vect-34.c
+++ b/gcc/testsuite/gcc.dg/tree-ssa/gen-vect-34.c
@@ -13,4 +13,4 @@  float summul(int n, float *arg1, float *arg2)
     return res1;                                       
 }
 
-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { ! { avr-*-* pru-*-* } } } } } */
+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { ! { avr-*-* pru-*-* riscv*-*-* } } } } } */