[00/34] RISC-V: Add RVV (RISC-V 'V' Extension) support
Message ID | 20220601022917.270325-1-juzhe.zhong@rivai.ai |
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Headers |
Return-Path: <gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org> X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id CDC6338582B7 for <patchwork@sourceware.org>; Wed, 1 Jun 2022 02:29:48 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtpbg501.qq.com (smtpbg501.qq.com [203.205.250.101]) by sourceware.org (Postfix) with ESMTPS id 217903858294 for <gcc-patches@gcc.gnu.org>; Wed, 1 Jun 2022 02:29:27 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 217903858294 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai X-QQ-mid: bizesmtp68t1654050561t04n9d99 Received: from server1.localdomain ( [42.247.22.65]) by bizesmtp.qq.com (ESMTP) with id ; Wed, 01 Jun 2022 10:29:20 +0800 (CST) X-QQ-SSF: 01400000000000C0F000000A0000000 X-QQ-FEAT: YSwSv5UBo8hBy2vjJfdZZcrgyJ/+7pHzTYCAeQ6d2zzQWSKT526HQ6mvWNidw sj2F7iYTWbVt50QOat4Cdmu11csBTiB/lnGelINcN4CnUff0FjLSW7pTCTIG5Fit0CFsC+H Z4ajPt3HxC7rJ127OhyoNVIRFR5RZDXXu5QInfuZgTKiS2OZ8sGyx9mACCrvKe/Ikyhk1tV JGJacS+8f+mzLglYXwcAVmknD2R3cHF9X3XBybeeVS96bX8t+7DEjj6984f7VbsWkiUtH0f LP2iqckegv5QRRX6WmscNxQso6c7ZVEdAfuP1ugarOv3dzarSHmePspQTd+sjVtiXzqYs91 PU5/devBJCWM/kh7dk= X-QQ-GoodBg: 2 From: juzhe.zhong@rivai.ai To: gcc-patches@gcc.gnu.org Subject: [PATCH 00/34] RISC-V: Add RVV (RISC-V 'V' Extension) support Date: Wed, 1 Jun 2022 10:28:43 +0800 Message-Id: <20220601022917.270325-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybgforeign:qybgforeign10 X-QQ-Bgrelay: 1 X-Spam-Status: No, score=-5.5 required=5.0 tests=BAYES_00, KAM_DMARC_STATUS, KAM_SHORT, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE, T_SPF_HELO_TEMPERROR autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list <gcc-patches.gcc.gnu.org> List-Unsubscribe: <https://gcc.gnu.org/mailman/options/gcc-patches>, <mailto:gcc-patches-request@gcc.gnu.org?subject=unsubscribe> List-Archive: <https://gcc.gnu.org/pipermail/gcc-patches/> List-Post: <mailto:gcc-patches@gcc.gnu.org> List-Help: <mailto:gcc-patches-request@gcc.gnu.org?subject=help> List-Subscribe: <https://gcc.gnu.org/mailman/listinfo/gcc-patches>, <mailto:gcc-patches-request@gcc.gnu.org?subject=subscribe> Cc: zhongjuzhe <juzhe.zhong@rivai.ai> Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" <gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org> |
Message
钟居哲
June 1, 2022, 2:28 a.m. UTC
From: zhongjuzhe <juzhe.zhong@rivai.ai>
This patche add the testcases that are missed in v1.
*** BLURB HERE ***
zhongjuzhe (34):
RISC-V: Add vlex_1.c
RISC-V: Add vlex_2.c
RISC-V: Add vlex_1.C
RISC-V: Add mask load store testcases
RISC-V: Add vlexff_1.c
RISC-V: Add vlexff_2.c
RISC-V: Add vloxeix_1.c
RISC-V: Add vloxeix_2.c
RISC-V: Add vloxeix_3.c
RISC-V: Add vloxeix_4.c
RISC-V: Add vlsex_1.c
RISC-V: Add vlsex_2.c
RISC-V: Add vluxeix_1.c
RISC-V: Add vluxeix_2.c
RISC-V: Add vluxeix_3.c
RISC-V: Add vluxeix_4.c
RISC-V: Add vsex.c
RISC-V: Add vsoxeix.c
RISC-V: Add vssex.c
RISC-V: Add vsuxeix.c
RISC-V: Add vlexff_1.C
RISC-V: Add vloxeix_1.C
RISC-V: Add vloxeix_2.C
RISC-V: Add vloxeix_3.C
RISC-V: Add vloxeix_4.C
RISC-V: Add vlsex_1.C
RISC-V: Add vluxeix_1.C
RISC-V: Add vluxeix_2.C
RISC-V: Add vluxeix_3.C
RISC-V: Add vluxeix_4.C
RISC-V: Add vsex.C
RISC-V: Add vsoxeix.C
RISC-V: Add vssex.C
RISC-V: Add vsuxeix.C
gcc/testsuite/g++.target/riscv/rvv/vlex_1.C | 6792 ++++++
gcc/testsuite/g++.target/riscv/rvv/vlexff_1.C | 6792 ++++++
.../g++.target/riscv/rvv/vloxeix_1.C | 8663 +++++++
.../g++.target/riscv/rvv/vloxeix_2.C | 7191 ++++++
.../g++.target/riscv/rvv/vloxeix_3.C | 6120 +++++
.../g++.target/riscv/rvv/vloxeix_4.C | 2503 +++
gcc/testsuite/g++.target/riscv/rvv/vlsex_1.C | 6792 ++++++
.../g++.target/riscv/rvv/vluxeix_1.C | 8663 +++++++
.../g++.target/riscv/rvv/vluxeix_2.C | 7191 ++++++
.../g++.target/riscv/rvv/vluxeix_3.C | 6120 +++++
.../g++.target/riscv/rvv/vluxeix_4.C | 2503 +++
gcc/testsuite/g++.target/riscv/rvv/vsex.C | 1704 ++
gcc/testsuite/g++.target/riscv/rvv/vsoxeix.C | 6120 +++++
gcc/testsuite/g++.target/riscv/rvv/vssex.C | 1704 ++
gcc/testsuite/g++.target/riscv/rvv/vsuxeix.C | 6120 +++++
.../riscv/rvv/intrinsic/mask_load_store.c | 77 +
.../riscv/rvv/intrinsic/mask_load_store_31.c | 77 +
.../riscv/rvv/intrinsic/mask_load_store_32.c | 77 +
.../gcc.target/riscv/rvv/intrinsic/vlex_1.c | 17840 +++++++++++++++
.../gcc.target/riscv/rvv/intrinsic/vlex_2.c | 1251 ++
.../gcc.target/riscv/rvv/intrinsic/vlexff_1.c | 17840 +++++++++++++++
.../gcc.target/riscv/rvv/intrinsic/vlexff_2.c | 1251 ++
.../riscv/rvv/intrinsic/vloxeix_1.c | 16220 +++++++++++++
.../riscv/rvv/intrinsic/vloxeix_2.c | 18755 ++++++++++++++++
.../riscv/rvv/intrinsic/vloxeix_3.c | 18320 +++++++++++++++
.../riscv/rvv/intrinsic/vloxeix_4.c | 15486 +++++++++++++
.../gcc.target/riscv/rvv/intrinsic/vlsex_1.c | 17840 +++++++++++++++
.../gcc.target/riscv/rvv/intrinsic/vlsex_2.c | 1251 ++
.../riscv/rvv/intrinsic/vluxeix_1.c | 16220 +++++++++++++
.../riscv/rvv/intrinsic/vluxeix_2.c | 18755 ++++++++++++++++
.../riscv/rvv/intrinsic/vluxeix_3.c | 18320 +++++++++++++++
.../riscv/rvv/intrinsic/vluxeix_4.c | 15486 +++++++++++++
.../gcc.target/riscv/rvv/intrinsic/vsex.c | 4776 ++++
.../gcc.target/riscv/rvv/intrinsic/vsoxeix.c | 17196 ++++++++++++++
.../gcc.target/riscv/rvv/intrinsic/vssex.c | 4776 ++++
.../gcc.target/riscv/rvv/intrinsic/vsuxeix.c | 17196 ++++++++++++++
36 files changed, 323988 insertions(+)
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/vlex_1.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/vlexff_1.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/vloxeix_1.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/vloxeix_2.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/vloxeix_3.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/vloxeix_4.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/vlsex_1.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/vluxeix_1.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/vluxeix_2.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/vluxeix_3.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/vluxeix_4.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/vsex.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/vsoxeix.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/vssex.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/vsuxeix.C
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/intrinsic/mask_load_store.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/intrinsic/mask_load_store_31.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/intrinsic/mask_load_store_32.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/intrinsic/vlex_1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/intrinsic/vlex_2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/intrinsic/vlexff_1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/intrinsic/vlexff_2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/intrinsic/vloxeix_1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/intrinsic/vloxeix_2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/intrinsic/vloxeix_3.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/intrinsic/vloxeix_4.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/intrinsic/vlsex_1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/intrinsic/vlsex_2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/intrinsic/vluxeix_1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/intrinsic/vluxeix_2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/intrinsic/vluxeix_3.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/intrinsic/vluxeix_4.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/intrinsic/vsex.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/intrinsic/vsoxeix.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/intrinsic/vssex.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/intrinsic/vsuxeix.c