Show patches with: Search = RISC-V       |    Archived = No       |   3475 patches
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Patch Series rb/tb S/W/F Date Submitter Delegate State
[v1,3/6] RISC-V: Refine unsigned vector SAT_TRUNC testcase dump check to tree optimized [v1,1/6] RISC-V: Refine unsigned vector SAT_ADD testcase dump check to tree optimized - - 10-- 2024-12-08 Li, Pan2 Committed
[v1,2/6] RISC-V: Refine unsigned vector SAT_SUB testcase dump check to tree optimized [v1,1/6] RISC-V: Refine unsigned vector SAT_ADD testcase dump check to tree optimized - - 8-- 2024-12-08 Li, Pan2 Committed
[v1,1/6] RISC-V: Refine unsigned vector SAT_ADD testcase dump check to tree optimized [v1,1/6] RISC-V: Refine unsigned vector SAT_ADD testcase dump check to tree optimized - - 8-- 2024-12-08 Li, Pan2 Committed
[v1,6/6] RISC-V: Refine signed SAT_TRUNC testcase dump check to tree optimized [v1,1/6] RISC-V: Refine unsigned SAT_ADD testcase dump check to tree optimized - - 12-- 2024-12-08 Li, Pan2 Committed
[v1,5/6] RISC-V: Refine signed SAT_SUB testcase dump check to tree optimized [v1,1/6] RISC-V: Refine unsigned SAT_ADD testcase dump check to tree optimized - - 12-- 2024-12-08 Li, Pan2 Committed
[v1,4/6] RISC-V: Refine signed SAT_ADD testcase dump check to tree optimized [v1,1/6] RISC-V: Refine unsigned SAT_ADD testcase dump check to tree optimized - - 11-- 2024-12-08 Li, Pan2 Committed
[v1,3/6] RISC-V: Refine unsigned SAT_TRUNC testcase dump check to tree optimized [v1,1/6] RISC-V: Refine unsigned SAT_ADD testcase dump check to tree optimized - - 12-- 2024-12-08 Li, Pan2 Committed
[v1,2/6] RISC-V: Refine unsigned SAT_SUB testcase dump check to tree optimized [v1,1/6] RISC-V: Refine unsigned SAT_ADD testcase dump check to tree optimized - - 12-- 2024-12-08 Li, Pan2 Committed
[v1,1/6] RISC-V: Refine unsigned SAT_ADD testcase dump check to tree optimized [v1,1/6] RISC-V: Refine unsigned SAT_ADD testcase dump check to tree optimized - - 10-- 2024-12-08 Li, Pan2 Committed
RISC-V: optimization on checking certain bits set ((x & mask) == val) RISC-V: optimization on checking certain bits set ((x & mask) == val) - - 12-- 2024-12-06 Oliver Kozul JeffreyALaw Superseded
[v1,2/2] RISC-V: Refactor the testcases for rvv binop and cmp [v1,1/2] RISC-V: Fix incorrect optimization options passing to binop and cmp - - 12-- 2024-12-06 Li, Pan2 Committed
[v1,1/2] RISC-V: Fix incorrect optimization options passing to binop and cmp [v1,1/2] RISC-V: Fix incorrect optimization options passing to binop and cmp - - 10-1 2024-12-06 Li, Pan2 Committed
[committed] RISC-V: Add const to function_shape::get_name [NFC] [committed] RISC-V: Add const to function_shape::get_name [NFC] - - 8-2 2024-12-05 Kito Cheng Committed
[v3] RISC-V: Add --with-cmodel configure option [v3] RISC-V: Add --with-cmodel configure option - - 111- 2024-12-05 Kito Cheng Committed
[v1] RISC-V: Add assert for insn operand out of range access [PR117878][NFC] [v1] RISC-V: Add assert for insn operand out of range access [PR117878][NFC] - - 9-2 2024-12-04 Li, Pan2 Committed
[v1,2/2] RISC-V: Refactor the testcases for bswap16-0 [v1,1/2] RISC-V: Fix incorrect optimization options passing to convert and unop - - 12-- 2024-12-04 Li, Pan2 Committed
[v1,1/2] RISC-V: Fix incorrect optimization options passing to convert and unop [v1,1/2] RISC-V: Fix incorrect optimization options passing to convert and unop - - 11-1 2024-12-04 Li, Pan2 Committed
[Committed] RISC-V: Fix test target selector [Committed] RISC-V: Fix test target selector - - 8-2 2024-12-03 Edwin Lu Committed
[2/2] RISC-V: Support RISC-V Profiles RVA/B23. RISC-V: Support RISC-V Profiles. - - 91- 2024-12-03 Jiawei JeffreyALaw Superseded
[1/2] RISC-V: Support RISC-V Profiles RV20/22. RISC-V: Support RISC-V Profiles. - - 101- 2024-12-03 Jiawei JeffreyALaw Superseded
[v2] RISC-V: Fix ICE for unrecognizable insn `UNSPEC_VSETVL` for XTheadVector [v2] RISC-V: Fix ICE for unrecognizable insn `UNSPEC_VSETVL` for XTheadVector - - 12-- 2024-12-03 Jin Ma JeffreyALaw Superseded
[v1] RISC-V: Fix incorrect optimization options passing to reduc and ternop [v1] RISC-V: Fix incorrect optimization options passing to reduc and ternop - - 8-3 2024-12-03 Li, Pan2 Committed
[v1] RISC-V: Fix incorrect optimization options passing to cond and builtin [v1] RISC-V: Fix incorrect optimization options passing to cond and builtin - - 4-- 2024-12-02 Li, Pan2 Committed
[2/2] RISC-V: Add intrinsics testcases for SiFive Xsfvfnrclipxfqf extensions. RISC-V: Add intrinsics support and testcases for SiFive Xsfvfnrclipxfqf extension. - - 111- 2024-12-02 yulong Committed
[1/2] RISC-V: Add intrinsics support for SiFive Xsfvfnrclipxfqf extensions. RISC-V: Add intrinsics support and testcases for SiFive Xsfvfnrclipxfqf extension. - - 111- 2024-12-02 yulong Committed
RISC-V: Introduce vector lowering of VEC_PERM_EXPR for large vector types RISC-V: Introduce vector lowering of VEC_PERM_EXPR for large vector types - - 9-3 2024-12-01 Dusan Stojkovic Deferred
[v7,03/12] RISC-V: Add CRC expander to generate faster CRC. Untitled series #41359 - - 611 2024-11-29 Jeff Law Committed
[v1] RISC-V: Fix RVV strided load/store testcases failure [v1] RISC-V: Fix RVV strided load/store testcases failure - - 12-- 2024-11-29 Li, Pan2 Committed
[v1] RISC-V: Fix incorrect optimization options passing to widden [v1] RISC-V: Fix incorrect optimization options passing to widden - - 11-1 2024-11-29 Li, Pan2 Committed
[v1] RISC-V: Fix incorrect optimization options passing to widden [v1] RISC-V: Fix incorrect optimization options passing to widden - - 11-1 2024-11-29 Li, Pan2 Committed
[v2] RISC-V: Minimal support for ssdbltrp and smdbltrp extension. [v2] RISC-V: Minimal support for ssdbltrp and smdbltrp extension. - - 111- 2024-11-28 chendongyan Committed
RISC-V: Minimal support for ssdbltrp and smdbltrp extension. RISC-V: Minimal support for ssdbltrp and smdbltrp extension. - - 515 2024-11-28 chendongyan Dropped
[2/2] RISC-V: Add intrinsics testcases for SiFive Xsfvqmaccqoq/dod extensions. RISC-V: Add intrinsics support and testcases for SiFive Xsfvqmaccqoq/dod. - - 111- 2024-11-28 yulong Committed
[1/2] RISC-V: Add intrinsics support for SiFive Xsfvqmaccqoq/dod extensions. RISC-V: Add intrinsics support and testcases for SiFive Xsfvqmaccqoq/dod. - - 111- 2024-11-28 yulong Committed
[v1,3/3] RISC-V: Add testcases for vec_duplicate + vadd.vv combine to vadd.vx [v1,1/3] RISC-V: Combine vec_duplicate + vadd.vv to vadd.vx - - 12-- 2024-11-27 Li, Pan2 Deferred
[v1,2/3] RISC-V: Adjust the testcases after vec_duplicate + vadd.vv combine [v1,1/3] RISC-V: Combine vec_duplicate + vadd.vv to vadd.vx - - 12-- 2024-11-27 Li, Pan2 Deferred
[v1,1/3] RISC-V: Combine vec_duplicate + vadd.vv to vadd.vx [v1,1/3] RISC-V: Combine vec_duplicate + vadd.vv to vadd.vx - - 9-1 2024-11-27 Li, Pan2 Deferred
RISC-V: avlprop: Do not propagate VL from slidedown. RISC-V: avlprop: Do not propagate VL from slidedown. - - 12-- 2024-11-25 Robin Dapp Committed
[v1,2/2] RISC-V: Refactor the testcases for RVV gather/scatter [v1,1/2] RISC-V: Fix incorrect optimization options passing to gather/scatter - - 12-- 2024-11-25 Li, Pan2 Committed
[v1,1/2] RISC-V: Fix incorrect optimization options passing to gather/scatter [v1,1/2] RISC-V: Fix incorrect optimization options passing to gather/scatter - - 11-1 2024-11-25 Li, Pan2 Committed
testsuite:RISC-V:Modify the char string. testsuite:RISC-V:Modify the char string. - - 12-- 2024-11-23 yulong JeffreyALaw Committed
[v2,4/4] RISC-V: Improve slide1up pattern. Improve and add VLS slide strategies. - - 1011 2024-11-22 Robin Dapp JuzheZhong Committed
[v2,3/4] RISC-V: Add even/odd vec_perm_const pattern. Improve and add VLS slide strategies. - - 1011 2024-11-22 Robin Dapp JuzheZhong Committed
[v2,2/4] RISC-V: Add interleave pattern. Improve and add VLS slide strategies. - - 1011 2024-11-22 Robin Dapp JuzheZhong Committed
[v2,1/4] RISC-V: Add slide to perm_const strategies. Improve and add VLS slide strategies. - - 1011 2024-11-22 Robin Dapp JuzheZhong Committed
RISC-V: Ensure vtype for full-register moves [PR117544]. RISC-V: Ensure vtype for full-register moves [PR117544]. - - 12-- 2024-11-22 Robin Dapp JeffreyALaw Committed
[to-be-committed,RISC-V,PR,target/109s79] Improve RISC-V constant synthesis [to-be-committed,RISC-V,PR,target/109s79] Improve RISC-V constant synthesis - - 12-- 2024-11-22 Jeff Law Committed
[v3] RISC-V: Minimal support for svvptc extension. [v3] RISC-V: Minimal support for svvptc extension. - - 111- 2024-11-22 chendongyan Committed
[to-be-committed,RISC-V,PR,target/117690] Add missing shift in constant synthesis [to-be-committed,RISC-V,PR,target/117690] Add missing shift in constant synthesis - - 10-2 2024-11-21 Jeff Law Committed
testsuite: RISC-V: Fix vector flags handling [PR117603] testsuite: RISC-V: Fix vector flags handling [PR117603] - - 12-- 2024-11-21 Dimitar Dimitrov rdapp Committed
[v2] RISC-V: Minimal support for svvptc extension. [v2] RISC-V: Minimal support for svvptc extension. - - 111- 2024-11-21 chendongyan kitoc Superseded
RISC-V: Minimal support for svvptc extension. RISC-V: Minimal support for svvptc extension. - - 111- 2024-11-21 chendongyan Dropped
[v1,7/7] RISC-V: Refine the vector stride load/store testcases [v1,1/7] RISC-V: Rearrange the test files for vector SAT_SUB [NFC] - - 12-- 2024-11-21 Li, Pan2 Committed
[v1,6/7] RISC-V: Refactor the test files for all other vector SAT ALU [v1,1/7] RISC-V: Rearrange the test files for vector SAT_SUB [NFC] - - 10-- 2024-11-21 Li, Pan2 Committed
[v1,5/7] RISC-V: Rearrange the test files for all other vector SAT ALU [NFC] [v1,1/7] RISC-V: Rearrange the test files for vector SAT_SUB [NFC] - - 7-1 2024-11-21 Li, Pan2 Committed
[v1,4/7] RISC-V: Refactor the testcases for vector SAT_TRUNC [v1,1/7] RISC-V: Rearrange the test files for vector SAT_SUB [NFC] - - 8-- 2024-11-21 Li, Pan2 Committed
[v1,3/7] RISC-V: Rearrange the test files for vector SAT_TRUNC [NFC] [v1,1/7] RISC-V: Rearrange the test files for vector SAT_SUB [NFC] - - 8-- 2024-11-21 Li, Pan2 Committed
[v1,2/7] RISC-V: Refactor the testcases for vector SAT_SUB [v1,1/7] RISC-V: Rearrange the test files for vector SAT_SUB [NFC] - - 8-- 2024-11-21 Li, Pan2 Committed
[v1,1/7] RISC-V: Rearrange the test files for vector SAT_SUB [NFC] [v1,1/7] RISC-V: Rearrange the test files for vector SAT_SUB [NFC] - - 7-1 2024-11-21 Li, Pan2 Committed
[to-be-committed,RISC-V,PR,target/116590] Avoid emitting multiple instructions from fmacc patterns [to-be-committed,RISC-V,PR,target/116590] Avoid emitting multiple instructions from fmacc patterns - - 111- 2024-11-20 Jeff Law Committed
[v1,3/3] RISC-V: Refine the rtl dump expand check for vector SAT_ADD [v1,1/3] RISC-V: Rearrange the test files for vector SAT_ADD [NFC] - - 811 2024-11-20 Li, Pan2 Committed
[v1,2/3] RISC-V: Introduce riscv/rvv/autovec/sat folder to rvv.exp testsuite [v1,1/3] RISC-V: Rearrange the test files for vector SAT_ADD [NFC] - - 512 2024-11-20 Li, Pan2 Committed
[v1,1/3] RISC-V: Rearrange the test files for vector SAT_ADD [NFC] [v1,1/3] RISC-V: Rearrange the test files for vector SAT_ADD [NFC] - - 8-2 2024-11-20 Li, Pan2 Committed
PR target/117669 - RISC-V:The 'VEEWTRUNC4' iterator 'RVVMF2BF' type condition error PR target/117669 - RISC-V:The 'VEEWTRUNC4' iterator 'RVVMF2BF' type condition error - - 8-2 2024-11-20 Feng Wang Committed
RISC-V:Fix wrong condition for vector-bfloat16 RISC-V:Fix wrong condition for vector-bfloat16 - - 7-2 2024-11-20 Feng Wang JeffreyALaw Committed
RISC-V: testsuite: restrict big endian test to non vector RISC-V: testsuite: restrict big endian test to non vector - - 12-- 2024-11-19 Edwin Lu JeffreyALaw Committed
[to-be-committed,RISC-V,PR,target/117649] Fix branch on masked values splitter [to-be-committed,RISC-V,PR,target/117649] Fix branch on masked values splitter - - 12-- 2024-11-19 Jeff Law JeffreyALaw Committed
[v1,2/2] RISC-V: Refine the rtl expand check for strided ld/st [v1,1/2] RISC-V: Fix incorrect optimization options passing to strided ld/st test - - 12-- 2024-11-19 Li, Pan2 JeffreyALaw Committed
[v1,1/2] RISC-V: Fix incorrect optimization options passing to strided ld/st test [v1,1/2] RISC-V: Fix incorrect optimization options passing to strided ld/st test - - 12-- 2024-11-19 Li, Pan2 JeffreyALaw Committed
RISC-V: testsuite: fix old-style function definition error [NFC] RISC-V: testsuite: fix old-style function definition error [NFC] - - 12-- 2024-11-18 Edwin Lu JeffreyALaw Committed
[committed,RISC-V,PR,target/117595] Fix bogus use of simplify_gen_subreg [committed,RISC-V,PR,target/117595] Fix bogus use of simplify_gen_subreg - - 7-3 2024-11-18 Jeff Law Committed
[v1,2/2] RISC-V: Remove unnecessary option for all other scalar SAT_* testcase [v1,1/2] RISC-V: Rearrange the rest of test files for scalar SAT_* [NFC] - - 11-1 2024-11-18 Li, Pan2 JeffreyALaw Committed
[v1,1/2] RISC-V: Rearrange the rest of test files for scalar SAT_* [NFC] [v1,1/2] RISC-V: Rearrange the rest of test files for scalar SAT_* [NFC] - - 10-1 2024-11-18 Li, Pan2 JeffreyALaw Committed
[4/4] RISC-V: Improve slide1up pattern. Add maskload else operand. - - -13 2024-11-17 Robin Dapp JuzheZhong Superseded
[3/4] RISC-V: Add even/odd vec_perm_const pattern. Add maskload else operand. - - -12 2024-11-17 Robin Dapp JuzheZhong Superseded
[2/4] RISC-V: Add interleave pattern. Add maskload else operand. - - -11 2024-11-17 Robin Dapp JuzheZhong Superseded
RISC-V: Add slide to perm_const strategies. Add maskload else operand. - - 611 2024-11-17 Robin Dapp JuzheZhong Superseded
[V1] RISC-V: Add the mini support for SiFive extensions. [V1] RISC-V: Add the mini support for SiFive extensions. - - 101- 2024-11-17 yulong kitoc Committed
[committed] RISC-V testsuite adjustments for c23 [committed] RISC-V testsuite adjustments for c23 - - 8-2 2024-11-16 Jeff Law Committed
[v1,2/2] RISC-V: Remove unnecessary option for scalar SAT_TRUNC testcase [v1,1/2] RISC-V: Rearrange the test files for scalar SAT_TRUNC [NFC] - - 10-- 2024-11-16 Li, Pan2 JeffreyALaw Committed
[v1,1/2] RISC-V: Rearrange the test files for scalar SAT_TRUNC [NFC] [v1,1/2] RISC-V: Rearrange the test files for scalar SAT_TRUNC [NFC] - - 9-1 2024-11-16 Li, Pan2 JeffreyALaw Committed
RISC-V:Support N32(32-bit ABI on 64-bit ISA) in riscv RISC-V:Support N32(32-bit ABI on 64-bit ISA) in riscv - 1 10-- 2024-11-16 Liao Shihua kitoc Deferred
[v2] RISC-V: Tie MUL and DIV masks to the M extension [v2] RISC-V: Tie MUL and DIV masks to the M extension - - 11-- 2024-11-15 Dimitar Dimitrov JeffreyALaw Committed
[v1,2/2] RISC-V: Remove unnecessary option for scalar SAT_SUB testcase [v1,1/2] RISC-V: Rearrange the test files for scalar SAT_SUB [NFC] - - 512 2024-11-15 Li, Pan2 JuzheZhong Committed
[v1,1/2] RISC-V: Rearrange the test files for scalar SAT_SUB [NFC] [v1,1/2] RISC-V: Rearrange the test files for scalar SAT_SUB [NFC] - - 8-2 2024-11-15 Li, Pan2 JuzheZhong Committed
[4/4] RISC-V: Add -fcf-protection=[full|branch|return] to enable zicfiss, zicfilp. [1/4] RISC-V: Add Zicfiss ISA extension. - - 911 2024-11-15 Monk Chiang kitoc Superseded
[3/4] RISC-V: Add .note.gnu.property for ZICFILP and ZICFISS ISA extension [1/4] RISC-V: Add Zicfiss ISA extension. - - 91- 2024-11-15 Monk Chiang kitoc Superseded
[2/4] RISC-V: Add Zicfilp ISA extension. [1/4] RISC-V: Add Zicfiss ISA extension. - - 71- 2024-11-15 Monk Chiang kitoc Superseded
[1/4] RISC-V: Add Zicfiss ISA extension. [1/4] RISC-V: Add Zicfiss ISA extension. - - 71- 2024-11-15 Monk Chiang kitoc Superseded
[v1] RISC-V: Remove unnecessary option for scalar SAT_ADD testcase [v1] RISC-V: Remove unnecessary option for scalar SAT_ADD testcase - - 811 2024-11-15 Li, Pan2 JuzheZhong Committed
[COMMITTED] RISC-V: Move scalar SAT_ADD test cases to a isolated folder [COMMITTED] RISC-V: Move scalar SAT_ADD test cases to a isolated folder - - 712 2024-11-15 Li, Pan2 JuzheZhong Committed
[2/2] RISC-V: Use dynamic shadow offset [1/2] asan: Support dynamic shadow offset - - 12-- 2024-11-15 Kito Cheng JeffreyALaw Committed
[RFC,RISC-V] Add target dependent pass to optimize related permutation constants [RFC,RISC-V] Add target dependent pass to optimize related permutation constants - - 73- 2024-11-14 Jeff Law Deferred
[to-be-committed,RISC-V,V2] Fix type on vector move patterns [to-be-committed,RISC-V,V2] Fix type on vector move patterns - - 11-1 2024-11-14 Jeff Law Committed
[v1] RISC-V: Rearrange the test files for scalar SAT_ADD [NFC] [v1] RISC-V: Rearrange the test files for scalar SAT_ADD [NFC] - - 8-2 2024-11-14 Li, Pan2 Committed
RISC-V: Add VLS modes to strided loads. RISC-V: Add VLS modes to strided loads. - - 111- 2024-11-13 Robin Dapp JuzheZhong Committed
RISC-V: Tie MUL and DIV masks to the M extension RISC-V: Tie MUL and DIV masks to the M extension - - 11-1 2024-11-13 Dimitar Dimitrov JeffreyALaw Superseded
RISC-V: Bugfix for unrecognizable insn for XTheadVector RISC-V: Bugfix for unrecognizable insn for XTheadVector - - 12-- 2024-11-13 Jin Ma Committed
[v2] RISC-V: Bugfix for max_sew_overlap_and_next_ratio_valid_for_prev_sew_p[pr117483] [v2] RISC-V: Bugfix for max_sew_overlap_and_next_ratio_valid_for_prev_sew_p[pr117483] - - 9-2 2024-11-13 xuli1@eswincomputing.com Committed
RISC-V: Bugfix for max_sew_overlap_and_next_ratio_valid_for_prev_sew_p[pr117483] RISC-V: Bugfix for max_sew_overlap_and_next_ratio_valid_for_prev_sew_p[pr117483] - - 9-2 2024-11-13 xuli1@eswincomputing.com JeffreyALaw Superseded
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