diff mbox series

[v1] RISC-V: Fix RVV strided load/store testcases failure

Message ID 20241129040133.3970279-1-pan2.li@intel.com
State Committed
Commit aedb306a457496bac3b0029c6b4a1e63c738ddde
Headers
Series [v1] RISC-V: Fix RVV strided load/store testcases failure |

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Context Check Description
rivoscibot/toolchain-ci-rivos-lint success Lint passed
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linaro-tcwg-bot/tcwg_gcc_build--master-aarch64 success Build passed
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rivoscibot/toolchain-ci-rivos-build--linux-rv64gc-lp64d-non-multilib success Build passed
rivoscibot/toolchain-ci-rivos-build--newlib-rv64gcv-lp64d-multilib success Build passed
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Commit Message

Li, Pan2 Nov. 29, 2024, 4:01 a.m. UTC 
  From: Pan Li <pan2.li@intel.com>

This patch would like to fix the testcases failures of strided
load/store after sorts of optimization option passing to testcase.

* Add no strict align for vector option.
* Adjust dg-final by any-opts and/or no-opts if the rtl dump changes
  on different optimization options (like O2, O3, zvl).

The below test suites are passed for this patch.
* The rv64gcv fully regression test.

It is test only patch and obvious up to a point, will commit it
directly if no comments in next 48H.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-f16.c: Fix
	the failed test by target any-opts and/or no-opts.
	* gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-f32.c: Ditto
	* gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-f64.c: Ditto
	* gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-i16.c: Ditto
	* gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-i32.c: Ditto
	* gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-i64.c: Ditto
	* gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-i8.c: Ditto
	* gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-u16.c: Ditto
	* gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-u32.c: Ditto
	* gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-u64.c: Ditto
	* gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-u8.c: Ditto

Signed-off-by: Pan Li <pan2.li@intel.com>
---
 .../rvv/autovec/strided/strided_ld_st-1-f16.c | 32 ++++++++++---
 .../rvv/autovec/strided/strided_ld_st-1-f32.c | 32 ++++++++++---
 .../rvv/autovec/strided/strided_ld_st-1-f64.c |  2 +-
 .../rvv/autovec/strided/strided_ld_st-1-i16.c | 32 ++++++++++---
 .../rvv/autovec/strided/strided_ld_st-1-i32.c | 46 ++++++++++++++++---
 .../rvv/autovec/strided/strided_ld_st-1-i64.c |  2 +-
 .../rvv/autovec/strided/strided_ld_st-1-i8.c  | 32 ++++++++++---
 .../rvv/autovec/strided/strided_ld_st-1-u16.c | 32 ++++++++++---
 .../rvv/autovec/strided/strided_ld_st-1-u32.c | 46 ++++++++++++++++---
 .../rvv/autovec/strided/strided_ld_st-1-u64.c |  2 +-
 .../rvv/autovec/strided/strided_ld_st-1-u8.c  | 32 ++++++++++---
 11 files changed, 231 insertions(+), 59 deletions(-)
diff mbox series

Patch

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-f16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-f16.c
index a128e9fb20a..4098774ba38 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-f16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-f16.c
@@ -1,13 +1,31 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -fno-vect-cost-model -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -mno-vector-strict-align -fno-vect-cost-model -fdump-rtl-expand-details" } */
 
 #include "strided_ld_st.h"
 
 DEF_STRIDED_LD_ST_FORM_1(_Float16)
 
-/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_LOAD " 4 "expand" { target { any-opts "-O3" } } } } */
-/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_STORE " 4 "expand" { target { any-opts "-O3" } } } } */
-/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_LOAD " 2 "expand" { target { any-opts "-O2" } } } } */
-/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_STORE " 2 "expand" { target { any-opts "-O2" } } } } */
-/* { dg-final { scan-assembler-times {vlse16.v} 1 } } */
-/* { dg-final { scan-assembler-times {vsse16.v} 1 } } */
+/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_LOAD " 4 "expand" { target {
+     any-opts "-O3"
+     no-opts "-mrvv-vector-bits=zvl"
+   } } } } */
+/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_STORE " 4 "expand" { target {
+     any-opts "-O3"
+     no-opts "-mrvv-vector-bits=zvl"
+   } } } } */
+
+/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_LOAD " 2 "expand" { target {
+     any-opts "-O2"
+     no-opts "-mrvv-vector-bits=zvl"
+   } } } } */
+/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_STORE " 2 "expand" { target {
+     any-opts "-O2"
+     no-opts "-mrvv-vector-bits=zvl"
+   } } } } */
+
+/* { dg-final { scan-assembler-times {vlse16.v} 1 { target {
+     no-opts "-mrvv-vector-bits=zvl"
+   } } } } */
+/* { dg-final { scan-assembler-times {vsse16.v} 1 { target {
+     no-opts "-mrvv-vector-bits=zvl"
+   } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-f32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-f32.c
index 621c26a2df2..e1d1063ec8c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-f32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-f32.c
@@ -1,13 +1,31 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -fno-vect-cost-model -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -mno-vector-strict-align -fno-vect-cost-model -fdump-rtl-expand-details" } */
 
 #include "strided_ld_st.h"
 
 DEF_STRIDED_LD_ST_FORM_1(float)
 
-/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_LOAD " 4 "expand" { target { any-opts "-O3" } } } } */
-/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_STORE " 4 "expand" { target { any-opts "-O3" } } } } */
-/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_LOAD " 2 "expand" { target { any-opts "-O2" } } } } */
-/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_STORE " 2 "expand" { target { any-opts "-O2" } } } } */
-/* { dg-final { scan-assembler-times {vlse32.v} 1 } } */
-/* { dg-final { scan-assembler-times {vsse32.v} 1 } } */
+/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_LOAD " 4 "expand" { target {
+     any-opts "-O3"
+     no-opts "-mrvv-vector-bits=zvl"
+   } } } } */
+/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_STORE " 4 "expand" { target {
+     any-opts "-O3"
+     no-opts "-mrvv-vector-bits=zvl"
+   } } } } */
+
+/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_LOAD " 2 "expand" { target {
+     any-opts "-O2"
+     no-opts "-mrvv-vector-bits=zvl"
+   } } } } */
+/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_STORE " 2 "expand" { target {
+     any-opts "-O2"
+     no-opts "-mrvv-vector-bits=zvl"
+   } } } } */
+
+/* { dg-final { scan-assembler-times {vlse32.v} 1 { target {
+     no-opts "-mrvv-vector-bits=zvl"
+   } } } } */
+/* { dg-final { scan-assembler-times {vsse32.v} 1 { target {
+     no-opts "-mrvv-vector-bits=zvl"
+   } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-f64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-f64.c
index 48ae5aa6d42..e4f6a40873b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-f64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-f64.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -fno-vect-cost-model -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -mno-vector-strict-align -fno-vect-cost-model -fdump-rtl-expand-details" } */
 
 #include "strided_ld_st.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-i16.c
index 37d43106113..57b20a2f952 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-i16.c
@@ -1,13 +1,31 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -fno-vect-cost-model -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -mno-vector-strict-align -fno-vect-cost-model -fdump-rtl-expand-details" } */
 
 #include "strided_ld_st.h"
 
 DEF_STRIDED_LD_ST_FORM_1(int16_t)
 
-/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_LOAD " 4 "expand" { target { any-opts "-O3" } } } } */
-/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_STORE " 4 "expand" { target { any-opts "-O3" } } } } */
-/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_LOAD " 2 "expand" { target { any-opts "-O2" } } } } */
-/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_STORE " 2 "expand" { target { any-opts "-O2" } } } } */
-/* { dg-final { scan-assembler-times {vlse16.v} 1 } } */
-/* { dg-final { scan-assembler-times {vsse16.v} 1 } } */
+/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_LOAD " 4 "expand" { target {
+     any-opts "-O3"
+     no-opts "-mrvv-vector-bits=zvl"
+   } } } } */
+/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_STORE " 4 "expand" { target {
+     any-opts "-O3"
+     no-opts "-mrvv-vector-bits=zvl"
+   } } } } */
+
+/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_LOAD " 2 "expand" { target {
+     any-opts "-O2"
+     no-opts "-mrvv-vector-bits=zvl"
+   } } } } */
+/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_STORE " 2 "expand" { target {
+     any-opts "-O2"
+     no-opts "-mrvv-vector-bits=zvl"
+   } } } } */
+
+/* { dg-final { scan-assembler-times {vlse16.v} 1 { target {
+     no-opts "-mrvv-vector-bits=zvl"
+   } } } } */
+/* { dg-final { scan-assembler-times {vsse16.v} 1 { target {
+     no-opts "-mrvv-vector-bits=zvl"
+   } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-i32.c
index 88a9bf02dac..1e4ae9fc98f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-i32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-i32.c
@@ -1,13 +1,45 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -fno-vect-cost-model -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -mno-vector-strict-align -fno-vect-cost-model -fdump-rtl-expand-details" } */
 
 #include "strided_ld_st.h"
 
 DEF_STRIDED_LD_ST_FORM_1(int32_t)
 
-/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_LOAD " 4 "expand" { target { any-opts "-O3" } } } } */
-/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_STORE " 4 "expand" { target { any-opts "-O3" } } } } */
-/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_LOAD " 2 "expand" { target { any-opts "-O2" } } } } */
-/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_STORE " 2 "expand" { target { any-opts "-O2" } } } } */
-/* { dg-final { scan-assembler-times {vlse32.v} 1 } } */
-/* { dg-final { scan-assembler-times {vsse32.v} 1 } } */
+/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_LOAD " 4 "expand" { target {
+     any-opts "-O3"
+     no-opts "-mrvv-vector-bits=zvl"
+   } } } } */
+/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_STORE " 4 "expand" { target {
+     any-opts "-O3"
+     no-opts "-mrvv-vector-bits=zvl"
+   } } } } */
+
+/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_LOAD " 8 "expand" { target {
+     any-opts "-O3" "-mrvv-vector-bits=zvl"
+   } } } } */
+/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_STORE " 8 "expand" { target {
+     any-opts "-O3" "-mrvv-vector-bits=zvl"
+   } } } } */
+
+/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_LOAD " 2 "expand" { target {
+     any-opts "-O2"
+     no-opts "-mrvv-vector-bits=zvl"
+   } } } } */
+/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_STORE " 2 "expand" { target {
+     any-opts "-O2"
+     no-opts "-mrvv-vector-bits=zvl"
+   } } } } */
+
+/* { dg-final { scan-assembler-times {vlse32.v} 1 { target {
+     no-opts "-mrvv-vector-bits=zvl"
+   } } } } */
+/* { dg-final { scan-assembler-times {vsse32.v} 1 { target {
+     no-opts "-mrvv-vector-bits=zvl"
+   } } } } */
+
+/* { dg-final { scan-assembler-times {vlse32.v} 2 { target {
+     any-opts "-mrvv-vector-bits=zvl"
+   } } } } */
+/* { dg-final { scan-assembler-times {vsse32.v} 2 { target {
+     any-opts "-mrvv-vector-bits=zvl"
+   } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-i64.c
index 3b3ad5da6c0..afbce226368 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-i64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-i64.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -fno-vect-cost-model -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -mno-vector-strict-align -fno-vect-cost-model -fdump-rtl-expand-details" } */
 
 #include "strided_ld_st.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-i8.c
index 74f5aea3264..d948f89abe7 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-i8.c
@@ -1,13 +1,31 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -fno-vect-cost-model -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -mno-vector-strict-align -fno-vect-cost-model -fdump-rtl-expand-details" } */
 
 #include "strided_ld_st.h"
 
 DEF_STRIDED_LD_ST_FORM_1(int8_t)
 
-/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_LOAD " 4 "expand" { target { any-opts "-O3" } } } } */
-/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_STORE " 4 "expand" { target { any-opts "-O3" } } } } */
-/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_LOAD " 2 "expand" { target { any-opts "-O2" } } } } */
-/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_STORE " 2 "expand" { target { any-opts "-O2" } } } } */
-/* { dg-final { scan-assembler-times {vlse8.v} 1 } } */
-/* { dg-final { scan-assembler-times {vsse8.v} 1 } } */
+/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_LOAD " 4 "expand" { target {
+     any-opts "-O3"
+     no-opts "-mrvv-vector-bits=zvl"
+   } } } } */
+/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_STORE " 4 "expand" { target {
+     any-opts "-O3"
+     no-opts "-mrvv-vector-bits=zvl"
+   } } } } */
+
+/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_LOAD " 2 "expand" { target {
+     any-opts "-O2"
+     no-opts "-mrvv-vector-bits=zvl"
+   } } } } */
+/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_STORE " 2 "expand" { target {
+     any-opts "-O2"
+     no-opts "-mrvv-vector-bits=zvl"
+   } } } } */
+
+/* { dg-final { scan-assembler-times {vlse8.v} 1 { target {
+     no-opts "-mrvv-vector-bits=zvl"
+   } } } } */
+/* { dg-final { scan-assembler-times {vsse8.v} 1 { target {
+     no-opts "-mrvv-vector-bits=zvl"
+   } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-u16.c
index 8176006f8bf..78b6dbc1c49 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-u16.c
@@ -1,13 +1,31 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -fno-vect-cost-model -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -mno-vector-strict-align -fno-vect-cost-model -fdump-rtl-expand-details" } */
 
 #include "strided_ld_st.h"
 
 DEF_STRIDED_LD_ST_FORM_1(uint16_t)
 
-/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_LOAD " 4 "expand" { target { any-opts "-O3" } } } } */
-/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_STORE " 4 "expand" { target { any-opts "-O3" } } } } */
-/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_LOAD " 2 "expand" { target { any-opts "-O2" } } } } */
-/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_STORE " 2 "expand" { target { any-opts "-O2" } } } } */
-/* { dg-final { scan-assembler-times {vlse16.v} 1 } } */
-/* { dg-final { scan-assembler-times {vsse16.v} 1 } } */
+/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_LOAD " 4 "expand" { target {
+     any-opts "-O3"
+     no-opts "-mrvv-vector-bits=zvl"
+   } } } } */
+/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_STORE " 4 "expand" { target {
+     any-opts "-O3"
+     no-opts "-mrvv-vector-bits=zvl"
+   } } } } */
+
+/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_LOAD " 2 "expand" { target {
+     any-opts "-O2"
+     no-opts "-mrvv-vector-bits=zvl"
+   } } } } */
+/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_STORE " 2 "expand" { target {
+     any-opts "-O2"
+     no-opts "-mrvv-vector-bits=zvl"
+   } } } } */
+
+/* { dg-final { scan-assembler-times {vlse16.v} 1 { target {
+     no-opts "-mrvv-vector-bits=zvl"
+   } } } } */
+/* { dg-final { scan-assembler-times {vsse16.v} 1 { target {
+     no-opts "-mrvv-vector-bits=zvl"
+   } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-u32.c
index 41531f39f26..b1994d7d199 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-u32.c
@@ -1,13 +1,45 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -fno-vect-cost-model -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -mno-vector-strict-align -fno-vect-cost-model -fdump-rtl-expand-details" } */
 
 #include "strided_ld_st.h"
 
 DEF_STRIDED_LD_ST_FORM_1(uint32_t)
 
-/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_LOAD " 4 "expand" { target { any-opts "-O3" } } } } */
-/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_STORE " 4 "expand" { target { any-opts "-O3" } } } } */
-/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_LOAD " 2 "expand" { target { any-opts "-O2" } } } } */
-/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_STORE " 2 "expand" { target { any-opts "-O2" } } } } */
-/* { dg-final { scan-assembler-times {vlse32.v} 1 } } */
-/* { dg-final { scan-assembler-times {vsse32.v} 1 } } */
+/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_LOAD " 4 "expand" { target {
+     any-opts "-O3"
+     no-opts "-mrvv-vector-bits=zvl"
+   } } } } */
+/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_STORE " 4 "expand" { target {
+     any-opts "-O3"
+     no-opts "-mrvv-vector-bits=zvl"
+   } } } } */
+
+/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_LOAD " 8 "expand" { target {
+     any-opts "-O3" "-mrvv-vector-bits=zvl"
+   } } } } */
+/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_STORE " 8 "expand" { target {
+     any-opts "-O3" "-mrvv-vector-bits=zvl"
+   } } } } */
+
+/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_LOAD " 2 "expand" { target {
+     any-opts "-O2"
+     no-opts "-mrvv-vector-bits=zvl"
+   } } } } */
+/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_STORE " 2 "expand" { target {
+     any-opts "-O2"
+     no-opts "-mrvv-vector-bits=zvl"
+   } } } } */
+
+/* { dg-final { scan-assembler-times {vlse32.v} 1 { target {
+     no-opts "-mrvv-vector-bits=zvl"
+   } } } } */
+/* { dg-final { scan-assembler-times {vsse32.v} 1 { target {
+     no-opts "-mrvv-vector-bits=zvl"
+   } } } } */
+
+/* { dg-final { scan-assembler-times {vlse32.v} 2 { target {
+     any-opts "-mrvv-vector-bits=zvl"
+   } } } } */
+/* { dg-final { scan-assembler-times {vsse32.v} 2 { target {
+     any-opts "-mrvv-vector-bits=zvl"
+   } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-u64.c
index 695964fedb1..a66eb5bcfd4 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-u64.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -fno-vect-cost-model -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -mno-vector-strict-align -fno-vect-cost-model -fdump-rtl-expand-details" } */
 
 #include "strided_ld_st.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-u8.c
index 7bc3b4ee602..7870ede903d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-u8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-u8.c
@@ -1,13 +1,31 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -fno-vect-cost-model -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -mno-vector-strict-align -fno-vect-cost-model -fdump-rtl-expand-details" } */
 
 #include "strided_ld_st.h"
 
 DEF_STRIDED_LD_ST_FORM_1(uint8_t)
 
-/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_LOAD " 4 "expand" { target { any-opts "-O3" } } } } */
-/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_STORE " 4 "expand" { target { any-opts "-O3" } } } } */
-/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_LOAD " 2 "expand" { target { any-opts "-O2" } } } } */
-/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_STORE " 2 "expand" { target { any-opts "-O2" } } } } */
-/* { dg-final { scan-assembler-times {vlse8.v} 1 } } */
-/* { dg-final { scan-assembler-times {vsse8.v} 1 } } */
+/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_LOAD " 4 "expand" { target {
+     any-opts "-O3"
+     no-opts "-mrvv-vector-bits=zvl"
+   } } } } */
+/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_STORE " 4 "expand" { target {
+     any-opts "-O3"
+     no-opts "-mrvv-vector-bits=zvl"
+   } } } } */
+
+/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_LOAD " 2 "expand" { target {
+     any-opts "-O2"
+     no-opts "-mrvv-vector-bits=zvl"
+   } } } } */
+/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_STORE " 2 "expand" { target {
+     any-opts "-O2"
+     no-opts "-mrvv-vector-bits=zvl"
+   } } } } */
+
+/* { dg-final { scan-assembler-times {vlse8.v} 1 { target {
+     no-opts "-mrvv-vector-bits=zvl"
+   } } } } */
+/* { dg-final { scan-assembler-times {vsse8.v} 1 { target {
+     no-opts "-mrvv-vector-bits=zvl"
+   } } } } */