diff mbox series

[2/2] RISC-V: Add intrinsics testcases for SiFive Xsfvqmaccqoq/dod extensions.

Message ID 20241128023605.14438-3-shiyulong@iscas.ac.cn
State Committed
Commit fe29b03825c9971ef1726bf9c7288de3389511b3
Headers
Series RISC-V: Add intrinsics support and testcases for SiFive Xsfvqmaccqoq/dod. |

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Commit Message

yulong Nov. 28, 2024, 2:36 a.m. UTC 
  From: yulong <shiyulong@iscas.ac.cn>

This commit adds testcases for Xsfvqmaccqoq/dod.

Co-Authored by: Kito Cheng <kito.cheng@sifive.com>
Co-Authored by: Monk Chiang <monk.chiang@sifive.com>
Co-Authored by: Jiawei Chen <jiawei@iscas.ac.cn>
Co-Authored by: Shihua Liao <shihua@iscas.ac.cn>
Co-Authored by: Yixuan Chen <chenyixuan@iscas.ac.cn>

gcc/testsuite/ChangeLog:

        * gcc.target/riscv/rvv/rvv.exp:
        * gcc.target/riscv/rvv/xsfvector/sf_vqmacc_2x8x2.c: New test.
        * gcc.target/riscv/rvv/xsfvector/sf_vqmacc_4x8x4.c: New test.
        * gcc.target/riscv/rvv/xsfvector/sf_vqmaccsu_2x8x2.c: New test.
        * gcc.target/riscv/rvv/xsfvector/sf_vqmaccsu_4x8x4.c: New test.
        * gcc.target/riscv/rvv/xsfvector/sf_vqmaccu_2x8x2.c: New test.
        * gcc.target/riscv/rvv/xsfvector/sf_vqmaccu_4x8x4.c: New test.
        * gcc.target/riscv/rvv/xsfvector/sf_vqmaccus_2x8x2.c: New test.
        * gcc.target/riscv/rvv/xsfvector/sf_vqmaccus_4x8x4.c: New test.

---
 gcc/testsuite/gcc.target/riscv/rvv/rvv.exp    |   2 +
 .../riscv/rvv/xsfvector/sf_vqmacc_2x8x2.c     | 213 ++++++++++++++++++
 .../riscv/rvv/xsfvector/sf_vqmacc_4x8x4.c     | 213 ++++++++++++++++++
 .../riscv/rvv/xsfvector/sf_vqmaccsu_2x8x2.c   | 213 ++++++++++++++++++
 .../riscv/rvv/xsfvector/sf_vqmaccsu_4x8x4.c   | 213 ++++++++++++++++++
 .../riscv/rvv/xsfvector/sf_vqmaccu_2x8x2.c    | 213 ++++++++++++++++++
 .../riscv/rvv/xsfvector/sf_vqmaccu_4x8x4.c    | 213 ++++++++++++++++++
 .../riscv/rvv/xsfvector/sf_vqmaccus_2x8x2.c   | 213 ++++++++++++++++++
 .../riscv/rvv/xsfvector/sf_vqmaccus_4x8x4.c   | 213 ++++++++++++++++++
 9 files changed, 1706 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vqmacc_2x8x2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vqmacc_4x8x4.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vqmaccsu_2x8x2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vqmaccsu_4x8x4.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vqmaccu_2x8x2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vqmaccu_4x8x4.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vqmaccus_2x8x2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vqmaccus_4x8x4.c
diff mbox series

Patch

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp b/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp
index 448374d49db..8f5860c46b4 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp
+++ b/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp
@@ -37,6 +37,8 @@  dg-init
 set CFLAGS "$DEFAULT_CFLAGS -O3"
 dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/base/*.\[cS\]]] \
 	"" $CFLAGS
+dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/xsfvector/*.\[cS\]]] \
+	"" $CFLAGS
 gcc-dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/vsetvl/*.\[cS\]]] \
 	"" $CFLAGS
 dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/autovec/*.\[cS\]]] \
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vqmacc_2x8x2.c b/gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vqmacc_2x8x2.c
new file mode 100644
index 00000000000..f2058a14779
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vqmacc_2x8x2.c
@@ -0,0 +1,213 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_xsfvqmaccdod -mabi=lp64d -O3" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "riscv_vector.h"
+
+/*
+** test_sf_vqmacc_2x8x2_i32m1_vint32m1_t:
+** ...
+** sf\.vqmacc\.2x8x2\tv[0-9]+,v[0-9]+,v[0-9]+
+** ...
+*/
+vint32m1_t
+test_sf_vqmacc_2x8x2_i32m1_vint32m1_t (vint32m1_t vd, vint8m1_t vs1,
+				       vint8m1_t vs2, size_t vl)
+{
+  return __riscv_sf_vqmacc_2x8x2_i32m1 (vd, vs1, vs2, vl);
+}
+
+/*
+** test_sf_vqmacc_2x8x2_i32m2_vint32m2_t:
+** ...
+** sf\.vqmacc\.2x8x2\tv[0-9]+,v[0-9]+,v[0-9]+
+** ...
+*/
+vint32m2_t
+test_sf_vqmacc_2x8x2_i32m2_vint32m2_t (vint32m2_t vd, vint8m1_t vs1,
+				       vint8m2_t vs2, size_t vl)
+{
+  return __riscv_sf_vqmacc_2x8x2_i32m2 (vd, vs1, vs2, vl);
+}
+
+/*
+** test_sf_vqmacc_2x8x2_i32m4_vint32m4_t:
+** ...
+** sf\.vqmacc\.2x8x2\tv[0-9]+,v[0-9]+,v[0-9]+
+** ...
+*/
+vint32m4_t
+test_sf_vqmacc_2x8x2_i32m4_vint32m4_t (vint32m4_t vd, vint8m1_t vs1,
+				       vint8m4_t vs2, size_t vl)
+{
+  return __riscv_sf_vqmacc_2x8x2_i32m4 (vd, vs1, vs2, vl);
+}
+
+/*
+** test_sf_vqmacc_2x8x2_i32m8_vint32m8_t:
+** ...
+** sf\.vqmacc\.2x8x2\tv[0-9]+,v[0-9]+,v[0-9]+
+** ...
+*/
+vint32m8_t
+test_sf_vqmacc_2x8x2_i32m8_vint32m8_t (vint32m8_t vd, vint8m1_t vs1,
+				       vint8m8_t vs2, size_t vl)
+{
+  return __riscv_sf_vqmacc_2x8x2_i32m8 (vd, vs1, vs2, vl);
+}
+
+/*
+** test_sf_vqmacc_2x8x2_vint32m1_t:
+** ...
+** sf\.vqmacc\.2x8x2\tv[0-9]+,v[0-9]+,v[0-9]+
+** ...
+*/
+vint32m1_t
+test_sf_vqmacc_2x8x2_vint32m1_t (vint32m1_t vd, vint8m1_t vs1, vint8m1_t vs2,
+				 size_t vl)
+{
+  return __riscv_sf_vqmacc_2x8x2 (vd, vs1, vs2, vl);
+}
+
+/*
+** test_sf_vqmacc_2x8x2_vint32m2_t:
+** ...
+** sf\.vqmacc\.2x8x2\tv[0-9]+,v[0-9]+,v[0-9]+
+** ...
+*/
+vint32m2_t
+test_sf_vqmacc_2x8x2_vint32m2_t (vint32m2_t vd, vint8m1_t vs1, vint8m2_t vs2,
+				 size_t vl)
+{
+  return __riscv_sf_vqmacc_2x8x2 (vd, vs1, vs2, vl);
+}
+
+/*
+** test_sf_vqmacc_2x8x2_vint32m4_t:
+** ...
+** sf\.vqmacc\.2x8x2\tv[0-9]+,v[0-9]+,v[0-9]+
+** ...
+*/
+vint32m4_t
+test_sf_vqmacc_2x8x2_vint32m4_t (vint32m4_t vd, vint8m1_t vs1, vint8m4_t vs2,
+				 size_t vl)
+{
+  return __riscv_sf_vqmacc_2x8x2 (vd, vs1, vs2, vl);
+}
+
+/*
+** test_sf_vqmacc_2x8x2_vint32m8_t:
+** ...
+** sf\.vqmacc\.2x8x2\tv[0-9]+,v[0-9]+,v[0-9]+
+** ...
+*/
+vint32m8_t
+test_sf_vqmacc_2x8x2_vint32m8_t (vint32m8_t vd, vint8m1_t vs1, vint8m8_t vs2,
+				 size_t vl)
+{
+  return __riscv_sf_vqmacc_2x8x2 (vd, vs1, vs2, vl);
+}
+
+/*
+** test_sf_vqmacc_2x8x2_i32m1_tu_vint32m1_t:
+** ...
+** sf\.vqmacc\.2x8x2\tv[0-9]+,v[0-9]+,v[0-9]+
+** ...
+*/
+vint32m1_t
+test_sf_vqmacc_2x8x2_i32m1_tu_vint32m1_t (vint32m1_t vd, vint8m1_t vs1,
+					  vint8m1_t vs2, size_t vl)
+{
+  return __riscv_sf_vqmacc_2x8x2_i32m1_tu (vd, vs1, vs2, vl);
+}
+
+/*
+** test_sf_vqmacc_2x8x2_i32m2_tu_vint32m2_t:
+** ...
+** sf\.vqmacc\.2x8x2\tv[0-9]+,v[0-9]+,v[0-9]+
+** ...
+*/
+vint32m2_t
+test_sf_vqmacc_2x8x2_i32m2_tu_vint32m2_t (vint32m2_t vd, vint8m1_t vs1,
+					  vint8m2_t vs2, size_t vl)
+{
+  return __riscv_sf_vqmacc_2x8x2_i32m2_tu (vd, vs1, vs2, vl);
+}
+
+/*
+** test_sf_vqmacc_2x8x2_i32m4_tu_vint32m4_t:
+** ...
+** sf\.vqmacc\.2x8x2\tv[0-9]+,v[0-9]+,v[0-9]+
+** ...
+*/
+vint32m4_t
+test_sf_vqmacc_2x8x2_i32m4_tu_vint32m4_t (vint32m4_t vd, vint8m1_t vs1,
+					  vint8m4_t vs2, size_t vl)
+{
+  return __riscv_sf_vqmacc_2x8x2_i32m4_tu (vd, vs1, vs2, vl);
+}
+
+/*
+** test_sf_vqmacc_2x8x2_i32m8_tu_vint32m8_t:
+** ...
+** sf\.vqmacc\.2x8x2\tv[0-9]+,v[0-9]+,v[0-9]+
+** ...
+*/
+vint32m8_t
+test_sf_vqmacc_2x8x2_i32m8_tu_vint32m8_t (vint32m8_t vd, vint8m1_t vs1,
+					  vint8m8_t vs2, size_t vl)
+{
+  return __riscv_sf_vqmacc_2x8x2_i32m8_tu (vd, vs1, vs2, vl);
+}
+
+/*
+** test_sf_vqmacc_2x8x2_tu_vint32m1_t:
+** ...
+** sf\.vqmacc\.2x8x2\tv[0-9]+,v[0-9]+,v[0-9]+
+** ...
+*/
+vint32m1_t
+test_sf_vqmacc_2x8x2_tu_vint32m1_t (vint32m1_t vd, vint8m1_t vs1, vint8m1_t vs2,
+				    size_t vl)
+{
+  return __riscv_sf_vqmacc_2x8x2_tu (vd, vs1, vs2, vl);
+}
+
+/*
+** test_sf_vqmacc_2x8x2_tu_vint32m2_t:
+** ...
+** sf\.vqmacc\.2x8x2\tv[0-9]+,v[0-9]+,v[0-9]+
+** ...
+*/
+vint32m2_t
+test_sf_vqmacc_2x8x2_tu_vint32m2_t (vint32m2_t vd, vint8m1_t vs1, vint8m2_t vs2,
+				    size_t vl)
+{
+  return __riscv_sf_vqmacc_2x8x2_tu (vd, vs1, vs2, vl);
+}
+
+/*
+** test_sf_vqmacc_2x8x2_tu_vint32m4_t:
+** ...
+** sf\.vqmacc\.2x8x2\tv[0-9]+,v[0-9]+,v[0-9]+
+** ...
+*/
+vint32m4_t
+test_sf_vqmacc_2x8x2_tu_vint32m4_t (vint32m4_t vd, vint8m1_t vs1, vint8m4_t vs2,
+				    size_t vl)
+{
+  return __riscv_sf_vqmacc_2x8x2_tu (vd, vs1, vs2, vl);
+}
+
+/*
+** test_sf_vqmacc_2x8x2_tu_vint32m8_t:
+** ...
+** sf\.vqmacc\.2x8x2\tv[0-9]+,v[0-9]+,v[0-9]+
+** ...
+*/
+vint32m8_t
+test_sf_vqmacc_2x8x2_tu_vint32m8_t (vint32m8_t vd, vint8m1_t vs1, vint8m8_t vs2,
+				    size_t vl)
+{
+  return __riscv_sf_vqmacc_2x8x2_tu (vd, vs1, vs2, vl);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vqmacc_4x8x4.c b/gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vqmacc_4x8x4.c
new file mode 100644
index 00000000000..3bd6f1c273c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vqmacc_4x8x4.c
@@ -0,0 +1,213 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_xsfvqmaccqoq -mabi=lp64d -O3" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "riscv_vector.h"
+
+/*
+** test_sf_vqmacc_4x8x4_i32m1_vint32m1_t:
+** ...
+** sf\.vqmacc\.4x8x4\tv[0-9]+,v[0-9]+,v[0-9]+
+** ...
+*/
+vint32m1_t
+test_sf_vqmacc_4x8x4_i32m1_vint32m1_t (vint32m1_t vd, vint8m1_t vs1,
+				       vint8mf2_t vs2, size_t vl)
+{
+  return __riscv_sf_vqmacc_4x8x4_i32m1 (vd, vs1, vs2, vl);
+}
+
+/*
+** test_sf_vqmacc_4x8x4_i32m2_vint32m2_t:
+** ...
+** sf\.vqmacc\.4x8x4\tv[0-9]+,v[0-9]+,v[0-9]+
+** ...
+*/
+vint32m2_t
+test_sf_vqmacc_4x8x4_i32m2_vint32m2_t (vint32m2_t vd, vint8m1_t vs1,
+				       vint8m1_t vs2, size_t vl)
+{
+  return __riscv_sf_vqmacc_4x8x4_i32m2 (vd, vs1, vs2, vl);
+}
+
+/*
+** test_sf_vqmacc_4x8x4_i32m4_vint32m4_t:
+** ...
+** sf\.vqmacc\.4x8x4\tv[0-9]+,v[0-9]+,v[0-9]+
+** ...
+*/
+vint32m4_t
+test_sf_vqmacc_4x8x4_i32m4_vint32m4_t (vint32m4_t vd, vint8m1_t vs1,
+				       vint8m2_t vs2, size_t vl)
+{
+  return __riscv_sf_vqmacc_4x8x4_i32m4 (vd, vs1, vs2, vl);
+}
+
+/*
+** test_sf_vqmacc_4x8x4_i32m8_vint32m8_t:
+** ...
+** sf\.vqmacc\.4x8x4\tv[0-9]+,v[0-9]+,v[0-9]+
+** ...
+*/
+vint32m8_t
+test_sf_vqmacc_4x8x4_i32m8_vint32m8_t (vint32m8_t vd, vint8m1_t vs1,
+				       vint8m4_t vs2, size_t vl)
+{
+  return __riscv_sf_vqmacc_4x8x4_i32m8 (vd, vs1, vs2, vl);
+}
+
+/*
+** test_sf_vqmacc_4x8x4_vint32m1_t:
+** ...
+** sf\.vqmacc\.4x8x4\tv[0-9]+,v[0-9]+,v[0-9]+
+** ...
+*/
+vint32m1_t
+test_sf_vqmacc_4x8x4_vint32m1_t (vint32m1_t vd, vint8m1_t vs1, vint8mf2_t vs2,
+				 size_t vl)
+{
+  return __riscv_sf_vqmacc_4x8x4 (vd, vs1, vs2, vl);
+}
+
+/*
+** test_sf_vqmacc_4x8x4_vint32m2_t:
+** ...
+** sf\.vqmacc\.4x8x4\tv[0-9]+,v[0-9]+,v[0-9]+
+** ...
+*/
+vint32m2_t
+test_sf_vqmacc_4x8x4_vint32m2_t (vint32m2_t vd, vint8m1_t vs1, vint8m1_t vs2,
+				 size_t vl)
+{
+  return __riscv_sf_vqmacc_4x8x4 (vd, vs1, vs2, vl);
+}
+
+/*
+** test_sf_vqmacc_4x8x4_vint32m4_t:
+** ...
+** sf\.vqmacc\.4x8x4\tv[0-9]+,v[0-9]+,v[0-9]+
+** ...
+*/
+vint32m4_t
+test_sf_vqmacc_4x8x4_vint32m4_t (vint32m4_t vd, vint8m1_t vs1, vint8m2_t vs2,
+				 size_t vl)
+{
+  return __riscv_sf_vqmacc_4x8x4 (vd, vs1, vs2, vl);
+}
+
+/*
+** test_sf_vqmacc_4x8x4_vint32m8_t:
+** ...
+** sf\.vqmacc\.4x8x4\tv[0-9]+,v[0-9]+,v[0-9]+
+** ...
+*/
+vint32m8_t
+test_sf_vqmacc_4x8x4_vint32m8_t (vint32m8_t vd, vint8m1_t vs1, vint8m4_t vs2,
+				 size_t vl)
+{
+  return __riscv_sf_vqmacc_4x8x4 (vd, vs1, vs2, vl);
+}
+
+/*
+** test_sf_vqmacc_4x8x4_i32m1_tu_vint32m1_t:
+** ...
+** sf\.vqmacc\.4x8x4\tv[0-9]+,v[0-9]+,v[0-9]+
+** ...
+*/
+vint32m1_t
+test_sf_vqmacc_4x8x4_i32m1_tu_vint32m1_t (vint32m1_t vd, vint8m1_t vs1,
+					  vint8mf2_t vs2, size_t vl)
+{
+  return __riscv_sf_vqmacc_4x8x4_i32m1_tu (vd, vs1, vs2, vl);
+}
+
+/*
+** test_sf_vqmacc_4x8x4_i32m2_tu_vint32m2_t:
+** ...
+** sf\.vqmacc\.4x8x4\tv[0-9]+,v[0-9]+,v[0-9]+
+** ...
+*/
+vint32m2_t
+test_sf_vqmacc_4x8x4_i32m2_tu_vint32m2_t (vint32m2_t vd, vint8m1_t vs1,
+					  vint8m1_t vs2, size_t vl)
+{
+  return __riscv_sf_vqmacc_4x8x4_i32m2_tu (vd, vs1, vs2, vl);
+}
+
+/*
+** test_sf_vqmacc_4x8x4_i32m4_tu_vint32m4_t:
+** ...
+** sf\.vqmacc\.4x8x4\tv[0-9]+,v[0-9]+,v[0-9]+
+** ...
+*/
+vint32m4_t
+test_sf_vqmacc_4x8x4_i32m4_tu_vint32m4_t (vint32m4_t vd, vint8m1_t vs1,
+					  vint8m2_t vs2, size_t vl)
+{
+  return __riscv_sf_vqmacc_4x8x4_i32m4_tu (vd, vs1, vs2, vl);
+}
+
+/*
+** test_sf_vqmacc_4x8x4_i32m8_tu_vint32m8_t:
+** ...
+** sf\.vqmacc\.4x8x4\tv[0-9]+,v[0-9]+,v[0-9]+
+** ...
+*/
+vint32m8_t
+test_sf_vqmacc_4x8x4_i32m8_tu_vint32m8_t (vint32m8_t vd, vint8m1_t vs1,
+					  vint8m4_t vs2, size_t vl)
+{
+  return __riscv_sf_vqmacc_4x8x4_i32m8_tu (vd, vs1, vs2, vl);
+}
+
+/*
+** test_sf_vqmacc_4x8x4_tu_vint32m1_t:
+** ...
+** sf\.vqmacc\.4x8x4\tv[0-9]+,v[0-9]+,v[0-9]+
+** ...
+*/
+vint32m1_t
+test_sf_vqmacc_4x8x4_tu_vint32m1_t (vint32m1_t vd, vint8m1_t vs1,
+				    vint8mf2_t vs2, size_t vl)
+{
+  return __riscv_sf_vqmacc_4x8x4_tu (vd, vs1, vs2, vl);
+}
+
+/*
+** test_sf_vqmacc_4x8x4_tu_vint32m2_t:
+** ...
+** sf\.vqmacc\.4x8x4\tv[0-9]+,v[0-9]+,v[0-9]+
+** ...
+*/
+vint32m2_t
+test_sf_vqmacc_4x8x4_tu_vint32m2_t (vint32m2_t vd, vint8m1_t vs1, vint8m1_t vs2,
+				    size_t vl)
+{
+  return __riscv_sf_vqmacc_4x8x4_tu (vd, vs1, vs2, vl);
+}
+
+/*
+** test_sf_vqmacc_4x8x4_tu_vint32m4_t:
+** ...
+** sf\.vqmacc\.4x8x4\tv[0-9]+,v[0-9]+,v[0-9]+
+** ...
+*/
+vint32m4_t
+test_sf_vqmacc_4x8x4_tu_vint32m4_t (vint32m4_t vd, vint8m1_t vs1, vint8m2_t vs2,
+				    size_t vl)
+{
+  return __riscv_sf_vqmacc_4x8x4_tu (vd, vs1, vs2, vl);
+}
+
+/*
+** test_sf_vqmacc_4x8x4_tu_vint32m8_t:
+** ...
+** sf\.vqmacc\.4x8x4\tv[0-9]+,v[0-9]+,v[0-9]+
+** ...
+*/
+vint32m8_t
+test_sf_vqmacc_4x8x4_tu_vint32m8_t (vint32m8_t vd, vint8m1_t vs1, vint8m4_t vs2,
+				    size_t vl)
+{
+  return __riscv_sf_vqmacc_4x8x4_tu (vd, vs1, vs2, vl);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vqmaccsu_2x8x2.c b/gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vqmaccsu_2x8x2.c
new file mode 100644
index 00000000000..663c7634ebf
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vqmaccsu_2x8x2.c
@@ -0,0 +1,213 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_xsfvqmaccdod -mabi=lp64d -O3" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "riscv_vector.h"
+
+/*
+** test_sf_vqmaccsu_2x8x2_i32m1_vint32m1_t:
+** ...
+** sf\.vqmaccsu\.2x8x2\tv[0-9]+,v[0-9]+,v[0-9]+
+** ...
+*/
+vint32m1_t
+test_sf_vqmaccsu_2x8x2_i32m1_vint32m1_t (vint32m1_t vd, vint8m1_t vs1,
+					 vuint8m1_t vs2, size_t vl)
+{
+  return __riscv_sf_vqmaccsu_2x8x2_i32m1 (vd, vs1, vs2, vl);
+}
+
+/*
+** test_sf_vqmaccsu_2x8x2_i32m2_vint32m2_t:
+** ...
+** sf\.vqmaccsu\.2x8x2\tv[0-9]+,v[0-9]+,v[0-9]+
+** ...
+*/
+vint32m2_t
+test_sf_vqmaccsu_2x8x2_i32m2_vint32m2_t (vint32m2_t vd, vint8m1_t vs1,
+					 vuint8m2_t vs2, size_t vl)
+{
+  return __riscv_sf_vqmaccsu_2x8x2_i32m2 (vd, vs1, vs2, vl);
+}
+
+/*
+** test_sf_vqmaccsu_2x8x2_i32m4_vint32m4_t:
+** ...
+** sf\.vqmaccsu\.2x8x2\tv[0-9]+,v[0-9]+,v[0-9]+
+** ...
+*/
+vint32m4_t
+test_sf_vqmaccsu_2x8x2_i32m4_vint32m4_t (vint32m4_t vd, vint8m1_t vs1,
+					 vuint8m4_t vs2, size_t vl)
+{
+  return __riscv_sf_vqmaccsu_2x8x2_i32m4 (vd, vs1, vs2, vl);
+}
+
+/*
+** test_sf_vqmaccsu_2x8x2_i32m8_vint32m8_t:
+** ...
+** sf\.vqmaccsu\.2x8x2\tv[0-9]+,v[0-9]+,v[0-9]+
+** ...
+*/
+vint32m8_t
+test_sf_vqmaccsu_2x8x2_i32m8_vint32m8_t (vint32m8_t vd, vint8m1_t vs1,
+					 vuint8m8_t vs2, size_t vl)
+{
+  return __riscv_sf_vqmaccsu_2x8x2_i32m8 (vd, vs1, vs2, vl);
+}
+
+/*
+** test_sf_vqmaccsu_2x8x2_vint32m1_t:
+** ...
+** sf\.vqmaccsu\.2x8x2\tv[0-9]+,v[0-9]+,v[0-9]+
+** ...
+*/
+vint32m1_t
+test_sf_vqmaccsu_2x8x2_vint32m1_t (vint32m1_t vd, vint8m1_t vs1, vuint8m1_t vs2,
+				   size_t vl)
+{
+  return __riscv_sf_vqmaccsu_2x8x2 (vd, vs1, vs2, vl);
+}
+
+/*
+** test_sf_vqmaccsu_2x8x2_vint32m2_t:
+** ...
+** sf\.vqmaccsu\.2x8x2\tv[0-9]+,v[0-9]+,v[0-9]+
+** ...
+*/
+vint32m2_t
+test_sf_vqmaccsu_2x8x2_vint32m2_t (vint32m2_t vd, vint8m1_t vs1, vuint8m2_t vs2,
+				   size_t vl)
+{
+  return __riscv_sf_vqmaccsu_2x8x2 (vd, vs1, vs2, vl);
+}
+
+/*
+** test_sf_vqmaccsu_2x8x2_vint32m4_t:
+** ...
+** sf\.vqmaccsu\.2x8x2\tv[0-9]+,v[0-9]+,v[0-9]+
+** ...
+*/
+vint32m4_t
+test_sf_vqmaccsu_2x8x2_vint32m4_t (vint32m4_t vd, vint8m1_t vs1, vuint8m4_t vs2,
+				   size_t vl)
+{
+  return __riscv_sf_vqmaccsu_2x8x2 (vd, vs1, vs2, vl);
+}
+
+/*
+** test_sf_vqmaccsu_2x8x2_vint32m8_t:
+** ...
+** sf\.vqmaccsu\.2x8x2\tv[0-9]+,v[0-9]+,v[0-9]+
+** ...
+*/
+vint32m8_t
+test_sf_vqmaccsu_2x8x2_vint32m8_t (vint32m8_t vd, vint8m1_t vs1, vuint8m8_t vs2,
+				   size_t vl)
+{
+  return __riscv_sf_vqmaccsu_2x8x2 (vd, vs1, vs2, vl);
+}
+
+/*
+** test_sf_vqmaccsu_2x8x2_i32m1_tu_vint32m1_t:
+** ...
+** sf\.vqmaccsu\.2x8x2\tv[0-9]+,v[0-9]+,v[0-9]+
+** ...
+*/
+vint32m1_t
+test_sf_vqmaccsu_2x8x2_i32m1_tu_vint32m1_t (vint32m1_t vd, vint8m1_t vs1,
+					    vuint8m1_t vs2, size_t vl)
+{
+  return __riscv_sf_vqmaccsu_2x8x2_i32m1_tu (vd, vs1, vs2, vl);
+}
+
+/*
+** test_sf_vqmaccsu_2x8x2_i32m2_tu_vint32m2_t:
+** ...
+** sf\.vqmaccsu\.2x8x2\tv[0-9]+,v[0-9]+,v[0-9]+
+** ...
+*/
+vint32m2_t
+test_sf_vqmaccsu_2x8x2_i32m2_tu_vint32m2_t (vint32m2_t vd, vint8m1_t vs1,
+					    vuint8m2_t vs2, size_t vl)
+{
+  return __riscv_sf_vqmaccsu_2x8x2_i32m2_tu (vd, vs1, vs2, vl);
+}
+
+/*
+** test_sf_vqmaccsu_2x8x2_i32m4_tu_vint32m4_t:
+** ...
+** sf\.vqmaccsu\.2x8x2\tv[0-9]+,v[0-9]+,v[0-9]+
+** ...
+*/
+vint32m4_t
+test_sf_vqmaccsu_2x8x2_i32m4_tu_vint32m4_t (vint32m4_t vd, vint8m1_t vs1,
+					    vuint8m4_t vs2, size_t vl)
+{
+  return __riscv_sf_vqmaccsu_2x8x2_i32m4_tu (vd, vs1, vs2, vl);
+}
+
+/*
+** test_sf_vqmaccsu_2x8x2_i32m8_tu_vint32m8_t:
+** ...
+** sf\.vqmaccsu\.2x8x2\tv[0-9]+,v[0-9]+,v[0-9]+
+** ...
+*/
+vint32m8_t
+test_sf_vqmaccsu_2x8x2_i32m8_tu_vint32m8_t (vint32m8_t vd, vint8m1_t vs1,
+					    vuint8m8_t vs2, size_t vl)
+{
+  return __riscv_sf_vqmaccsu_2x8x2_i32m8_tu (vd, vs1, vs2, vl);
+}
+
+/*
+** test_sf_vqmaccsu_2x8x2_tu_vint32m1_t:
+** ...
+** sf\.vqmaccsu\.2x8x2\tv[0-9]+,v[0-9]+,v[0-9]+
+** ...
+*/
+vint32m1_t
+test_sf_vqmaccsu_2x8x2_tu_vint32m1_t (vint32m1_t vd, vint8m1_t vs1,
+				      vuint8m1_t vs2, size_t vl)
+{
+  return __riscv_sf_vqmaccsu_2x8x2_tu (vd, vs1, vs2, vl);
+}
+
+/*
+** test_sf_vqmaccsu_2x8x2_tu_vint32m2_t:
+** ...
+** sf\.vqmaccsu\.2x8x2\tv[0-9]+,v[0-9]+,v[0-9]+
+** ...
+*/
+vint32m2_t
+test_sf_vqmaccsu_2x8x2_tu_vint32m2_t (vint32m2_t vd, vint8m1_t vs1,
+				      vuint8m2_t vs2, size_t vl)
+{
+  return __riscv_sf_vqmaccsu_2x8x2_tu (vd, vs1, vs2, vl);
+}
+
+/*
+** test_sf_vqmaccsu_2x8x2_tu_vint32m4_t:
+** ...
+** sf\.vqmaccsu\.2x8x2\tv[0-9]+,v[0-9]+,v[0-9]+
+** ...
+*/
+vint32m4_t
+test_sf_vqmaccsu_2x8x2_tu_vint32m4_t (vint32m4_t vd, vint8m1_t vs1,
+				      vuint8m4_t vs2, size_t vl)
+{
+  return __riscv_sf_vqmaccsu_2x8x2_tu (vd, vs1, vs2, vl);
+}
+
+/*
+** test_sf_vqmaccsu_2x8x2_tu_vint32m8_t:
+** ...
+** sf\.vqmaccsu\.2x8x2\tv[0-9]+,v[0-9]+,v[0-9]+
+** ...
+*/
+vint32m8_t
+test_sf_vqmaccsu_2x8x2_tu_vint32m8_t (vint32m8_t vd, vint8m1_t vs1,
+				      vuint8m8_t vs2, size_t vl)
+{
+  return __riscv_sf_vqmaccsu_2x8x2_tu (vd, vs1, vs2, vl);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vqmaccsu_4x8x4.c b/gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vqmaccsu_4x8x4.c
new file mode 100644
index 00000000000..0554e564253
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vqmaccsu_4x8x4.c
@@ -0,0 +1,213 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_xsfvqmaccqoq -mabi=lp64d -O3" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "riscv_vector.h"
+
+/*
+** test_sf_vqmaccsu_4x8x4_i32m1_vint32m1_t:
+** ...
+** sf\.vqmaccsu\.4x8x4\tv[0-9]+,v[0-9]+,v[0-9]+
+** ...
+*/
+vint32m1_t
+test_sf_vqmaccsu_4x8x4_i32m1_vint32m1_t (vint32m1_t vd, vint8m1_t vs1,
+					 vuint8mf2_t vs2, size_t vl)
+{
+  return __riscv_sf_vqmaccsu_4x8x4_i32m1 (vd, vs1, vs2, vl);
+}
+
+/*
+** test_sf_vqmaccsu_4x8x4_i32m2_vint32m2_t:
+** ...
+** sf\.vqmaccsu\.4x8x4\tv[0-9]+,v[0-9]+,v[0-9]+
+** ...
+*/
+vint32m2_t
+test_sf_vqmaccsu_4x8x4_i32m2_vint32m2_t (vint32m2_t vd, vint8m1_t vs1,
+					 vuint8m1_t vs2, size_t vl)
+{
+  return __riscv_sf_vqmaccsu_4x8x4_i32m2 (vd, vs1, vs2, vl);
+}
+
+/*
+** test_sf_vqmaccsu_4x8x4_i32m4_vint32m4_t:
+** ...
+** sf\.vqmaccsu\.4x8x4\tv[0-9]+,v[0-9]+,v[0-9]+
+** ...
+*/
+vint32m4_t
+test_sf_vqmaccsu_4x8x4_i32m4_vint32m4_t (vint32m4_t vd, vint8m1_t vs1,
+					 vuint8m2_t vs2, size_t vl)
+{
+  return __riscv_sf_vqmaccsu_4x8x4_i32m4 (vd, vs1, vs2, vl);
+}
+
+/*
+** test_sf_vqmaccsu_4x8x4_i32m8_vint32m8_t:
+** ...
+** sf\.vqmaccsu\.4x8x4\tv[0-9]+,v[0-9]+,v[0-9]+
+** ...
+*/
+vint32m8_t
+test_sf_vqmaccsu_4x8x4_i32m8_vint32m8_t (vint32m8_t vd, vint8m1_t vs1,
+					 vuint8m4_t vs2, size_t vl)
+{
+  return __riscv_sf_vqmaccsu_4x8x4_i32m8 (vd, vs1, vs2, vl);
+}
+
+/*
+** test_sf_vqmaccsu_4x8x4_vint32m1_t:
+** ...
+** sf\.vqmaccsu\.4x8x4\tv[0-9]+,v[0-9]+,v[0-9]+
+** ...
+*/
+vint32m1_t
+test_sf_vqmaccsu_4x8x4_vint32m1_t (vint32m1_t vd, vint8m1_t vs1,
+				   vuint8mf2_t vs2, size_t vl)
+{
+  return __riscv_sf_vqmaccsu_4x8x4 (vd, vs1, vs2, vl);
+}
+
+/*
+** test_sf_vqmaccsu_4x8x4_vint32m2_t:
+** ...
+** sf\.vqmaccsu\.4x8x4\tv[0-9]+,v[0-9]+,v[0-9]+
+** ...
+*/
+vint32m2_t
+test_sf_vqmaccsu_4x8x4_vint32m2_t (vint32m2_t vd, vint8m1_t vs1, vuint8m1_t vs2,
+				   size_t vl)
+{
+  return __riscv_sf_vqmaccsu_4x8x4 (vd, vs1, vs2, vl);
+}
+
+/*
+** test_sf_vqmaccsu_4x8x4_vint32m4_t:
+** ...
+** sf\.vqmaccsu\.4x8x4\tv[0-9]+,v[0-9]+,v[0-9]+
+** ...
+*/
+vint32m4_t
+test_sf_vqmaccsu_4x8x4_vint32m4_t (vint32m4_t vd, vint8m1_t vs1, vuint8m2_t vs2,
+				   size_t vl)
+{
+  return __riscv_sf_vqmaccsu_4x8x4 (vd, vs1, vs2, vl);
+}
+
+/*
+** test_sf_vqmaccsu_4x8x4_vint32m8_t:
+** ...
+** sf\.vqmaccsu\.4x8x4\tv[0-9]+,v[0-9]+,v[0-9]+
+** ...
+*/
+vint32m8_t
+test_sf_vqmaccsu_4x8x4_vint32m8_t (vint32m8_t vd, vint8m1_t vs1, vuint8m4_t vs2,
+				   size_t vl)
+{
+  return __riscv_sf_vqmaccsu_4x8x4 (vd, vs1, vs2, vl);
+}
+
+/*
+** test_sf_vqmaccsu_4x8x4_i32m1_tu_vint32m1_t:
+** ...
+** sf\.vqmaccsu\.4x8x4\tv[0-9]+,v[0-9]+,v[0-9]+
+** ...
+*/
+vint32m1_t
+test_sf_vqmaccsu_4x8x4_i32m1_tu_vint32m1_t (vint32m1_t vd, vint8m1_t vs1,
+					    vuint8mf2_t vs2, size_t vl)
+{
+  return __riscv_sf_vqmaccsu_4x8x4_i32m1_tu (vd, vs1, vs2, vl);
+}
+
+/*
+** test_sf_vqmaccsu_4x8x4_i32m2_tu_vint32m2_t:
+** ...
+** sf\.vqmaccsu\.4x8x4\tv[0-9]+,v[0-9]+,v[0-9]+
+** ...
+*/
+vint32m2_t
+test_sf_vqmaccsu_4x8x4_i32m2_tu_vint32m2_t (vint32m2_t vd, vint8m1_t vs1,
+					    vuint8m1_t vs2, size_t vl)
+{
+  return __riscv_sf_vqmaccsu_4x8x4_i32m2_tu (vd, vs1, vs2, vl);
+}
+
+/*
+** test_sf_vqmaccsu_4x8x4_i32m4_tu_vint32m4_t:
+** ...
+** sf\.vqmaccsu\.4x8x4\tv[0-9]+,v[0-9]+,v[0-9]+
+** ...
+*/
+vint32m4_t
+test_sf_vqmaccsu_4x8x4_i32m4_tu_vint32m4_t (vint32m4_t vd, vint8m1_t vs1,
+					    vuint8m2_t vs2, size_t vl)
+{
+  return __riscv_sf_vqmaccsu_4x8x4_i32m4_tu (vd, vs1, vs2, vl);
+}
+
+/*
+** test_sf_vqmaccsu_4x8x4_i32m8_tu_vint32m8_t:
+** ...
+** sf\.vqmaccsu\.4x8x4\tv[0-9]+,v[0-9]+,v[0-9]+
+** ...
+*/
+vint32m8_t
+test_sf_vqmaccsu_4x8x4_i32m8_tu_vint32m8_t (vint32m8_t vd, vint8m1_t vs1,
+					    vuint8m4_t vs2, size_t vl)
+{
+  return __riscv_sf_vqmaccsu_4x8x4_i32m8_tu (vd, vs1, vs2, vl);
+}
+
+/*
+** test_sf_vqmaccsu_4x8x4_tu_vint32m1_t:
+** ...
+** sf\.vqmaccsu\.4x8x4\tv[0-9]+,v[0-9]+,v[0-9]+
+** ...
+*/
+vint32m1_t
+test_sf_vqmaccsu_4x8x4_tu_vint32m1_t (vint32m1_t vd, vint8m1_t vs1,
+				      vuint8mf2_t vs2, size_t vl)
+{
+  return __riscv_sf_vqmaccsu_4x8x4_tu (vd, vs1, vs2, vl);
+}
+
+/*
+** test_sf_vqmaccsu_4x8x4_tu_vint32m2_t:
+** ...
+** sf\.vqmaccsu\.4x8x4\tv[0-9]+,v[0-9]+,v[0-9]+
+** ...
+*/
+vint32m2_t
+test_sf_vqmaccsu_4x8x4_tu_vint32m2_t (vint32m2_t vd, vint8m1_t vs1,
+				      vuint8m1_t vs2, size_t vl)
+{
+  return __riscv_sf_vqmaccsu_4x8x4_tu (vd, vs1, vs2, vl);
+}
+
+/*
+** test_sf_vqmaccsu_4x8x4_tu_vint32m4_t:
+** ...
+** sf\.vqmaccsu\.4x8x4\tv[0-9]+,v[0-9]+,v[0-9]+
+** ...
+*/
+vint32m4_t
+test_sf_vqmaccsu_4x8x4_tu_vint32m4_t (vint32m4_t vd, vint8m1_t vs1,
+				      vuint8m2_t vs2, size_t vl)
+{
+  return __riscv_sf_vqmaccsu_4x8x4_tu (vd, vs1, vs2, vl);
+}
+
+/*
+** test_sf_vqmaccsu_4x8x4_tu_vint32m8_t:
+** ...
+** sf\.vqmaccsu\.4x8x4\tv[0-9]+,v[0-9]+,v[0-9]+
+** ...
+*/
+vint32m8_t
+test_sf_vqmaccsu_4x8x4_tu_vint32m8_t (vint32m8_t vd, vint8m1_t vs1,
+				      vuint8m4_t vs2, size_t vl)
+{
+  return __riscv_sf_vqmaccsu_4x8x4_tu (vd, vs1, vs2, vl);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vqmaccu_2x8x2.c b/gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vqmaccu_2x8x2.c
new file mode 100644
index 00000000000..dd15cc2d544
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vqmaccu_2x8x2.c
@@ -0,0 +1,213 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_xsfvqmaccdod -mabi=lp64d -O3" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "riscv_vector.h"
+
+/*
+** test_sf_vqmaccu_2x8x2_i32m1_vint32m1_t:
+** ...
+** sf\.vqmaccu\.2x8x2\tv[0-9]+,v[0-9]+,v[0-9]+
+** ...
+*/
+vint32m1_t
+test_sf_vqmaccu_2x8x2_i32m1_vint32m1_t (vint32m1_t vd, vuint8m1_t vs1,
+					vuint8m1_t vs2, size_t vl)
+{
+  return __riscv_sf_vqmaccu_2x8x2_i32m1 (vd, vs1, vs2, vl);
+}
+
+/*
+** test_sf_vqmaccu_2x8x2_i32m2_vint32m2_t:
+** ...
+** sf\.vqmaccu\.2x8x2\tv[0-9]+,v[0-9]+,v[0-9]+
+** ...
+*/
+vint32m2_t
+test_sf_vqmaccu_2x8x2_i32m2_vint32m2_t (vint32m2_t vd, vuint8m1_t vs1,
+					vuint8m2_t vs2, size_t vl)
+{
+  return __riscv_sf_vqmaccu_2x8x2_i32m2 (vd, vs1, vs2, vl);
+}
+
+/*
+** test_sf_vqmaccu_2x8x2_i32m4_vint32m4_t:
+** ...
+** sf\.vqmaccu\.2x8x2\tv[0-9]+,v[0-9]+,v[0-9]+
+** ...
+*/
+vint32m4_t
+test_sf_vqmaccu_2x8x2_i32m4_vint32m4_t (vint32m4_t vd, vuint8m1_t vs1,
+					vuint8m4_t vs2, size_t vl)
+{
+  return __riscv_sf_vqmaccu_2x8x2_i32m4 (vd, vs1, vs2, vl);
+}
+
+/*
+** test_sf_vqmaccu_2x8x2_i32m8_vint32m8_t:
+** ...
+** sf\.vqmaccu\.2x8x2\tv[0-9]+,v[0-9]+,v[0-9]+
+** ...
+*/
+vint32m8_t
+test_sf_vqmaccu_2x8x2_i32m8_vint32m8_t (vint32m8_t vd, vuint8m1_t vs1,
+					vuint8m8_t vs2, size_t vl)
+{
+  return __riscv_sf_vqmaccu_2x8x2_i32m8 (vd, vs1, vs2, vl);
+}
+
+/*
+** test_sf_vqmaccu_2x8x2_vint32m1_t:
+** ...
+** sf\.vqmaccu\.2x8x2\tv[0-9]+,v[0-9]+,v[0-9]+
+** ...
+*/
+vint32m1_t
+test_sf_vqmaccu_2x8x2_vint32m1_t (vint32m1_t vd, vuint8m1_t vs1, vuint8m1_t vs2,
+				  size_t vl)
+{
+  return __riscv_sf_vqmaccu_2x8x2 (vd, vs1, vs2, vl);
+}
+
+/*
+** test_sf_vqmaccu_2x8x2_vint32m2_t:
+** ...
+** sf\.vqmaccu\.2x8x2\tv[0-9]+,v[0-9]+,v[0-9]+
+** ...
+*/
+vint32m2_t
+test_sf_vqmaccu_2x8x2_vint32m2_t (vint32m2_t vd, vuint8m1_t vs1, vuint8m2_t vs2,
+				  size_t vl)
+{
+  return __riscv_sf_vqmaccu_2x8x2 (vd, vs1, vs2, vl);
+}
+
+/*
+** test_sf_vqmaccu_2x8x2_vint32m4_t:
+** ...
+** sf\.vqmaccu\.2x8x2\tv[0-9]+,v[0-9]+,v[0-9]+
+** ...
+*/
+vint32m4_t
+test_sf_vqmaccu_2x8x2_vint32m4_t (vint32m4_t vd, vuint8m1_t vs1, vuint8m4_t vs2,
+				  size_t vl)
+{
+  return __riscv_sf_vqmaccu_2x8x2 (vd, vs1, vs2, vl);
+}
+
+/*
+** test_sf_vqmaccu_2x8x2_vint32m8_t:
+** ...
+** sf\.vqmaccu\.2x8x2\tv[0-9]+,v[0-9]+,v[0-9]+
+** ...
+*/
+vint32m8_t
+test_sf_vqmaccu_2x8x2_vint32m8_t (vint32m8_t vd, vuint8m1_t vs1, vuint8m8_t vs2,
+				  size_t vl)
+{
+  return __riscv_sf_vqmaccu_2x8x2 (vd, vs1, vs2, vl);
+}
+
+/*
+** test_sf_vqmaccu_2x8x2_i32m1_tu_vint32m1_t:
+** ...
+** sf\.vqmaccu\.2x8x2\tv[0-9]+,v[0-9]+,v[0-9]+
+** ...
+*/
+vint32m1_t
+test_sf_vqmaccu_2x8x2_i32m1_tu_vint32m1_t (vint32m1_t vd, vuint8m1_t vs1,
+					   vuint8m1_t vs2, size_t vl)
+{
+  return __riscv_sf_vqmaccu_2x8x2_i32m1_tu (vd, vs1, vs2, vl);
+}
+
+/*
+** test_sf_vqmaccu_2x8x2_i32m2_tu_vint32m2_t:
+** ...
+** sf\.vqmaccu\.2x8x2\tv[0-9]+,v[0-9]+,v[0-9]+
+** ...
+*/
+vint32m2_t
+test_sf_vqmaccu_2x8x2_i32m2_tu_vint32m2_t (vint32m2_t vd, vuint8m1_t vs1,
+					   vuint8m2_t vs2, size_t vl)
+{
+  return __riscv_sf_vqmaccu_2x8x2_i32m2_tu (vd, vs1, vs2, vl);
+}
+
+/*
+** test_sf_vqmaccu_2x8x2_i32m4_tu_vint32m4_t:
+** ...
+** sf\.vqmaccu\.2x8x2\tv[0-9]+,v[0-9]+,v[0-9]+
+** ...
+*/
+vint32m4_t
+test_sf_vqmaccu_2x8x2_i32m4_tu_vint32m4_t (vint32m4_t vd, vuint8m1_t vs1,
+					   vuint8m4_t vs2, size_t vl)
+{
+  return __riscv_sf_vqmaccu_2x8x2_i32m4_tu (vd, vs1, vs2, vl);
+}
+
+/*
+** test_sf_vqmaccu_2x8x2_i32m8_tu_vint32m8_t:
+** ...
+** sf\.vqmaccu\.2x8x2\tv[0-9]+,v[0-9]+,v[0-9]+
+** ...
+*/
+vint32m8_t
+test_sf_vqmaccu_2x8x2_i32m8_tu_vint32m8_t (vint32m8_t vd, vuint8m1_t vs1,
+					   vuint8m8_t vs2, size_t vl)
+{
+  return __riscv_sf_vqmaccu_2x8x2_i32m8_tu (vd, vs1, vs2, vl);
+}
+
+/*
+** test_sf_vqmaccu_2x8x2_tu_vint32m1_t:
+** ...
+** sf\.vqmaccu\.2x8x2\tv[0-9]+,v[0-9]+,v[0-9]+
+** ...
+*/
+vint32m1_t
+test_sf_vqmaccu_2x8x2_tu_vint32m1_t (vint32m1_t vd, vuint8m1_t vs1,
+				     vuint8m1_t vs2, size_t vl)
+{
+  return __riscv_sf_vqmaccu_2x8x2_tu (vd, vs1, vs2, vl);
+}
+
+/*
+** test_sf_vqmaccu_2x8x2_tu_vint32m2_t:
+** ...
+** sf\.vqmaccu\.2x8x2\tv[0-9]+,v[0-9]+,v[0-9]+
+** ...
+*/
+vint32m2_t
+test_sf_vqmaccu_2x8x2_tu_vint32m2_t (vint32m2_t vd, vuint8m1_t vs1,
+				     vuint8m2_t vs2, size_t vl)
+{
+  return __riscv_sf_vqmaccu_2x8x2_tu (vd, vs1, vs2, vl);
+}
+
+/*
+** test_sf_vqmaccu_2x8x2_tu_vint32m4_t:
+** ...
+** sf\.vqmaccu\.2x8x2\tv[0-9]+,v[0-9]+,v[0-9]+
+** ...
+*/
+vint32m4_t
+test_sf_vqmaccu_2x8x2_tu_vint32m4_t (vint32m4_t vd, vuint8m1_t vs1,
+				     vuint8m4_t vs2, size_t vl)
+{
+  return __riscv_sf_vqmaccu_2x8x2_tu (vd, vs1, vs2, vl);
+}
+
+/*
+** test_sf_vqmaccu_2x8x2_tu_vint32m8_t:
+** ...
+** sf\.vqmaccu\.2x8x2\tv[0-9]+,v[0-9]+,v[0-9]+
+** ...
+*/
+vint32m8_t
+test_sf_vqmaccu_2x8x2_tu_vint32m8_t (vint32m8_t vd, vuint8m1_t vs1,
+				     vuint8m8_t vs2, size_t vl)
+{
+  return __riscv_sf_vqmaccu_2x8x2_tu (vd, vs1, vs2, vl);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vqmaccu_4x8x4.c b/gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vqmaccu_4x8x4.c
new file mode 100644
index 00000000000..c386b4ee79e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vqmaccu_4x8x4.c
@@ -0,0 +1,213 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_xsfvqmaccqoq -mabi=lp64d -O3" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "riscv_vector.h"
+
+/*
+** test_sf_vqmaccu_4x8x4_i32m1_vint32m1_t:
+** ...
+** sf\.vqmaccu\.4x8x4\tv[0-9]+,v[0-9]+,v[0-9]+
+** ...
+*/
+vint32m1_t
+test_sf_vqmaccu_4x8x4_i32m1_vint32m1_t (vint32m1_t vd, vuint8m1_t vs1,
+					vuint8mf2_t vs2, size_t vl)
+{
+  return __riscv_sf_vqmaccu_4x8x4_i32m1 (vd, vs1, vs2, vl);
+}
+
+/*
+** test_sf_vqmaccu_4x8x4_i32m2_vint32m2_t:
+** ...
+** sf\.vqmaccu\.4x8x4\tv[0-9]+,v[0-9]+,v[0-9]+
+** ...
+*/
+vint32m2_t
+test_sf_vqmaccu_4x8x4_i32m2_vint32m2_t (vint32m2_t vd, vuint8m1_t vs1,
+					vuint8m1_t vs2, size_t vl)
+{
+  return __riscv_sf_vqmaccu_4x8x4_i32m2 (vd, vs1, vs2, vl);
+}
+
+/*
+** test_sf_vqmaccu_4x8x4_i32m4_vint32m4_t:
+** ...
+** sf\.vqmaccu\.4x8x4\tv[0-9]+,v[0-9]+,v[0-9]+
+** ...
+*/
+vint32m4_t
+test_sf_vqmaccu_4x8x4_i32m4_vint32m4_t (vint32m4_t vd, vuint8m1_t vs1,
+					vuint8m2_t vs2, size_t vl)
+{
+  return __riscv_sf_vqmaccu_4x8x4_i32m4 (vd, vs1, vs2, vl);
+}
+
+/*
+** test_sf_vqmaccu_4x8x4_i32m8_vint32m8_t:
+** ...
+** sf\.vqmaccu\.4x8x4\tv[0-9]+,v[0-9]+,v[0-9]+
+** ...
+*/
+vint32m8_t
+test_sf_vqmaccu_4x8x4_i32m8_vint32m8_t (vint32m8_t vd, vuint8m1_t vs1,
+					vuint8m4_t vs2, size_t vl)
+{
+  return __riscv_sf_vqmaccu_4x8x4_i32m8 (vd, vs1, vs2, vl);
+}
+
+/*
+** test_sf_vqmaccu_4x8x4_vint32m1_t:
+** ...
+** sf\.vqmaccu\.4x8x4\tv[0-9]+,v[0-9]+,v[0-9]+
+** ...
+*/
+vint32m1_t
+test_sf_vqmaccu_4x8x4_vint32m1_t (vint32m1_t vd, vuint8m1_t vs1,
+				  vuint8mf2_t vs2, size_t vl)
+{
+  return __riscv_sf_vqmaccu_4x8x4 (vd, vs1, vs2, vl);
+}
+
+/*
+** test_sf_vqmaccu_4x8x4_vint32m2_t:
+** ...
+** sf\.vqmaccu\.4x8x4\tv[0-9]+,v[0-9]+,v[0-9]+
+** ...
+*/
+vint32m2_t
+test_sf_vqmaccu_4x8x4_vint32m2_t (vint32m2_t vd, vuint8m1_t vs1, vuint8m1_t vs2,
+				  size_t vl)
+{
+  return __riscv_sf_vqmaccu_4x8x4 (vd, vs1, vs2, vl);
+}
+
+/*
+** test_sf_vqmaccu_4x8x4_vint32m4_t:
+** ...
+** sf\.vqmaccu\.4x8x4\tv[0-9]+,v[0-9]+,v[0-9]+
+** ...
+*/
+vint32m4_t
+test_sf_vqmaccu_4x8x4_vint32m4_t (vint32m4_t vd, vuint8m1_t vs1, vuint8m2_t vs2,
+				  size_t vl)
+{
+  return __riscv_sf_vqmaccu_4x8x4 (vd, vs1, vs2, vl);
+}
+
+/*
+** test_sf_vqmaccu_4x8x4_vint32m8_t:
+** ...
+** sf\.vqmaccu\.4x8x4\tv[0-9]+,v[0-9]+,v[0-9]+
+** ...
+*/
+vint32m8_t
+test_sf_vqmaccu_4x8x4_vint32m8_t (vint32m8_t vd, vuint8m1_t vs1, vuint8m4_t vs2,
+				  size_t vl)
+{
+  return __riscv_sf_vqmaccu_4x8x4 (vd, vs1, vs2, vl);
+}
+
+/*
+** test_sf_vqmaccu_4x8x4_i32m1_tu_vint32m1_t:
+** ...
+** sf\.vqmaccu\.4x8x4\tv[0-9]+,v[0-9]+,v[0-9]+
+** ...
+*/
+vint32m1_t
+test_sf_vqmaccu_4x8x4_i32m1_tu_vint32m1_t (vint32m1_t vd, vuint8m1_t vs1,
+					   vuint8mf2_t vs2, size_t vl)
+{
+  return __riscv_sf_vqmaccu_4x8x4_i32m1_tu (vd, vs1, vs2, vl);
+}
+
+/*
+** test_sf_vqmaccu_4x8x4_i32m2_tu_vint32m2_t:
+** ...
+** sf\.vqmaccu\.4x8x4\tv[0-9]+,v[0-9]+,v[0-9]+
+** ...
+*/
+vint32m2_t
+test_sf_vqmaccu_4x8x4_i32m2_tu_vint32m2_t (vint32m2_t vd, vuint8m1_t vs1,
+					   vuint8m1_t vs2, size_t vl)
+{
+  return __riscv_sf_vqmaccu_4x8x4_i32m2_tu (vd, vs1, vs2, vl);
+}
+
+/*
+** test_sf_vqmaccu_4x8x4_i32m4_tu_vint32m4_t:
+** ...
+** sf\.vqmaccu\.4x8x4\tv[0-9]+,v[0-9]+,v[0-9]+
+** ...
+*/
+vint32m4_t
+test_sf_vqmaccu_4x8x4_i32m4_tu_vint32m4_t (vint32m4_t vd, vuint8m1_t vs1,
+					   vuint8m2_t vs2, size_t vl)
+{
+  return __riscv_sf_vqmaccu_4x8x4_i32m4_tu (vd, vs1, vs2, vl);
+}
+
+/*
+** test_sf_vqmaccu_4x8x4_i32m8_tu_vint32m8_t:
+** ...
+** sf\.vqmaccu\.4x8x4\tv[0-9]+,v[0-9]+,v[0-9]+
+** ...
+*/
+vint32m8_t
+test_sf_vqmaccu_4x8x4_i32m8_tu_vint32m8_t (vint32m8_t vd, vuint8m1_t vs1,
+					   vuint8m4_t vs2, size_t vl)
+{
+  return __riscv_sf_vqmaccu_4x8x4_i32m8_tu (vd, vs1, vs2, vl);
+}
+
+/*
+** test_sf_vqmaccu_4x8x4_tu_vint32m1_t:
+** ...
+** sf\.vqmaccu\.4x8x4\tv[0-9]+,v[0-9]+,v[0-9]+
+** ...
+*/
+vint32m1_t
+test_sf_vqmaccu_4x8x4_tu_vint32m1_t (vint32m1_t vd, vuint8m1_t vs1,
+				     vuint8mf2_t vs2, size_t vl)
+{
+  return __riscv_sf_vqmaccu_4x8x4_tu (vd, vs1, vs2, vl);
+}
+
+/*
+** test_sf_vqmaccu_4x8x4_tu_vint32m2_t:
+** ...
+** sf\.vqmaccu\.4x8x4\tv[0-9]+,v[0-9]+,v[0-9]+
+** ...
+*/
+vint32m2_t
+test_sf_vqmaccu_4x8x4_tu_vint32m2_t (vint32m2_t vd, vuint8m1_t vs1,
+				     vuint8m1_t vs2, size_t vl)
+{
+  return __riscv_sf_vqmaccu_4x8x4_tu (vd, vs1, vs2, vl);
+}
+
+/*
+** test_sf_vqmaccu_4x8x4_tu_vint32m4_t:
+** ...
+** sf\.vqmaccu\.4x8x4\tv[0-9]+,v[0-9]+,v[0-9]+
+** ...
+*/
+vint32m4_t
+test_sf_vqmaccu_4x8x4_tu_vint32m4_t (vint32m4_t vd, vuint8m1_t vs1,
+				     vuint8m2_t vs2, size_t vl)
+{
+  return __riscv_sf_vqmaccu_4x8x4_tu (vd, vs1, vs2, vl);
+}
+
+/*
+** test_sf_vqmaccu_4x8x4_tu_vint32m8_t:
+** ...
+** sf\.vqmaccu\.4x8x4\tv[0-9]+,v[0-9]+,v[0-9]+
+** ...
+*/
+vint32m8_t
+test_sf_vqmaccu_4x8x4_tu_vint32m8_t (vint32m8_t vd, vuint8m1_t vs1,
+				     vuint8m4_t vs2, size_t vl)
+{
+  return __riscv_sf_vqmaccu_4x8x4_tu (vd, vs1, vs2, vl);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vqmaccus_2x8x2.c b/gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vqmaccus_2x8x2.c
new file mode 100644
index 00000000000..db1650eb6ad
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vqmaccus_2x8x2.c
@@ -0,0 +1,213 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_xsfvqmaccdod -mabi=lp64d -O3" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "riscv_vector.h"
+
+/*
+** test_sf_vqmaccus_2x8x2_i32m1_vint32m1_t:
+** ...
+** sf\.vqmaccus\.2x8x2\tv[0-9]+,v[0-9]+,v[0-9]+
+** ...
+*/
+vint32m1_t
+test_sf_vqmaccus_2x8x2_i32m1_vint32m1_t (vint32m1_t vd, vuint8m1_t vs1,
+					 vint8m1_t vs2, size_t vl)
+{
+  return __riscv_sf_vqmaccus_2x8x2_i32m1 (vd, vs1, vs2, vl);
+}
+
+/*
+** test_sf_vqmaccus_2x8x2_i32m2_vint32m2_t:
+** ...
+** sf\.vqmaccus\.2x8x2\tv[0-9]+,v[0-9]+,v[0-9]+
+** ...
+*/
+vint32m2_t
+test_sf_vqmaccus_2x8x2_i32m2_vint32m2_t (vint32m2_t vd, vuint8m1_t vs1,
+					 vint8m2_t vs2, size_t vl)
+{
+  return __riscv_sf_vqmaccus_2x8x2_i32m2 (vd, vs1, vs2, vl);
+}
+
+/*
+** test_sf_vqmaccus_2x8x2_i32m4_vint32m4_t:
+** ...
+** sf\.vqmaccus\.2x8x2\tv[0-9]+,v[0-9]+,v[0-9]+
+** ...
+*/
+vint32m4_t
+test_sf_vqmaccus_2x8x2_i32m4_vint32m4_t (vint32m4_t vd, vuint8m1_t vs1,
+					 vint8m4_t vs2, size_t vl)
+{
+  return __riscv_sf_vqmaccus_2x8x2_i32m4 (vd, vs1, vs2, vl);
+}
+
+/*
+** test_sf_vqmaccus_2x8x2_i32m8_vint32m8_t:
+** ...
+** sf\.vqmaccus\.2x8x2\tv[0-9]+,v[0-9]+,v[0-9]+
+** ...
+*/
+vint32m8_t
+test_sf_vqmaccus_2x8x2_i32m8_vint32m8_t (vint32m8_t vd, vuint8m1_t vs1,
+					 vint8m8_t vs2, size_t vl)
+{
+  return __riscv_sf_vqmaccus_2x8x2_i32m8 (vd, vs1, vs2, vl);
+}
+
+/*
+** test_sf_vqmaccus_2x8x2_vint32m1_t:
+** ...
+** sf\.vqmaccus\.2x8x2\tv[0-9]+,v[0-9]+,v[0-9]+
+** ...
+*/
+vint32m1_t
+test_sf_vqmaccus_2x8x2_vint32m1_t (vint32m1_t vd, vuint8m1_t vs1, vint8m1_t vs2,
+				   size_t vl)
+{
+  return __riscv_sf_vqmaccus_2x8x2 (vd, vs1, vs2, vl);
+}
+
+/*
+** test_sf_vqmaccus_2x8x2_vint32m2_t:
+** ...
+** sf\.vqmaccus\.2x8x2\tv[0-9]+,v[0-9]+,v[0-9]+
+** ...
+*/
+vint32m2_t
+test_sf_vqmaccus_2x8x2_vint32m2_t (vint32m2_t vd, vuint8m1_t vs1, vint8m2_t vs2,
+				   size_t vl)
+{
+  return __riscv_sf_vqmaccus_2x8x2 (vd, vs1, vs2, vl);
+}
+
+/*
+** test_sf_vqmaccus_2x8x2_vint32m4_t:
+** ...
+** sf\.vqmaccus\.2x8x2\tv[0-9]+,v[0-9]+,v[0-9]+
+** ...
+*/
+vint32m4_t
+test_sf_vqmaccus_2x8x2_vint32m4_t (vint32m4_t vd, vuint8m1_t vs1, vint8m4_t vs2,
+				   size_t vl)
+{
+  return __riscv_sf_vqmaccus_2x8x2 (vd, vs1, vs2, vl);
+}
+
+/*
+** test_sf_vqmaccus_2x8x2_vint32m8_t:
+** ...
+** sf\.vqmaccus\.2x8x2\tv[0-9]+,v[0-9]+,v[0-9]+
+** ...
+*/
+vint32m8_t
+test_sf_vqmaccus_2x8x2_vint32m8_t (vint32m8_t vd, vuint8m1_t vs1, vint8m8_t vs2,
+				   size_t vl)
+{
+  return __riscv_sf_vqmaccus_2x8x2 (vd, vs1, vs2, vl);
+}
+
+/*
+** test_sf_vqmaccus_2x8x2_i32m1_tu_vint32m1_t:
+** ...
+** sf\.vqmaccus\.2x8x2\tv[0-9]+,v[0-9]+,v[0-9]+
+** ...
+*/
+vint32m1_t
+test_sf_vqmaccus_2x8x2_i32m1_tu_vint32m1_t (vint32m1_t vd, vuint8m1_t vs1,
+					    vint8m1_t vs2, size_t vl)
+{
+  return __riscv_sf_vqmaccus_2x8x2_i32m1_tu (vd, vs1, vs2, vl);
+}
+
+/*
+** test_sf_vqmaccus_2x8x2_i32m2_tu_vint32m2_t:
+** ...
+** sf\.vqmaccus\.2x8x2\tv[0-9]+,v[0-9]+,v[0-9]+
+** ...
+*/
+vint32m2_t
+test_sf_vqmaccus_2x8x2_i32m2_tu_vint32m2_t (vint32m2_t vd, vuint8m1_t vs1,
+					    vint8m2_t vs2, size_t vl)
+{
+  return __riscv_sf_vqmaccus_2x8x2_i32m2_tu (vd, vs1, vs2, vl);
+}
+
+/*
+** test_sf_vqmaccus_2x8x2_i32m4_tu_vint32m4_t:
+** ...
+** sf\.vqmaccus\.2x8x2\tv[0-9]+,v[0-9]+,v[0-9]+
+** ...
+*/
+vint32m4_t
+test_sf_vqmaccus_2x8x2_i32m4_tu_vint32m4_t (vint32m4_t vd, vuint8m1_t vs1,
+					    vint8m4_t vs2, size_t vl)
+{
+  return __riscv_sf_vqmaccus_2x8x2_i32m4_tu (vd, vs1, vs2, vl);
+}
+
+/*
+** test_sf_vqmaccus_2x8x2_i32m8_tu_vint32m8_t:
+** ...
+** sf\.vqmaccus\.2x8x2\tv[0-9]+,v[0-9]+,v[0-9]+
+** ...
+*/
+vint32m8_t
+test_sf_vqmaccus_2x8x2_i32m8_tu_vint32m8_t (vint32m8_t vd, vuint8m1_t vs1,
+					    vint8m8_t vs2, size_t vl)
+{
+  return __riscv_sf_vqmaccus_2x8x2_i32m8_tu (vd, vs1, vs2, vl);
+}
+
+/*
+** test_sf_vqmaccus_2x8x2_tu_vint32m1_t:
+** ...
+** sf\.vqmaccus\.2x8x2\tv[0-9]+,v[0-9]+,v[0-9]+
+** ...
+*/
+vint32m1_t
+test_sf_vqmaccus_2x8x2_tu_vint32m1_t (vint32m1_t vd, vuint8m1_t vs1,
+				      vint8m1_t vs2, size_t vl)
+{
+  return __riscv_sf_vqmaccus_2x8x2_tu (vd, vs1, vs2, vl);
+}
+
+/*
+** test_sf_vqmaccus_2x8x2_tu_vint32m2_t:
+** ...
+** sf\.vqmaccus\.2x8x2\tv[0-9]+,v[0-9]+,v[0-9]+
+** ...
+*/
+vint32m2_t
+test_sf_vqmaccus_2x8x2_tu_vint32m2_t (vint32m2_t vd, vuint8m1_t vs1,
+				      vint8m2_t vs2, size_t vl)
+{
+  return __riscv_sf_vqmaccus_2x8x2_tu (vd, vs1, vs2, vl);
+}
+
+/*
+** test_sf_vqmaccus_2x8x2_tu_vint32m4_t:
+** ...
+** sf\.vqmaccus\.2x8x2\tv[0-9]+,v[0-9]+,v[0-9]+
+** ...
+*/
+vint32m4_t
+test_sf_vqmaccus_2x8x2_tu_vint32m4_t (vint32m4_t vd, vuint8m1_t vs1,
+				      vint8m4_t vs2, size_t vl)
+{
+  return __riscv_sf_vqmaccus_2x8x2_tu (vd, vs1, vs2, vl);
+}
+
+/*
+** test_sf_vqmaccus_2x8x2_tu_vint32m8_t:
+** ...
+** sf\.vqmaccus\.2x8x2\tv[0-9]+,v[0-9]+,v[0-9]+
+** ...
+*/
+vint32m8_t
+test_sf_vqmaccus_2x8x2_tu_vint32m8_t (vint32m8_t vd, vuint8m1_t vs1,
+				      vint8m8_t vs2, size_t vl)
+{
+  return __riscv_sf_vqmaccus_2x8x2_tu (vd, vs1, vs2, vl);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vqmaccus_4x8x4.c b/gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vqmaccus_4x8x4.c
new file mode 100644
index 00000000000..5c5e1a043bc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vqmaccus_4x8x4.c
@@ -0,0 +1,213 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_xsfvqmaccqoq -mabi=lp64d -O3" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "riscv_vector.h"
+
+/*
+** test_sf_vqmaccus_4x8x4_i32m1_vint32m1_t:
+** ...
+** sf\.vqmaccus\.4x8x4\tv[0-9]+,v[0-9]+,v[0-9]+
+** ...
+*/
+vint32m1_t
+test_sf_vqmaccus_4x8x4_i32m1_vint32m1_t (vint32m1_t vd, vuint8m1_t vs1,
+					 vint8mf2_t vs2, size_t vl)
+{
+  return __riscv_sf_vqmaccus_4x8x4_i32m1 (vd, vs1, vs2, vl);
+}
+
+/*
+** test_sf_vqmaccus_4x8x4_i32m2_vint32m2_t:
+** ...
+** sf\.vqmaccus\.4x8x4\tv[0-9]+,v[0-9]+,v[0-9]+
+** ...
+*/
+vint32m2_t
+test_sf_vqmaccus_4x8x4_i32m2_vint32m2_t (vint32m2_t vd, vuint8m1_t vs1,
+					 vint8m1_t vs2, size_t vl)
+{
+  return __riscv_sf_vqmaccus_4x8x4_i32m2 (vd, vs1, vs2, vl);
+}
+
+/*
+** test_sf_vqmaccus_4x8x4_i32m4_vint32m4_t:
+** ...
+** sf\.vqmaccus\.4x8x4\tv[0-9]+,v[0-9]+,v[0-9]+
+** ...
+*/
+vint32m4_t
+test_sf_vqmaccus_4x8x4_i32m4_vint32m4_t (vint32m4_t vd, vuint8m1_t vs1,
+					 vint8m2_t vs2, size_t vl)
+{
+  return __riscv_sf_vqmaccus_4x8x4_i32m4 (vd, vs1, vs2, vl);
+}
+
+/*
+** test_sf_vqmaccus_4x8x4_i32m8_vint32m8_t:
+** ...
+** sf\.vqmaccus\.4x8x4\tv[0-9]+,v[0-9]+,v[0-9]+
+** ...
+*/
+vint32m8_t
+test_sf_vqmaccus_4x8x4_i32m8_vint32m8_t (vint32m8_t vd, vuint8m1_t vs1,
+					 vint8m4_t vs2, size_t vl)
+{
+  return __riscv_sf_vqmaccus_4x8x4_i32m8 (vd, vs1, vs2, vl);
+}
+
+/*
+** test_sf_vqmaccus_4x8x4_vint32m1_t:
+** ...
+** sf\.vqmaccus\.4x8x4\tv[0-9]+,v[0-9]+,v[0-9]+
+** ...
+*/
+vint32m1_t
+test_sf_vqmaccus_4x8x4_vint32m1_t (vint32m1_t vd, vuint8m1_t vs1,
+				   vint8mf2_t vs2, size_t vl)
+{
+  return __riscv_sf_vqmaccus_4x8x4 (vd, vs1, vs2, vl);
+}
+
+/*
+** test_sf_vqmaccus_4x8x4_vint32m2_t:
+** ...
+** sf\.vqmaccus\.4x8x4\tv[0-9]+,v[0-9]+,v[0-9]+
+** ...
+*/
+vint32m2_t
+test_sf_vqmaccus_4x8x4_vint32m2_t (vint32m2_t vd, vuint8m1_t vs1, vint8m1_t vs2,
+				   size_t vl)
+{
+  return __riscv_sf_vqmaccus_4x8x4 (vd, vs1, vs2, vl);
+}
+
+/*
+** test_sf_vqmaccus_4x8x4_vint32m4_t:
+** ...
+** sf\.vqmaccus\.4x8x4\tv[0-9]+,v[0-9]+,v[0-9]+
+** ...
+*/
+vint32m4_t
+test_sf_vqmaccus_4x8x4_vint32m4_t (vint32m4_t vd, vuint8m1_t vs1, vint8m2_t vs2,
+				   size_t vl)
+{
+  return __riscv_sf_vqmaccus_4x8x4 (vd, vs1, vs2, vl);
+}
+
+/*
+** test_sf_vqmaccus_4x8x4_vint32m8_t:
+** ...
+** sf\.vqmaccus\.4x8x4\tv[0-9]+,v[0-9]+,v[0-9]+
+** ...
+*/
+vint32m8_t
+test_sf_vqmaccus_4x8x4_vint32m8_t (vint32m8_t vd, vuint8m1_t vs1, vint8m4_t vs2,
+				   size_t vl)
+{
+  return __riscv_sf_vqmaccus_4x8x4 (vd, vs1, vs2, vl);
+}
+
+/*
+** test_sf_vqmaccus_4x8x4_i32m1_tu_vint32m1_t:
+** ...
+** sf\.vqmaccus\.4x8x4\tv[0-9]+,v[0-9]+,v[0-9]+
+** ...
+*/
+vint32m1_t
+test_sf_vqmaccus_4x8x4_i32m1_tu_vint32m1_t (vint32m1_t vd, vuint8m1_t vs1,
+					    vint8mf2_t vs2, size_t vl)
+{
+  return __riscv_sf_vqmaccus_4x8x4_i32m1_tu (vd, vs1, vs2, vl);
+}
+
+/*
+** test_sf_vqmaccus_4x8x4_i32m2_tu_vint32m2_t:
+** ...
+** sf\.vqmaccus\.4x8x4\tv[0-9]+,v[0-9]+,v[0-9]+
+** ...
+*/
+vint32m2_t
+test_sf_vqmaccus_4x8x4_i32m2_tu_vint32m2_t (vint32m2_t vd, vuint8m1_t vs1,
+					    vint8m1_t vs2, size_t vl)
+{
+  return __riscv_sf_vqmaccus_4x8x4_i32m2_tu (vd, vs1, vs2, vl);
+}
+
+/*
+** test_sf_vqmaccus_4x8x4_i32m4_tu_vint32m4_t:
+** ...
+** sf\.vqmaccus\.4x8x4\tv[0-9]+,v[0-9]+,v[0-9]+
+** ...
+*/
+vint32m4_t
+test_sf_vqmaccus_4x8x4_i32m4_tu_vint32m4_t (vint32m4_t vd, vuint8m1_t vs1,
+					    vint8m2_t vs2, size_t vl)
+{
+  return __riscv_sf_vqmaccus_4x8x4_i32m4_tu (vd, vs1, vs2, vl);
+}
+
+/*
+** test_sf_vqmaccus_4x8x4_i32m8_tu_vint32m8_t:
+** ...
+** sf\.vqmaccus\.4x8x4\tv[0-9]+,v[0-9]+,v[0-9]+
+** ...
+*/
+vint32m8_t
+test_sf_vqmaccus_4x8x4_i32m8_tu_vint32m8_t (vint32m8_t vd, vuint8m1_t vs1,
+					    vint8m4_t vs2, size_t vl)
+{
+  return __riscv_sf_vqmaccus_4x8x4_i32m8_tu (vd, vs1, vs2, vl);
+}
+
+/*
+** test_sf_vqmaccus_4x8x4_tu_vint32m1_t:
+** ...
+** sf\.vqmaccus\.4x8x4\tv[0-9]+,v[0-9]+,v[0-9]+
+** ...
+*/
+vint32m1_t
+test_sf_vqmaccus_4x8x4_tu_vint32m1_t (vint32m1_t vd, vuint8m1_t vs1,
+				      vint8mf2_t vs2, size_t vl)
+{
+  return __riscv_sf_vqmaccus_4x8x4_tu (vd, vs1, vs2, vl);
+}
+
+/*
+** test_sf_vqmaccus_4x8x4_tu_vint32m2_t:
+** ...
+** sf\.vqmaccus\.4x8x4\tv[0-9]+,v[0-9]+,v[0-9]+
+** ...
+*/
+vint32m2_t
+test_sf_vqmaccus_4x8x4_tu_vint32m2_t (vint32m2_t vd, vuint8m1_t vs1,
+				      vint8m1_t vs2, size_t vl)
+{
+  return __riscv_sf_vqmaccus_4x8x4_tu (vd, vs1, vs2, vl);
+}
+
+/*
+** test_sf_vqmaccus_4x8x4_tu_vint32m4_t:
+** ...
+** sf\.vqmaccus\.4x8x4\tv[0-9]+,v[0-9]+,v[0-9]+
+** ...
+*/
+vint32m4_t
+test_sf_vqmaccus_4x8x4_tu_vint32m4_t (vint32m4_t vd, vuint8m1_t vs1,
+				      vint8m2_t vs2, size_t vl)
+{
+  return __riscv_sf_vqmaccus_4x8x4_tu (vd, vs1, vs2, vl);
+}
+
+/*
+** test_sf_vqmaccus_4x8x4_tu_vint32m8_t:
+** ...
+** sf\.vqmaccus\.4x8x4\tv[0-9]+,v[0-9]+,v[0-9]+
+** ...
+*/
+vint32m8_t
+test_sf_vqmaccus_4x8x4_tu_vint32m8_t (vint32m8_t vd, vuint8m1_t vs1,
+				      vint8m4_t vs2, size_t vl)
+{
+  return __riscv_sf_vqmaccus_4x8x4_tu (vd, vs1, vs2, vl);
+}