diff mbox series

[v1] RISC-V: Fix incorrect optimization options passing to cond and builtin

Message ID 20241202142540.2693651-1-pan2.li@intel.com
State Committed
Commit dfb9f6e0ed358706ade9a007f8723c4e9ef538fc
Headers
Series [v1] RISC-V: Fix incorrect optimization options passing to cond and builtin |

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Commit Message

Li, Pan2 Dec. 2, 2024, 2:25 p.m. UTC 
  From: Pan Li <pan2.li@intel.com>

Like the strided load/store, the testcases of vector cond and builtin are
designed to pick up different sorts of optimization options but actually
these option are ignored according to the Execution log of gcc.log.
This patch would like to make it correct almost the same as what we
fixed for strided load/store.

The below test suites are passed for this patch.
* The rv64gcv fully regression test.

It is test only patch and obvious up to a point, will commit it
directly if no comments in next 48H.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/rvv.exp: Fix the incorrect optimization
	options passing to testcases.

Signed-off-by: Pan Li <pan2.li@intel.com>
---
 gcc/testsuite/gcc.target/riscv/rvv/rvv.exp | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

Comments

Kito Cheng Dec. 3, 2024, 1:02 a.m. UTC | #1 
LGTM

<pan2.li@intel.com> 於 2024年12月2日 週一 22:25 寫道：

> From: Pan Li <pan2.li@intel.com>
>
> Like the strided load/store, the testcases of vector cond and builtin are
> designed to pick up different sorts of optimization options but actually
> these option are ignored according to the Execution log of gcc.log.
> This patch would like to make it correct almost the same as what we
> fixed for strided load/store.
>
> The below test suites are passed for this patch.
> * The rv64gcv fully regression test.
>
> It is test only patch and obvious up to a point, will commit it
> directly if no comments in next 48H.
>
> gcc/testsuite/ChangeLog:
>
>         * gcc.target/riscv/rvv/rvv.exp: Fix the incorrect optimization
>         options passing to testcases.
>
> Signed-off-by: Pan Li <pan2.li@intel.com>
> ---
>  gcc/testsuite/gcc.target/riscv/rvv/rvv.exp | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp
> b/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp
> index 87c5ecb1a8b..87dea457608 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp
> @@ -75,9 +75,9 @@ foreach op $AUTOVEC_TEST_OPTS {
>    dg-runtest [lsort [glob -nocomplain
> $srcdir/$subdir/autovec/reduc/*.\[cS\]]] \
>      "" "$op"
>    dg-runtest [lsort [glob -nocomplain
> $srcdir/$subdir/autovec/cond/*.\[cS\]]] \
> -    "" "$op"
> +    "$op" ""
>    dg-runtest [lsort [glob -nocomplain
> $srcdir/$subdir/autovec/builtin/*.\[cS\]]] \
> -    "" "$op"
> +    "$op" ""
>  }
>
>  # widening operation only test on LMUL < 8
> --
> 2.43.0
>
>
diff mbox series

Patch

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp b/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp
index 87c5ecb1a8b..87dea457608 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp
+++ b/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp
@@ -75,9 +75,9 @@  foreach op $AUTOVEC_TEST_OPTS {
   dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/autovec/reduc/*.\[cS\]]] \
     "" "$op"
   dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/autovec/cond/*.\[cS\]]] \
-    "" "$op"
+    "$op" ""
   dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/autovec/builtin/*.\[cS\]]] \
-    "" "$op"
+    "$op" ""
 }
 
 # widening operation only test on LMUL < 8