diff mbox series

[v1,2/2] RISC-V: Refactor the testcases for bswap16-0

Message ID 20241204020812.3604240-2-pan2.li@intel.com
State Committed
Headers
Series [v1,1/2] RISC-V: Fix incorrect optimization options passing to convert and unop |

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Commit Message

Li, Pan2 Dec. 4, 2024, 2:08 a.m. UTC 
  From: Pan Li <pan2.li@intel.com>

This patch would like to refactor the testcases of bswap16-0
after sorts of optimization option passing to testcase.  To
fits the big lmul like m8 for asm dump check.

The below test suites are passed for this patch.
* The rv64gcv fully regression test.

It is test only patch and obvious up to a point, will commit it
directly if no comments in next 48H.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/unop/bswap16-0.c: Update
	the vector register RE to cover v10 - v31.

Signed-off-by: Pan Li <pan2.li@intel.com>
---
 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/bswap16-0.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
diff mbox series

Patch

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/bswap16-0.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/bswap16-0.c
index 605b3565b6b..4b55c001a31 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/bswap16-0.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/bswap16-0.c
@@ -10,7 +10,7 @@ 
 **   ...
 **   vsrl\.vi\s+v[0-9]+,\s*v[0-9],\s*8+
 **   vsll\.vi\s+v[0-9]+,\s*v[0-9],\s*8+
-**   vor\.vv\s+v[0-9]+,\s*v[0-9],\s*v[0-9]+
+**   vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 **   ...
 */
 TEST_UNARY_CALL (uint16_t, __builtin_bswap16)