diff mbox series

[v1] RISC-V: Fix incorrect optimization options passing to reduc and ternop

Message ID 20241203061028.3112848-1-pan2.li@intel.com
State Committed
Commit 5cbeecf07df4f50ee02345419bafffc5f0e3d604
Headers
Series [v1] RISC-V: Fix incorrect optimization options passing to reduc and ternop |

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Commit Message

Li, Pan2 Dec. 3, 2024, 6:10 a.m. UTC 
  From: Pan Li <pan2.li@intel.com>

Like the strided load/store, the testcases of vector reduce and ternop
are designed to pick up different sorts of optimization options but
actually these option are ignored according to the Execution log of
the gcc.log.

This patch would like to make it correct almost the same as what we
fixed for strided load/store.

The below test suites are passed for this patch.
* The rv64gcv fully regression test.

It is test only patch and obvious up to a point, will commit it
directly if no comments in next 48H.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/rvv.exp: Fix the incorrect optimization
	options passing to testcases.

Signed-off-by: Pan Li <pan2.li@intel.com>
---
 gcc/testsuite/gcc.target/riscv/rvv/rvv.exp | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

Comments

Kito Cheng Dec. 3, 2024, 8:16 a.m. UTC | #1 
lgtm

On Tue, Dec 3, 2024 at 2:13 PM <pan2.li@intel.com> wrote:
>
> From: Pan Li <pan2.li@intel.com>
>
> Like the strided load/store, the testcases of vector reduce and ternop
> are designed to pick up different sorts of optimization options but
> actually these option are ignored according to the Execution log of
> the gcc.log.
>
> This patch would like to make it correct almost the same as what we
> fixed for strided load/store.
>
> The below test suites are passed for this patch.
> * The rv64gcv fully regression test.
>
> It is test only patch and obvious up to a point, will commit it
> directly if no comments in next 48H.
>
> gcc/testsuite/ChangeLog:
>
>         * gcc.target/riscv/rvv/rvv.exp: Fix the incorrect optimization
>         options passing to testcases.
>
> Signed-off-by: Pan Li <pan2.li@intel.com>
> ---
>  gcc/testsuite/gcc.target/riscv/rvv/rvv.exp | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp b/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp
> index 87dea457608..65a57aa7913 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp
> @@ -71,9 +71,9 @@ foreach op $AUTOVEC_TEST_OPTS {
>    dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/autovec/unop/*.\[cS\]]] \
>      "" "$op"
>    dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/autovec/ternop/*.\[cS\]]] \
> -    "" "$op"
> +    "$op" ""
>    dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/autovec/reduc/*.\[cS\]]] \
> -    "" "$op"
> +    "$op" ""
>    dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/autovec/cond/*.\[cS\]]] \
>      "$op" ""
>    dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/autovec/builtin/*.\[cS\]]] \
> --
> 2.43.0
>
diff mbox series

Patch

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp b/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp
index 87dea457608..65a57aa7913 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp
+++ b/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp
@@ -71,9 +71,9 @@  foreach op $AUTOVEC_TEST_OPTS {
   dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/autovec/unop/*.\[cS\]]] \
     "" "$op"
   dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/autovec/ternop/*.\[cS\]]] \
-    "" "$op"
+    "$op" ""
   dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/autovec/reduc/*.\[cS\]]] \
-    "" "$op"
+    "$op" ""
   dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/autovec/cond/*.\[cS\]]] \
     "$op" ""
   dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/autovec/builtin/*.\[cS\]]] \