diff mbox series

[v1] RISC-V: Add assert for insn operand out of range access [PR117878][NFC]

Message ID 20241204083101.1329043-1-pan2.li@intel.com
State Committed
Headers
Series [v1] RISC-V: Add assert for insn operand out of range access [PR117878][NFC] |

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Commit Message

Li, Pan2 Dec. 4, 2024, 8:31 a.m. UTC 
  From: Pan Li <pan2.li@intel.com>

According to the the initial analysis of PR117878, the ice comes from
the out-of-range operand access for recog_data.operand[].  Thus, add
one assert here to expose this explicitly.

	PR target/117878

gcc/ChangeLog:

	* config/riscv/riscv-v.cc (vlmax_avl_type_p): Add assert for
	out of range access.
	(nonvlmax_avl_type_p): Ditto.

Signed-off-by: Pan Li <pan2.li@intel.com>
---
 gcc/config/riscv/riscv-v.cc | 6 ++++++
 1 file changed, 6 insertions(+)

Comments

Kito Cheng Dec. 4, 2024, 8:38 a.m. UTC | #1 
LGTM

On Wed, Dec 4, 2024 at 4:31 PM <pan2.li@intel.com> wrote:
>
> From: Pan Li <pan2.li@intel.com>
>
> According to the the initial analysis of PR117878, the ice comes from
> the out-of-range operand access for recog_data.operand[].  Thus, add
> one assert here to expose this explicitly.
>
>         PR target/117878
>
> gcc/ChangeLog:
>
>         * config/riscv/riscv-v.cc (vlmax_avl_type_p): Add assert for
>         out of range access.
>         (nonvlmax_avl_type_p): Ditto.
>
> Signed-off-by: Pan Li <pan2.li@intel.com>
> ---
>  gcc/config/riscv/riscv-v.cc | 6 ++++++
>  1 file changed, 6 insertions(+)
>
> diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
> index ee7a0128c0e..47bc0255aa3 100644
> --- a/gcc/config/riscv/riscv-v.cc
> +++ b/gcc/config/riscv/riscv-v.cc
> @@ -5174,6 +5174,9 @@ vlmax_avl_type_p (rtx_insn *rinsn)
>    int index = get_attr_avl_type_idx (rinsn);
>    if (index == INVALID_ATTRIBUTE)
>      return false;
> +
> +  gcc_assert (index < recog_data.n_operands);
> +
>    rtx avl_type = recog_data.operand[index];
>    return INTVAL (avl_type) == VLMAX;
>  }
> @@ -5222,6 +5225,9 @@ nonvlmax_avl_type_p (rtx_insn *rinsn)
>    int index = get_attr_avl_type_idx (rinsn);
>    if (index == INVALID_ATTRIBUTE)
>      return false;
> +
> +  gcc_assert (index < recog_data.n_operands);
> +
>    rtx avl_type = recog_data.operand[index];
>    return INTVAL (avl_type) == NONVLMAX;
>  }
> --
> 2.43.0
>
diff mbox series

Patch

diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index ee7a0128c0e..47bc0255aa3 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -5174,6 +5174,9 @@  vlmax_avl_type_p (rtx_insn *rinsn)
   int index = get_attr_avl_type_idx (rinsn);
   if (index == INVALID_ATTRIBUTE)
     return false;
+
+  gcc_assert (index < recog_data.n_operands);
+
   rtx avl_type = recog_data.operand[index];
   return INTVAL (avl_type) == VLMAX;
 }
@@ -5222,6 +5225,9 @@  nonvlmax_avl_type_p (rtx_insn *rinsn)
   int index = get_attr_avl_type_idx (rinsn);
   if (index == INVALID_ATTRIBUTE)
     return false;
+
+  gcc_assert (index < recog_data.n_operands);
+
   rtx avl_type = recog_data.operand[index];
   return INTVAL (avl_type) == NONVLMAX;
 }