diff mbox series

[04/20] arm: [MVE intrinsics] factorize vrev16q vrev32q vrev64q

Message ID 20230510133036.596530-4-christophe.lyon@arm.com
State Committed
Commit 0c1eb90103c192a79ff2a5f4fce2583b4d2eceb2
Headers
Series [01/20] arm: [MVE intrinsics] factorize vcmp |

Commit Message

Christophe Lyon May 10, 2023, 1:30 p.m. UTC 
  Factorize vrev16q vrev32q vrev64q so that they use generic builtin
names.

2022-10-25  Christophe Lyon  <christophe.lyon@arm.com>

	gcc/
	* config/arm/iterators.md (MVE_V8HF, MVE_V16QI)
	(MVE_FP_VREV64Q_ONLY, MVE_FP_M_VREV64Q_ONLY, MVE_FP_VREV32Q_ONLY)
	(MVE_FP_M_VREV32Q_ONLY): New iterators.
	(mve_insn): Add vrev16q, vrev32q, vrev64q.
	* config/arm/mve.md (mve_vrev64q_f<mode>): Rename into ...
	(@mve_<mve_insn>q_f<mode>): ... this
	(mve_vrev32q_fv8hf): Rename into @mve_<mve_insn>q_f<mode>.
	(mve_vrev64q_<supf><mode>): Rename into ...
	(@mve_<mve_insn>q_<supf><mode>): ... this.
	(mve_vrev32q_<supf><mode>): Rename into
	@mve_<mve_insn>q_<supf><mode>.
	(mve_vrev16q_<supf>v16qi): Rename into
	@mve_<mve_insn>q_<supf><mode>.
	(mve_vrev64q_m_<supf><mode>): Rename into
	@mve_<mve_insn>q_m_<supf><mode>.
	(mve_vrev32q_m_fv8hf): Rename into @mve_<mve_insn>q_m_f<mode>.
	(mve_vrev32q_m_<supf><mode>): Rename into
	@mve_<mve_insn>q_m_<supf><mode>.
	(mve_vrev64q_m_f<mode>): Rename into @mve_<mve_insn>q_m_f<mode>.
	(mve_vrev16q_m_<supf>v16qi): Rename into
	@mve_<mve_insn>q_m_<supf><mode>.
---
 gcc/config/arm/iterators.md | 25 +++++++++++++
 gcc/config/arm/mve.md       | 72 ++++++++++++++++++-------------------
 2 files changed, 61 insertions(+), 36 deletions(-)
diff mbox series

Patch

diff --git a/gcc/config/arm/iterators.md b/gcc/config/arm/iterators.md
index ef9fae0412b..878210471c8 100644
--- a/gcc/config/arm/iterators.md
+++ b/gcc/config/arm/iterators.md
@@ -1,3 +1,4 @@ 
+
 ;; Code and mode itertator and attribute definitions for the ARM backend
 ;; Copyright (C) 2010-2023 Free Software Foundation, Inc.
 ;; Contributed by ARM Ltd.
@@ -274,6 +275,8 @@  (define_mode_iterator MVE_5 [V8HI V4SI])
 (define_mode_iterator MVE_6 [V8HI V4SI])
 (define_mode_iterator MVE_7 [V16BI V8BI V4BI V2QI])
 (define_mode_iterator MVE_7_HI [HI V16BI V8BI V4BI V2QI])
+(define_mode_iterator MVE_V8HF [V8HF])
+(define_mode_iterator MVE_V16QI [V16QI])
 
 ;;----------------------------------------------------------------------------
 ;; Code iterators
@@ -372,6 +375,22 @@  (define_int_iterator MVE_FP_M_UNARY [
 		     VRNDXQ_M_F
 		     ])
 
+(define_int_iterator MVE_FP_VREV64Q_ONLY [
+		     VREV64Q_F
+		     ])
+
+(define_int_iterator MVE_FP_M_VREV64Q_ONLY [
+		     VREV64Q_M_F
+		     ])
+
+(define_int_iterator MVE_FP_VREV32Q_ONLY [
+		     VREV32Q_F
+		     ])
+
+(define_int_iterator MVE_FP_M_VREV32Q_ONLY [
+		     VREV32Q_M_F
+		     ])
+
 ;; MVE integer binary operations.
 (define_code_iterator MVE_INT_BINARY_RTX [plus minus mult])
 
@@ -862,6 +881,12 @@  (define_int_attr mve_insn [
 		 (VQSUBQ_M_S "vqsub") (VQSUBQ_M_U "vqsub")
 		 (VQSUBQ_N_S "vqsub") (VQSUBQ_N_U "vqsub")
 		 (VQSUBQ_S "vqsub") (VQSUBQ_U "vqsub")
+		 (VREV16Q_M_S "vrev16") (VREV16Q_M_U "vrev16")
+		 (VREV16Q_S "vrev16") (VREV16Q_U "vrev16")
+		 (VREV32Q_M_S "vrev32") (VREV32Q_M_U "vrev32") (VREV32Q_M_F "vrev32")
+		 (VREV32Q_S "vrev32") (VREV32Q_U "vrev32") (VREV32Q_F "vrev32")
+		 (VREV64Q_M_S "vrev64") (VREV64Q_M_U "vrev64") (VREV64Q_M_F "vrev64")
+		 (VREV64Q_S "vrev64") (VREV64Q_U "vrev64") (VREV64Q_F "vrev64")
 		 (VRHADDQ_M_S "vrhadd") (VRHADDQ_M_U "vrhadd")
 		 (VRHADDQ_S "vrhadd") (VRHADDQ_U "vrhadd")
 		 (VRMULHQ_M_S "vrmulh") (VRMULHQ_M_U "vrmulh")
diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md
index 191d1268ad6..4dfcd6c4280 100644
--- a/gcc/config/arm/mve.md
+++ b/gcc/config/arm/mve.md
@@ -151,14 +151,14 @@  (define_insn "@mve_<mve_insn>q_f<mode>"
 ;;
 ;; [vrev64q_f])
 ;;
-(define_insn "mve_vrev64q_f<mode>"
+(define_insn "@mve_<mve_insn>q_f<mode>"
   [
    (set (match_operand:MVE_0 0 "s_register_operand" "=&w")
 	(unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")]
-	 VREV64Q_F))
+	 MVE_FP_VREV64Q_ONLY))
   ]
   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
-  "vrev64.%#<V_sz_elem> %q0, %q1"
+  "<mve_insn>.%#<V_sz_elem>\t%q0, %q1"
   [(set_attr "type" "mve_move")
 ])
 
@@ -193,14 +193,14 @@  (define_insn "mve_vdupq_n_f<mode>"
 ;;
 ;; [vrev32q_f])
 ;;
-(define_insn "mve_vrev32q_fv8hf"
+(define_insn "@mve_<mve_insn>q_f<mode>"
   [
-   (set (match_operand:V8HF 0 "s_register_operand" "=w")
-	(unspec:V8HF [(match_operand:V8HF 1 "s_register_operand" "w")]
-	 VREV32Q_F))
+   (set (match_operand:MVE_V8HF 0 "s_register_operand" "=w")
+	(unspec:MVE_V8HF [(match_operand:MVE_V8HF 1 "s_register_operand" "w")]
+	 MVE_FP_VREV32Q_ONLY))
   ]
   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
-  "vrev32.16 %q0, %q1"
+  "<mve_insn>.<V_sz_elem>\t%q0, %q1"
   [(set_attr "type" "mve_move")
 ])
 ;;
@@ -248,14 +248,14 @@  (define_insn "mve_vcvtq_to_f_<supf><mode>"
 ;;
 ;; [vrev64q_u, vrev64q_s])
 ;;
-(define_insn "mve_vrev64q_<supf><mode>"
+(define_insn "@mve_<mve_insn>q_<supf><mode>"
   [
    (set (match_operand:MVE_2 0 "s_register_operand" "=&w")
 	(unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")]
 	 VREV64Q))
   ]
   "TARGET_HAVE_MVE"
-  "vrev64.%#<V_sz_elem> %q0, %q1"
+  "<mve_insn>.%#<V_sz_elem>\t%q0, %q1"
   [(set_attr "type" "mve_move")
 ])
 
@@ -374,14 +374,14 @@  (define_insn "@mve_vaddvq_<supf><mode>"
 ;;
 ;; [vrev32q_u, vrev32q_s])
 ;;
-(define_insn "mve_vrev32q_<supf><mode>"
+(define_insn "@mve_<mve_insn>q_<supf><mode>"
   [
    (set (match_operand:MVE_3 0 "s_register_operand" "=w")
 	(unspec:MVE_3 [(match_operand:MVE_3 1 "s_register_operand" "w")]
 	 VREV32Q))
   ]
   "TARGET_HAVE_MVE"
-  "vrev32.%#<V_sz_elem>\t%q0, %q1"
+  "<mve_insn>.%#<V_sz_elem>\t%q0, %q1"
   [(set_attr "type" "mve_move")
 ])
 
@@ -486,14 +486,14 @@  (define_insn "mve_vmvnq_n_<supf><mode>"
 ;;
 ;; [vrev16q_u, vrev16q_s])
 ;;
-(define_insn "mve_vrev16q_<supf>v16qi"
+(define_insn "@mve_<mve_insn>q_<supf><mode>"
   [
-   (set (match_operand:V16QI 0 "s_register_operand" "=w")
-	(unspec:V16QI [(match_operand:V16QI 1 "s_register_operand" "w")]
+   (set (match_operand:MVE_V16QI 0 "s_register_operand" "=w")
+	(unspec:MVE_V16QI [(match_operand:MVE_V16QI 1 "s_register_operand" "w")]
 	 VREV16Q))
   ]
   "TARGET_HAVE_MVE"
-  "vrev16.8 %q0, %q1"
+  "<mve_insn>.<V_sz_elem>\t%q0, %q1"
   [(set_attr "type" "mve_move")
 ])
 
@@ -2364,7 +2364,7 @@  (define_insn "@mve_<mve_insn>q_m_r_<supf><mode>"
 ;;
 ;; [vrev64q_m_u, vrev64q_m_s])
 ;;
-(define_insn "mve_vrev64q_m_<supf><mode>"
+(define_insn "@mve_<mve_insn>q_m_<supf><mode>"
   [
    (set (match_operand:MVE_2 0 "s_register_operand" "=&w")
 	(unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
@@ -2373,7 +2373,7 @@  (define_insn "mve_vrev64q_m_<supf><mode>"
 	 VREV64Q_M))
   ]
   "TARGET_HAVE_MVE"
-  "vpst\;vrev64t.%#<V_sz_elem>\t%q0, %q2"
+  "vpst\;<mve_insn>t.%#<V_sz_elem>\t%q0, %q2"
   [(set_attr "type" "mve_move")
    (set_attr "length""8")])
 
@@ -3008,23 +3008,23 @@  (define_insn "@mve_vpselq_f<mode>"
 ;;
 ;; [vrev32q_m_f])
 ;;
-(define_insn "mve_vrev32q_m_fv8hf"
+(define_insn "@mve_<mve_insn>q_m_f<mode>"
   [
-   (set (match_operand:V8HF 0 "s_register_operand" "=w")
-	(unspec:V8HF [(match_operand:V8HF 1 "s_register_operand" "0")
-		       (match_operand:V8HF 2 "s_register_operand" "w")
-		       (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")]
-	 VREV32Q_M_F))
+   (set (match_operand:MVE_V8HF 0 "s_register_operand" "=w")
+	(unspec:MVE_V8HF [(match_operand:MVE_V8HF 1 "s_register_operand" "0")
+			  (match_operand:MVE_V8HF 2 "s_register_operand" "w")
+			  (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")]
+	 MVE_FP_M_VREV32Q_ONLY))
   ]
   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
-  "vpst\;vrev32t.16 %q0, %q2"
+  "vpst\;<mve_insn>t.<V_sz_elem>\t%q0, %q2"
   [(set_attr "type" "mve_move")
    (set_attr "length""8")])
 
 ;;
 ;; [vrev32q_m_s, vrev32q_m_u])
 ;;
-(define_insn "mve_vrev32q_m_<supf><mode>"
+(define_insn "@mve_<mve_insn>q_m_<supf><mode>"
   [
    (set (match_operand:MVE_3 0 "s_register_operand" "=w")
 	(unspec:MVE_3 [(match_operand:MVE_3 1 "s_register_operand" "0")
@@ -3033,23 +3033,23 @@  (define_insn "mve_vrev32q_m_<supf><mode>"
 	 VREV32Q_M))
   ]
   "TARGET_HAVE_MVE"
-  "vpst\;vrev32t.%#<V_sz_elem>	%q0, %q2"
+  "vpst\;<mve_insn>t.%#<V_sz_elem>\t%q0, %q2"
   [(set_attr "type" "mve_move")
    (set_attr "length""8")])
 
 ;;
 ;; [vrev64q_m_f])
 ;;
-(define_insn "mve_vrev64q_m_f<mode>"
+(define_insn "@mve_<mve_insn>q_m_f<mode>"
   [
    (set (match_operand:MVE_0 0 "s_register_operand" "=&w")
 	(unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
 		       (match_operand:MVE_0 2 "s_register_operand" "w")
 		       (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")]
-	 VREV64Q_M_F))
+	 MVE_FP_M_VREV64Q_ONLY))
   ]
   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
-  "vpst\;vrev64t.%#<V_sz_elem>	%q0, %q2"
+  "vpst\;<mve_insn>t.%#<V_sz_elem>\t%q0, %q2"
   [(set_attr "type" "mve_move")
    (set_attr "length""8")])
 
@@ -3201,16 +3201,16 @@  (define_insn "mve_vcvtq_m_n_from_f_<supf><mode>"
 ;;
 ;; [vrev16q_m_u, vrev16q_m_s])
 ;;
-(define_insn "mve_vrev16q_m_<supf>v16qi"
+(define_insn "@mve_<mve_insn>q_m_<supf><mode>"
   [
-   (set (match_operand:V16QI 0 "s_register_operand" "=w")
-	(unspec:V16QI [(match_operand:V16QI 1 "s_register_operand" "0")
-		       (match_operand:V16QI 2 "s_register_operand" "w")
-		       (match_operand:V16BI 3 "vpr_register_operand" "Up")]
+   (set (match_operand:MVE_V16QI 0 "s_register_operand" "=w")
+	(unspec:MVE_V16QI [(match_operand:MVE_V16QI 1 "s_register_operand" "0")
+			   (match_operand:MVE_V16QI 2 "s_register_operand" "w")
+			   (match_operand:V16BI 3 "vpr_register_operand" "Up")]
 	 VREV16Q_M))
   ]
   "TARGET_HAVE_MVE"
-  "vpst\;vrev16t.8 %q0, %q2"
+  "vpst\;<mve_insn>t.<V_sz_elem>\t%q0, %q2"
   [(set_attr "type" "mve_move")
    (set_attr "length""8")])