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Ip=[63.35.35.123]; Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: DBAEUR03FT015.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DBBPR08MB5882 X-Spam-Status: No, score=-12.6 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, FORGED_SPF_HELO, GIT_PATCH_0, KAM_DMARC_NONE, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE, UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Christophe Lyon via Gcc-patches From: Christophe Lyon Reply-To: Christophe Lyon Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" Factorize vrev16q vrev32q vrev64q so that they use generic builtin names. 2022-10-25 Christophe Lyon gcc/ * config/arm/iterators.md (MVE_V8HF, MVE_V16QI) (MVE_FP_VREV64Q_ONLY, MVE_FP_M_VREV64Q_ONLY, MVE_FP_VREV32Q_ONLY) (MVE_FP_M_VREV32Q_ONLY): New iterators. (mve_insn): Add vrev16q, vrev32q, vrev64q. * config/arm/mve.md (mve_vrev64q_f): Rename into ... (@mve_q_f): ... this (mve_vrev32q_fv8hf): Rename into @mve_q_f. (mve_vrev64q_): Rename into ... (@mve_q_): ... this. (mve_vrev32q_): Rename into @mve_q_. (mve_vrev16q_v16qi): Rename into @mve_q_. (mve_vrev64q_m_): Rename into @mve_q_m_. (mve_vrev32q_m_fv8hf): Rename into @mve_q_m_f. (mve_vrev32q_m_): Rename into @mve_q_m_. (mve_vrev64q_m_f): Rename into @mve_q_m_f. (mve_vrev16q_m_v16qi): Rename into @mve_q_m_. --- gcc/config/arm/iterators.md | 25 +++++++++++++ gcc/config/arm/mve.md | 72 ++++++++++++++++++------------------- 2 files changed, 61 insertions(+), 36 deletions(-) diff --git a/gcc/config/arm/iterators.md b/gcc/config/arm/iterators.md index ef9fae0412b..878210471c8 100644 --- a/gcc/config/arm/iterators.md +++ b/gcc/config/arm/iterators.md @@ -1,3 +1,4 @@ + ;; Code and mode itertator and attribute definitions for the ARM backend ;; Copyright (C) 2010-2023 Free Software Foundation, Inc. ;; Contributed by ARM Ltd. @@ -274,6 +275,8 @@ (define_mode_iterator MVE_5 [V8HI V4SI]) (define_mode_iterator MVE_6 [V8HI V4SI]) (define_mode_iterator MVE_7 [V16BI V8BI V4BI V2QI]) (define_mode_iterator MVE_7_HI [HI V16BI V8BI V4BI V2QI]) +(define_mode_iterator MVE_V8HF [V8HF]) +(define_mode_iterator MVE_V16QI [V16QI]) ;;---------------------------------------------------------------------------- ;; Code iterators @@ -372,6 +375,22 @@ (define_int_iterator MVE_FP_M_UNARY [ VRNDXQ_M_F ]) +(define_int_iterator MVE_FP_VREV64Q_ONLY [ + VREV64Q_F + ]) + +(define_int_iterator MVE_FP_M_VREV64Q_ONLY [ + VREV64Q_M_F + ]) + +(define_int_iterator MVE_FP_VREV32Q_ONLY [ + VREV32Q_F + ]) + +(define_int_iterator MVE_FP_M_VREV32Q_ONLY [ + VREV32Q_M_F + ]) + ;; MVE integer binary operations. (define_code_iterator MVE_INT_BINARY_RTX [plus minus mult]) @@ -862,6 +881,12 @@ (define_int_attr mve_insn [ (VQSUBQ_M_S "vqsub") (VQSUBQ_M_U "vqsub") (VQSUBQ_N_S "vqsub") (VQSUBQ_N_U "vqsub") (VQSUBQ_S "vqsub") (VQSUBQ_U "vqsub") + (VREV16Q_M_S "vrev16") (VREV16Q_M_U "vrev16") + (VREV16Q_S "vrev16") (VREV16Q_U "vrev16") + (VREV32Q_M_S "vrev32") (VREV32Q_M_U "vrev32") (VREV32Q_M_F "vrev32") + (VREV32Q_S "vrev32") (VREV32Q_U "vrev32") (VREV32Q_F "vrev32") + (VREV64Q_M_S "vrev64") (VREV64Q_M_U "vrev64") (VREV64Q_M_F "vrev64") + (VREV64Q_S "vrev64") (VREV64Q_U "vrev64") (VREV64Q_F "vrev64") (VRHADDQ_M_S "vrhadd") (VRHADDQ_M_U "vrhadd") (VRHADDQ_S "vrhadd") (VRHADDQ_U "vrhadd") (VRMULHQ_M_S "vrmulh") (VRMULHQ_M_U "vrmulh") diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md index 191d1268ad6..4dfcd6c4280 100644 --- a/gcc/config/arm/mve.md +++ b/gcc/config/arm/mve.md @@ -151,14 +151,14 @@ (define_insn "@mve_q_f" ;; ;; [vrev64q_f]) ;; -(define_insn "mve_vrev64q_f" +(define_insn "@mve_q_f" [ (set (match_operand:MVE_0 0 "s_register_operand" "=&w") (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")] - VREV64Q_F)) + MVE_FP_VREV64Q_ONLY)) ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" - "vrev64.%# %q0, %q1" + ".%#\t%q0, %q1" [(set_attr "type" "mve_move") ]) @@ -193,14 +193,14 @@ (define_insn "mve_vdupq_n_f" ;; ;; [vrev32q_f]) ;; -(define_insn "mve_vrev32q_fv8hf" +(define_insn "@mve_q_f" [ - (set (match_operand:V8HF 0 "s_register_operand" "=w") - (unspec:V8HF [(match_operand:V8HF 1 "s_register_operand" "w")] - VREV32Q_F)) + (set (match_operand:MVE_V8HF 0 "s_register_operand" "=w") + (unspec:MVE_V8HF [(match_operand:MVE_V8HF 1 "s_register_operand" "w")] + MVE_FP_VREV32Q_ONLY)) ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" - "vrev32.16 %q0, %q1" + ".\t%q0, %q1" [(set_attr "type" "mve_move") ]) ;; @@ -248,14 +248,14 @@ (define_insn "mve_vcvtq_to_f_" ;; ;; [vrev64q_u, vrev64q_s]) ;; -(define_insn "mve_vrev64q_" +(define_insn "@mve_q_" [ (set (match_operand:MVE_2 0 "s_register_operand" "=&w") (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")] VREV64Q)) ] "TARGET_HAVE_MVE" - "vrev64.%# %q0, %q1" + ".%#\t%q0, %q1" [(set_attr "type" "mve_move") ]) @@ -374,14 +374,14 @@ (define_insn "@mve_vaddvq_" ;; ;; [vrev32q_u, vrev32q_s]) ;; -(define_insn "mve_vrev32q_" +(define_insn "@mve_q_" [ (set (match_operand:MVE_3 0 "s_register_operand" "=w") (unspec:MVE_3 [(match_operand:MVE_3 1 "s_register_operand" "w")] VREV32Q)) ] "TARGET_HAVE_MVE" - "vrev32.%#\t%q0, %q1" + ".%#\t%q0, %q1" [(set_attr "type" "mve_move") ]) @@ -486,14 +486,14 @@ (define_insn "mve_vmvnq_n_" ;; ;; [vrev16q_u, vrev16q_s]) ;; -(define_insn "mve_vrev16q_v16qi" +(define_insn "@mve_q_" [ - (set (match_operand:V16QI 0 "s_register_operand" "=w") - (unspec:V16QI [(match_operand:V16QI 1 "s_register_operand" "w")] + (set (match_operand:MVE_V16QI 0 "s_register_operand" "=w") + (unspec:MVE_V16QI [(match_operand:MVE_V16QI 1 "s_register_operand" "w")] VREV16Q)) ] "TARGET_HAVE_MVE" - "vrev16.8 %q0, %q1" + ".\t%q0, %q1" [(set_attr "type" "mve_move") ]) @@ -2364,7 +2364,7 @@ (define_insn "@mve_q_m_r_" ;; ;; [vrev64q_m_u, vrev64q_m_s]) ;; -(define_insn "mve_vrev64q_m_" +(define_insn "@mve_q_m_" [ (set (match_operand:MVE_2 0 "s_register_operand" "=&w") (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") @@ -2373,7 +2373,7 @@ (define_insn "mve_vrev64q_m_" VREV64Q_M)) ] "TARGET_HAVE_MVE" - "vpst\;vrev64t.%#\t%q0, %q2" + "vpst\;t.%#\t%q0, %q2" [(set_attr "type" "mve_move") (set_attr "length""8")]) @@ -3008,23 +3008,23 @@ (define_insn "@mve_vpselq_f" ;; ;; [vrev32q_m_f]) ;; -(define_insn "mve_vrev32q_m_fv8hf" +(define_insn "@mve_q_m_f" [ - (set (match_operand:V8HF 0 "s_register_operand" "=w") - (unspec:V8HF [(match_operand:V8HF 1 "s_register_operand" "0") - (match_operand:V8HF 2 "s_register_operand" "w") - (match_operand: 3 "vpr_register_operand" "Up")] - VREV32Q_M_F)) + (set (match_operand:MVE_V8HF 0 "s_register_operand" "=w") + (unspec:MVE_V8HF [(match_operand:MVE_V8HF 1 "s_register_operand" "0") + (match_operand:MVE_V8HF 2 "s_register_operand" "w") + (match_operand: 3 "vpr_register_operand" "Up")] + MVE_FP_M_VREV32Q_ONLY)) ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" - "vpst\;vrev32t.16 %q0, %q2" + "vpst\;t.\t%q0, %q2" [(set_attr "type" "mve_move") (set_attr "length""8")]) ;; ;; [vrev32q_m_s, vrev32q_m_u]) ;; -(define_insn "mve_vrev32q_m_" +(define_insn "@mve_q_m_" [ (set (match_operand:MVE_3 0 "s_register_operand" "=w") (unspec:MVE_3 [(match_operand:MVE_3 1 "s_register_operand" "0") @@ -3033,23 +3033,23 @@ (define_insn "mve_vrev32q_m_" VREV32Q_M)) ] "TARGET_HAVE_MVE" - "vpst\;vrev32t.%# %q0, %q2" + "vpst\;t.%#\t%q0, %q2" [(set_attr "type" "mve_move") (set_attr "length""8")]) ;; ;; [vrev64q_m_f]) ;; -(define_insn "mve_vrev64q_m_f" +(define_insn "@mve_q_m_f" [ (set (match_operand:MVE_0 0 "s_register_operand" "=&w") (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") (match_operand:MVE_0 2 "s_register_operand" "w") (match_operand: 3 "vpr_register_operand" "Up")] - VREV64Q_M_F)) + MVE_FP_M_VREV64Q_ONLY)) ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" - "vpst\;vrev64t.%# %q0, %q2" + "vpst\;t.%#\t%q0, %q2" [(set_attr "type" "mve_move") (set_attr "length""8")]) @@ -3201,16 +3201,16 @@ (define_insn "mve_vcvtq_m_n_from_f_" ;; ;; [vrev16q_m_u, vrev16q_m_s]) ;; -(define_insn "mve_vrev16q_m_v16qi" +(define_insn "@mve_q_m_" [ - (set (match_operand:V16QI 0 "s_register_operand" "=w") - (unspec:V16QI [(match_operand:V16QI 1 "s_register_operand" "0") - (match_operand:V16QI 2 "s_register_operand" "w") - (match_operand:V16BI 3 "vpr_register_operand" "Up")] + (set (match_operand:MVE_V16QI 0 "s_register_operand" "=w") + (unspec:MVE_V16QI [(match_operand:MVE_V16QI 1 "s_register_operand" "0") + (match_operand:MVE_V16QI 2 "s_register_operand" "w") + (match_operand:V16BI 3 "vpr_register_operand" "Up")] VREV16Q_M)) ] "TARGET_HAVE_MVE" - "vpst\;vrev16t.8 %q0, %q2" + "vpst\;t.\t%q0, %q2" [(set_attr "type" "mve_move") (set_attr "length""8")])