diff mbox series

[09/20] arm: [MVE intrinsics] factorize vaddvq

Message ID 20230510133036.596530-9-christophe.lyon@arm.com
State Committed
Commit eb1ded464f339b498d487dd846dfa674884c8e6e
Headers
Series [01/20] arm: [MVE intrinsics] factorize vcmp |

Commit Message

Christophe Lyon May 10, 2023, 1:30 p.m. UTC 
  Factorize vaddvq builtins so that they use parameterized names.

2022-10-25  Christophe Lyon  <christophe.lyon@arm.com>

	gcc/
	* config/arm/iterators.md (mve_insn): Add vaddv.
	* config/arm/mve.md (@mve_vaddvq_<supf><mode>): Rename into ...
	(@mve_<mve_insn>q_<supf><mode>): ... this.
	(mve_vaddvq_p_<supf><mode>): Rename into ...
	(@mve_<mve_insn>q_p_<supf><mode>): ... this.
	* config/arm/vec-common.md: Use gen_mve_q instead of
	gen_mve_vaddvq.
---
 gcc/config/arm/iterators.md  | 2 ++
 gcc/config/arm/mve.md        | 8 ++++----
 gcc/config/arm/vec-common.md | 2 +-
 3 files changed, 7 insertions(+), 5 deletions(-)
diff mbox series

Patch

diff --git a/gcc/config/arm/iterators.md b/gcc/config/arm/iterators.md
index aff4e7fb814..46c7ddeda67 100644
--- a/gcc/config/arm/iterators.md
+++ b/gcc/config/arm/iterators.md
@@ -762,6 +762,8 @@  (define_int_attr mve_insn [
 		 (VADDQ_M_N_S "vadd") (VADDQ_M_N_U "vadd") (VADDQ_M_N_F "vadd")
 		 (VADDQ_M_S "vadd") (VADDQ_M_U "vadd") (VADDQ_M_F "vadd")
 		 (VADDQ_N_S "vadd") (VADDQ_N_U "vadd") (VADDQ_N_F "vadd")
+		 (VADDVQ_P_S "vaddv") (VADDVQ_P_U "vaddv")
+		 (VADDVQ_S "vaddv") (VADDVQ_U "vaddv")
 		 (VANDQ_M_S "vand") (VANDQ_M_U "vand") (VANDQ_M_F "vand")
 		 (VBICQ_M_N_S "vbic") (VBICQ_M_N_U "vbic")
 		 (VBICQ_M_S "vbic") (VBICQ_M_U "vbic") (VBICQ_M_F "vbic")
diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md
index 0c4e4e60bc4..d772f4d4380 100644
--- a/gcc/config/arm/mve.md
+++ b/gcc/config/arm/mve.md
@@ -360,14 +360,14 @@  (define_insn "@mve_<mve_insn>q_<supf><mode>"
 ;;
 ;; [vaddvq_s, vaddvq_u])
 ;;
-(define_insn "@mve_vaddvq_<supf><mode>"
+(define_insn "@mve_<mve_insn>q_<supf><mode>"
   [
    (set (match_operand:SI 0 "s_register_operand" "=Te")
 	(unspec:SI [(match_operand:MVE_2 1 "s_register_operand" "w")]
 	 VADDVQ))
   ]
   "TARGET_HAVE_MVE"
-  "vaddv.<supf>%#<V_sz_elem>\t%0, %q1"
+  "<mve_insn>.<supf>%#<V_sz_elem>\t%0, %q1"
   [(set_attr "type" "mve_move")
 ])
 
@@ -773,7 +773,7 @@  (define_insn "mve_vaddvaq_<supf><mode>"
 ;;
 ;; [vaddvq_p_u, vaddvq_p_s])
 ;;
-(define_insn "mve_vaddvq_p_<supf><mode>"
+(define_insn "@mve_<mve_insn>q_p_<supf><mode>"
   [
    (set (match_operand:SI 0 "s_register_operand" "=Te")
 	(unspec:SI [(match_operand:MVE_2 1 "s_register_operand" "w")
@@ -781,7 +781,7 @@  (define_insn "mve_vaddvq_p_<supf><mode>"
 	 VADDVQ_P))
   ]
   "TARGET_HAVE_MVE"
-  "vpst\;vaddvt.<supf>%#<V_sz_elem>	%0, %q1"
+  "vpst\;<mve_insn>t.<supf>%#<V_sz_elem>\t%0, %q1"
   [(set_attr "type" "mve_move")
    (set_attr "length""8")])
 
diff --git a/gcc/config/arm/vec-common.md b/gcc/config/arm/vec-common.md
index 6183c931e36..9af8429968d 100644
--- a/gcc/config/arm/vec-common.md
+++ b/gcc/config/arm/vec-common.md
@@ -559,7 +559,7 @@  (define_expand "reduc_plus_scal_<mode>"
       /* vaddv generates a 32 bits accumulator.  */
       rtx op0 = gen_reg_rtx (SImode);
 
-      emit_insn (gen_mve_vaddvq (VADDVQ_S, <MODE>mode, op0, operands[1]));
+      emit_insn (gen_mve_q (VADDVQ_S, VADDVQ_S, <MODE>mode, op0, operands[1]));
       emit_move_insn (operands[0], gen_lowpart (<V_elem>mode, op0));
     }