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[v2,3/3] RISC-V: Limit regs use for zfinx extension

Message ID 20211105130059.3332-4-jiawei@iscas.ac.cn
State Deferred, archived
Headers
Series RISC-V: Support zfinx extension |

Commit Message

Jiawei Nov. 5, 2021, 1 p.m. UTC 
  Limit zfinx abi support with 'ilp32','ilp32e','lp64' only.

Use GPR instead FPR when 'zfinx' enable, Only use even registers in RV32 when 'zdinx' enable.

gcc/ChangeLog:

        * config/riscv/constraints.md
	(TARGET_HARD_FLOAT ? FP_REGS : ((TARGET_ZFINX || TARGET_ZDINX) ? GR_REGS : NO_REGS)):
	  Use gpr when zfinx or zdinx enable.
        * config/riscv/riscv.c (riscv_hard_regno_mode_ok): Add TARGET_ZFINX.
        (riscv_option_override): Ditto.
	(riscv_abi): Add ABI limit for zfinx.

Co-Authored-By: sinan <sinan@isrc.iscas.ac.cn>
---
 gcc/config/riscv/constraints.md |  3 ++-
 gcc/config/riscv/riscv.c        | 14 +++++++++++++-
 2 files changed, 15 insertions(+), 2 deletions(-)
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Patch

diff --git a/gcc/config/riscv/constraints.md b/gcc/config/riscv/constraints.md
index c87d5b796a5..a99b8ce277e 100644
--- a/gcc/config/riscv/constraints.md
+++ b/gcc/config/riscv/constraints.md
@@ -20,8 +20,9 @@ 
 ;; <http://www.gnu.org/licenses/>.
 
 ;; Register constraints
+;; Zfinx support need refuse FPR and use GPR
 
-(define_register_constraint "f" "TARGET_HARD_FLOAT ? FP_REGS : NO_REGS"
+(define_register_constraint "f" "TARGET_HARD_FLOAT ? FP_REGS : ((TARGET_ZFINX || TARGET_ZDINX) ? GR_REGS : NO_REGS)"
   "A floating-point register (if available).")
 
 (define_register_constraint "j" "SIBCALL_REGS"
diff --git a/gcc/config/riscv/riscv.c b/gcc/config/riscv/riscv.c
index a545dbf66f7..f4e0e46e1a7 100644
--- a/gcc/config/riscv/riscv.c
+++ b/gcc/config/riscv/riscv.c
@@ -4789,6 +4789,13 @@  riscv_hard_regno_mode_ok (unsigned int regno, machine_mode mode)
 	!= call_used_or_fixed_reg_p (regno + i))
       return false;
 
+  /* Only use even registers in RV32 ZDINX */
+  if (!TARGET_64BIT && TARGET_ZDINX){
+    if (GET_MODE_CLASS (mode) == MODE_FLOAT &&
+	GET_MODE_UNIT_SIZE (mode) == GET_MODE_SIZE (DFmode))
+      return !(regno & 1);
+  }
+
   return true;
 }
 
@@ -4980,7 +4987,7 @@  riscv_option_override (void)
     error ("%<-mdiv%> requires %<-march%> to subsume the %<M%> extension");
 
   /* Likewise floating-point division and square root.  */
-  if (TARGET_HARD_FLOAT && (target_flags_explicit & MASK_FDIV) == 0)
+  if ((TARGET_HARD_FLOAT || TARGET_ZFINX) && (target_flags_explicit & MASK_FDIV) == 0)
     target_flags |= MASK_FDIV;
 
   /* Handle -mtune, use -mcpu if -mtune is not given, and use default -mtune
@@ -5026,6 +5033,11 @@  riscv_option_override (void)
   if (TARGET_RVE && riscv_abi != ABI_ILP32E)
     error ("rv32e requires ilp32e ABI");
 
+  // Zfinx require abi ilp32,ilp32e or lp64.
+  if (TARGET_ZFINX && riscv_abi != ABI_ILP32
+    && riscv_abi != ABI_LP64 && riscv_abi != ABI_ILP32E)
+  error ("z*inx requires ABI ilp32, ilp32e or lp64");
+
   /* We do not yet support ILP32 on RV64.  */
   if (BITS_PER_WORD != POINTER_SIZE)
     error ("ABI requires %<-march=rv%d%>", POINTER_SIZE);