From patchwork Fri Nov 5 13:00:57 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiawei X-Patchwork-Id: 47106 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id BABB0385E448 for ; Fri, 5 Nov 2021 13:03:14 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from cstnet.cn (smtp21.cstnet.cn [159.226.251.21]) by sourceware.org (Postfix) with ESMTP id 414B43858D28 for ; Fri, 5 Nov 2021 13:01:20 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 414B43858D28 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=iscas.ac.cn Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=iscas.ac.cn Received: from localhost.localdomain (unknown [120.25.159.94]) by APP-01 (Coremail) with SMTP id qwCowAB3ECEYK4VhkKOhBg--.16147S3; Fri, 05 Nov 2021 21:01:14 +0800 (CST) From: jiawei To: gcc-patches@gcc.gnu.org Subject: [PATCH v2 1/3] RISC-V: Minimal support of zfinx extension Date: Fri, 5 Nov 2021 21:00:57 +0800 Message-Id: <20211105130059.3332-2-jiawei@iscas.ac.cn> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211105130059.3332-1-jiawei@iscas.ac.cn> References: <20211105130059.3332-1-jiawei@iscas.ac.cn> MIME-Version: 1.0 X-CM-TRANSID: qwCowAB3ECEYK4VhkKOhBg--.16147S3 X-Coremail-Antispam: 1UD129KBjvJXoWxuF4ktFy8AFWDGr1DKry5twb_yoW5uw17pF WrWw45A34Fqan3Wa1xtrW8W3yUJwnYgr1rJw4ku347AanrJrWDAFn09w1Svr4kXFWYvrn2 k3WFk3yYvw4UGa7anT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUBE14x267AKxVWrJVCq3wAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2048vs2IY020E87I2jVAFwI0_Jr4l82xGYIkIc2 x26xkF7I0E14v26r4j6ryUM28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48ve4kI8wA2z4x0 Y4vE2Ix0cI8IcVAFwI0_Gr0_Xr1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI0_Cr0_Gr1UM2 8EF7xvwVC2z280aVAFwI0_Cr1j6rxdM28EF7xvwVC2z280aVCY1x0267AKxVW0oVCq3wAS 0I0E0xvYzxvE52x082IY62kv0487Mc02F40EFcxC0VAKzVAqx4xG6I80ewAv7VC0I7IYx2 IY67AKxVWUGVWUXwAv7VC2z280aVAFwI0_Jr0_Gr1lOx8S6xCaFVCjc4AY6r1j6r4UM4x0 Y48IcxkI7VAKI48JM4x0x7Aq67IIx4CEVc8vx2IErcIFxwACI402YVCY1x02628vn2kIc2 xKxwCF04k20xvY0x0EwIxGrwCFx2IqxVCFs4IE7xkEbVWUJVW8JwC20s026c02F40E14v2 6r1j6r18MI8I3I0E7480Y4vE14v26r106r1rMI8E67AF67kF1VAFwI0_Jw0_GFylIxkGc2 Ij64vIr41lIxAIcVC0I7IYx2IY67AKxVWUJVWUCwCI42IY6xIIjxv20xvEc7CjxVAFwI0_ Gr0_Cr1lIxAIcVCF04k26cxKx2IYs7xG6r1j6r1xMIIF0xvEx4A2jsIE14v26r1j6r4UMI IF0xvEx4A2jsIEc7CjxVAFwI0_Gr0_Gr1UYxBIdaVFxhVjvjDU0xZFpf9x0JUSYLPUUUUU = X-Originating-IP: [120.25.159.94] X-CM-SenderInfo: 5mld4v3l6l2u1dvotugofq/1tbiCQcQAF02arV46gAAs4 X-Spam-Status: No, score=-12.6 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: tariq.kurd@huawei.com, cmuellner@ventanamicro.com, andrew@sifive.com, sinan@isrc.iscas.ac.cn, philipp.tomsich@vrull.eu, jiawei , nelson.chu@sifive.com, kito.cheng@sifive.com, shihua@iscas.ac.cn Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" Minimal support of zfinx extension, include 'zfinx' and 'zdinx' corresponding to 'f' and 'd', the 'zdinx' will imply 'zfinx' same as 'd' imply 'f'. gcc/ChangeLog: * common/config/riscv/riscv-common.c(riscv_implied_info_t): Add zdinx imply zfinx. (riscv_ext_version_table): Add zfinx, zdinx. * config/riscv/arch-canonicalize(IMPLIED_EXT): Add zdinx imply zfinx. * config/riscv/riscv-opts.h (MASK_ZFINX): New. (MASK_ZDINX): Ditto. (TARGET_ZFINX): Ditto. (TARGET_ZDINX): Ditto. * config/riscv/riscv.opt(riscv_zf_subext): New. Co-Authored-By: sinan --- gcc/common/config/riscv/riscv-common.c | 7 +++++++ gcc/config/riscv/arch-canonicalize | 1 + gcc/config/riscv/riscv-opts.h | 6 ++++++ gcc/config/riscv/riscv.opt | 3 +++ 4 files changed, 17 insertions(+) diff --git a/gcc/common/config/riscv/riscv-common.c b/gcc/common/config/riscv/riscv-common.c index 37b6ea80086..6db5a434257 100644 --- a/gcc/common/config/riscv/riscv-common.c +++ b/gcc/common/config/riscv/riscv-common.c @@ -50,6 +50,7 @@ static const riscv_implied_info_t riscv_implied_info[] = {"d", "f"}, {"f", "zicsr"}, {"d", "zicsr"}, + {"zdinx", "zfinx"}, {NULL, NULL} }; @@ -106,6 +107,9 @@ static const struct riscv_ext_version riscv_ext_version_table[] = {"zbc", ISA_SPEC_CLASS_NONE, 1, 0}, {"zbs", ISA_SPEC_CLASS_NONE, 1, 0}, + {"zfinx", ISA_SPEC_CLASS_NONE, 1, 0}, + {"zdinx", ISA_SPEC_CLASS_NONE, 1, 0}, + /* Terminate the list. */ {NULL, ISA_SPEC_CLASS_NONE, 0, 0} }; @@ -916,6 +920,9 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] = {"zbc", &gcc_options::x_riscv_zb_subext, MASK_ZBC}, {"zbs", &gcc_options::x_riscv_zb_subext, MASK_ZBS}, + {"zfinx", &gcc_options::x_riscv_zf_subext, MASK_ZFINX}, + {"zdinx", &gcc_options::x_riscv_zf_subext, MASK_ZDINX}, + {NULL, NULL, 0} }; diff --git a/gcc/config/riscv/arch-canonicalize b/gcc/config/riscv/arch-canonicalize index c7df3c8a313..9197163d1c3 100755 --- a/gcc/config/riscv/arch-canonicalize +++ b/gcc/config/riscv/arch-canonicalize @@ -36,6 +36,7 @@ LONG_EXT_PREFIXES = ['z', 's', 'h', 'x'] # IMPLIED_EXT = { "d" : ["f"], + "zdinx" : ["zfinx"], } def arch_canonicalize(arch): diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h index 2efc4b80f1f..5a790a028cf 100644 --- a/gcc/config/riscv/riscv-opts.h +++ b/gcc/config/riscv/riscv-opts.h @@ -83,4 +83,10 @@ enum stack_protector_guard { #define TARGET_ZBC ((riscv_zb_subext & MASK_ZBC) != 0) #define TARGET_ZBS ((riscv_zb_subext & MASK_ZBS) != 0) +#define MASK_ZFINX (1 << 0) +#define MASK_ZDINX (1 << 1) + +#define TARGET_ZFINX ((riscv_zf_subext & MASK_ZFINX) != 0) +#define TARGET_ZDINX ((riscv_zf_subext & MASK_ZDINX) != 0) + #endif /* ! GCC_RISCV_OPTS_H */ diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt index 15bf89e17c2..54d27747eff 100644 --- a/gcc/config/riscv/riscv.opt +++ b/gcc/config/riscv/riscv.opt @@ -198,6 +198,9 @@ int riscv_zi_subext TargetVariable int riscv_zb_subext +TargetVariable +int riscv_zf_subext + Enum Name(isa_spec_class) Type(enum riscv_isa_spec_class) Supported ISA specs (for use with the -misa-spec= option): From patchwork Fri Nov 5 13:00:58 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiawei X-Patchwork-Id: 47104 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 75EAD3858030 for ; Fri, 5 Nov 2021 13:02:08 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from cstnet.cn (smtp21.cstnet.cn [159.226.251.21]) by sourceware.org (Postfix) with ESMTP id 48D073858C27 for ; Fri, 5 Nov 2021 13:01:20 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 48D073858C27 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=iscas.ac.cn Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=iscas.ac.cn Received: from localhost.localdomain (unknown [120.25.159.94]) by APP-01 (Coremail) with SMTP id qwCowAB3ECEYK4VhkKOhBg--.16147S4; Fri, 05 Nov 2021 21:01:15 +0800 (CST) From: jiawei To: gcc-patches@gcc.gnu.org Subject: [PATCH v2 2/3] RISC-V: Target support for zfinx extension Date: Fri, 5 Nov 2021 21:00:58 +0800 Message-Id: <20211105130059.3332-3-jiawei@iscas.ac.cn> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211105130059.3332-1-jiawei@iscas.ac.cn> References: <20211105130059.3332-1-jiawei@iscas.ac.cn> MIME-Version: 1.0 X-CM-TRANSID: qwCowAB3ECEYK4VhkKOhBg--.16147S4 X-Coremail-Antispam: 1UD129KBjvAXoW3Aw1fAw1xtrWDJFWfZw1UZFb_yoW8Xr45Ko Zayrs7Kr45Xry0g39Iga1fArnrXa9rJryrXFyYqr1Fyan5Ja98Kr92va13Z3s3tFy3Xa9x ZFn7u3WDAFWDZFs7n29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7v73VFW2AGmfu7bjvjm3 AaLaJ3UjIYCTnIWjp_UUUYR7AC8VAFwI0_Wr0E3s1l1xkIjI8I6I8E6xAIw20EY4v20xva j40_Wr0E3s1l1IIY67AEw4v_Jr0_Jr4l82xGYIkIc2x26280x7IE14v26r15M28IrcIa0x kI8VCY1x0267AKxVW5JVCq3wA2ocxC64kIII0Yj41l84x0c7CEw4AK67xGY2AK021l84AC jcxK6xIIjxv20xvE14v26r4j6ryUM28EF7xvwVC0I7IYx2IY6xkF7I0E14v26F4j6r4UJw A2z4x0Y4vEx4A2jsIE14v26F4UJVW0owA2z4x0Y4vEx4A2jsIEc7CjxVAFwI0_GcCE3s1l e2I262IYc4CY6c8Ij28IcVAaY2xG8wAqx4xG64xvF2IEw4CE5I8CrVC2j2WlYx0E2Ix0cI 8IcVAFwI0_JrI_JrylYx0Ex4A2jsIE14v26r1j6r4UMcvjeVCFs4IE7xkEbVWUJVW8JwAC jcxG0xvY0x0EwIxGrwACjI8F5VA0II8E6IAqYI8I648v4I1lFIxGxcIEc7CjxVA2Y2ka0x kIwI1l42xK82IYc2Ij64vIr41l4I8I3I0E4IkC6x0Yz7v_Jr0_Gr1lx2IqxVAqx4xG67AK xVWUJVWUGwC20s026x8GjcxK67AKxVWUGVWUWwC2zVAF1VAY17CE14v26r1q6r43MIIYrx kI7VAKI48JMIIF0xvE2Ix0cI8IcVAFwI0_Jr0_JF4lIxAIcVC0I7IYx2IY6xkF7I0E14v2 6r4j6F4UMIIF0xvE42xK8VAvwI8IcIk0rVWUJVWUCwCI42IY6I8E87Iv67AKxVWUJVW8Jw CI42IY6I8E87Iv6xkF7I0E14v26r4j6r4UJbIYCTnIWIevJa73UjIFyTuYvjfUFrcTDUUU U X-Originating-IP: [120.25.159.94] X-CM-SenderInfo: 5mld4v3l6l2u1dvotugofq/1tbiBgYQAF0TfubWqQAAs5 X-Spam-Status: No, score=-12.1 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: tariq.kurd@huawei.com, cmuellner@ventanamicro.com, andrew@sifive.com, sinan@isrc.iscas.ac.cn, philipp.tomsich@vrull.eu, jiawei , nelson.chu@sifive.com, kito.cheng@sifive.com, shihua@iscas.ac.cn Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" Support 'TARGET_ZFINX' with float instruction pattern and builtin function. gcc/ChangeLog: * config/riscv/riscv-builtins.c (AVAIL): Add TARGET_ZFINX. (riscv_atomic_assign_expand_fenv): Ditto. * config/riscv/riscv-c.c (riscv_cpu_cpp_builtins): Add TARGET_ZFINX. * config/riscv/riscv.md (TARGET_HARD_FLOAT || TARGET_ZFINX): Add TARGET_ZFINX. (TARGET_DOUBLE_FLOAT || TARGET_ZDINX): Add TARGET_ZDINX. Co-Authored-By: sinan --- gcc/config/riscv/riscv-builtins.c | 4 +- gcc/config/riscv/riscv-c.c | 2 +- gcc/config/riscv/riscv.md | 72 +++++++++++++++---------------- 3 files changed, 39 insertions(+), 39 deletions(-) diff --git a/gcc/config/riscv/riscv-builtins.c b/gcc/config/riscv/riscv-builtins.c index 97b1480a15e..d892e6cdb26 100644 --- a/gcc/config/riscv/riscv-builtins.c +++ b/gcc/config/riscv/riscv-builtins.c @@ -85,7 +85,7 @@ struct riscv_builtin_description { unsigned int (*avail) (void); }; -AVAIL (hard_float, TARGET_HARD_FLOAT) +AVAIL (hard_float, TARGET_HARD_FLOAT || TARGET_ZFINX) /* Construct a riscv_builtin_description from the given arguments. @@ -279,7 +279,7 @@ riscv_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED, void riscv_atomic_assign_expand_fenv (tree *hold, tree *clear, tree *update) { - if (!TARGET_HARD_FLOAT) + if (!(TARGET_HARD_FLOAT || TARGET_ZFINX)) return; tree frflags = GET_BUILTIN_DECL (CODE_FOR_riscv_frflags); diff --git a/gcc/config/riscv/riscv-c.c b/gcc/config/riscv/riscv-c.c index efd4a61ea29..d064a7fc2b3 100644 --- a/gcc/config/riscv/riscv-c.c +++ b/gcc/config/riscv/riscv-c.c @@ -58,7 +58,7 @@ riscv_cpu_cpp_builtins (cpp_reader *pfile) if (TARGET_HARD_FLOAT) builtin_define_with_int_value ("__riscv_flen", UNITS_PER_FP_REG * 8); - if (TARGET_HARD_FLOAT && TARGET_FDIV) + if ((TARGET_HARD_FLOAT || TARGET_ZFINX) && TARGET_FDIV) { builtin_define ("__riscv_fdiv"); builtin_define ("__riscv_fsqrt"); diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index 225e5b259c1..27c9c74c679 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -296,8 +296,8 @@ (define_mode_iterator ANYI [QI HI SI (DI "TARGET_64BIT")]) ;; Iterator for hardware-supported floating-point modes. -(define_mode_iterator ANYF [(SF "TARGET_HARD_FLOAT") - (DF "TARGET_DOUBLE_FLOAT")]) +(define_mode_iterator ANYF [(SF "TARGET_HARD_FLOAT || TARGET_ZFINX") + (DF "TARGET_DOUBLE_FLOAT || TARGET_ZDINX")]) ;; Iterator for floating-point modes that can be loaded into X registers. (define_mode_iterator SOFTF [SF (DF "TARGET_64BIT")]) @@ -444,7 +444,7 @@ [(set (match_operand:ANYF 0 "register_operand" "=f") (plus:ANYF (match_operand:ANYF 1 "register_operand" " f") (match_operand:ANYF 2 "register_operand" " f")))] - "TARGET_HARD_FLOAT" + "TARGET_HARD_FLOAT || TARGET_ZFINX" "fadd.\t%0,%1,%2" [(set_attr "type" "fadd") (set_attr "mode" "")]) @@ -575,7 +575,7 @@ [(set (match_operand:ANYF 0 "register_operand" "=f") (minus:ANYF (match_operand:ANYF 1 "register_operand" " f") (match_operand:ANYF 2 "register_operand" " f")))] - "TARGET_HARD_FLOAT" + "TARGET_HARD_FLOAT || TARGET_ZFINX" "fsub.\t%0,%1,%2" [(set_attr "type" "fadd") (set_attr "mode" "")]) @@ -745,7 +745,7 @@ [(set (match_operand:ANYF 0 "register_operand" "=f") (mult:ANYF (match_operand:ANYF 1 "register_operand" " f") (match_operand:ANYF 2 "register_operand" " f")))] - "TARGET_HARD_FLOAT" + "TARGET_HARD_FLOAT || TARGET_ZFINX" "fmul.\t%0,%1,%2" [(set_attr "type" "fmul") (set_attr "mode" "")]) @@ -1052,7 +1052,7 @@ [(set (match_operand:ANYF 0 "register_operand" "=f") (div:ANYF (match_operand:ANYF 1 "register_operand" " f") (match_operand:ANYF 2 "register_operand" " f")))] - "TARGET_HARD_FLOAT && TARGET_FDIV" + "(TARGET_HARD_FLOAT || TARGET_ZFINX) && TARGET_FDIV" "fdiv.\t%0,%1,%2" [(set_attr "type" "fdiv") (set_attr "mode" "")]) @@ -1067,7 +1067,7 @@ (define_insn "sqrt2" [(set (match_operand:ANYF 0 "register_operand" "=f") (sqrt:ANYF (match_operand:ANYF 1 "register_operand" " f")))] - "TARGET_HARD_FLOAT && TARGET_FDIV" + "(TARGET_HARD_FLOAT || TARGET_ZFINX) && TARGET_FDIV" { return "fsqrt.\t%0,%1"; } @@ -1082,7 +1082,7 @@ (fma:ANYF (match_operand:ANYF 1 "register_operand" " f") (match_operand:ANYF 2 "register_operand" " f") (match_operand:ANYF 3 "register_operand" " f")))] - "TARGET_HARD_FLOAT" + "TARGET_HARD_FLOAT || TARGET_ZFINX" "fmadd.\t%0,%1,%2,%3" [(set_attr "type" "fmadd") (set_attr "mode" "")]) @@ -1093,7 +1093,7 @@ (fma:ANYF (match_operand:ANYF 1 "register_operand" " f") (match_operand:ANYF 2 "register_operand" " f") (neg:ANYF (match_operand:ANYF 3 "register_operand" " f"))))] - "TARGET_HARD_FLOAT" + "TARGET_HARD_FLOAT || TARGET_ZFINX" "fmsub.\t%0,%1,%2,%3" [(set_attr "type" "fmadd") (set_attr "mode" "")]) @@ -1105,7 +1105,7 @@ (neg:ANYF (match_operand:ANYF 1 "register_operand" " f")) (match_operand:ANYF 2 "register_operand" " f") (neg:ANYF (match_operand:ANYF 3 "register_operand" " f"))))] - "TARGET_HARD_FLOAT" + "TARGET_HARD_FLOAT || TARGET_ZFINX" "fnmadd.\t%0,%1,%2,%3" [(set_attr "type" "fmadd") (set_attr "mode" "")]) @@ -1117,7 +1117,7 @@ (neg:ANYF (match_operand:ANYF 1 "register_operand" " f")) (match_operand:ANYF 2 "register_operand" " f") (match_operand:ANYF 3 "register_operand" " f")))] - "TARGET_HARD_FLOAT" + "TARGET_HARD_FLOAT || TARGET_ZFINX" "fnmsub.\t%0,%1,%2,%3" [(set_attr "type" "fmadd") (set_attr "mode" "")]) @@ -1130,7 +1130,7 @@ (neg:ANYF (match_operand:ANYF 1 "register_operand" " f")) (match_operand:ANYF 2 "register_operand" " f") (neg:ANYF (match_operand:ANYF 3 "register_operand" " f")))))] - "TARGET_HARD_FLOAT && !HONOR_SIGNED_ZEROS (mode)" + "(TARGET_HARD_FLOAT || TARGET_ZFINX) && !HONOR_SIGNED_ZEROS (mode)" "fmadd.\t%0,%1,%2,%3" [(set_attr "type" "fmadd") (set_attr "mode" "")]) @@ -1143,7 +1143,7 @@ (neg:ANYF (match_operand:ANYF 1 "register_operand" " f")) (match_operand:ANYF 2 "register_operand" " f") (match_operand:ANYF 3 "register_operand" " f"))))] - "TARGET_HARD_FLOAT && !HONOR_SIGNED_ZEROS (mode)" + "(TARGET_HARD_FLOAT || TARGET_ZFINX) && !HONOR_SIGNED_ZEROS (mode)" "fmsub.\t%0,%1,%2,%3" [(set_attr "type" "fmadd") (set_attr "mode" "")]) @@ -1156,7 +1156,7 @@ (match_operand:ANYF 1 "register_operand" " f") (match_operand:ANYF 2 "register_operand" " f") (match_operand:ANYF 3 "register_operand" " f"))))] - "TARGET_HARD_FLOAT && !HONOR_SIGNED_ZEROS (mode)" + "(TARGET_HARD_FLOAT || TARGET_ZFINX) && !HONOR_SIGNED_ZEROS (mode)" "fnmadd.\t%0,%1,%2,%3" [(set_attr "type" "fmadd") (set_attr "mode" "")]) @@ -1169,7 +1169,7 @@ (match_operand:ANYF 1 "register_operand" " f") (match_operand:ANYF 2 "register_operand" " f") (neg:ANYF (match_operand:ANYF 3 "register_operand" " f")))))] - "TARGET_HARD_FLOAT && !HONOR_SIGNED_ZEROS (mode)" + "(TARGET_HARD_FLOAT || TARGET_ZFINX) && !HONOR_SIGNED_ZEROS (mode)" "fnmsub.\t%0,%1,%2,%3" [(set_attr "type" "fmadd") (set_attr "mode" "")]) @@ -1184,7 +1184,7 @@ (define_insn "abs2" [(set (match_operand:ANYF 0 "register_operand" "=f") (abs:ANYF (match_operand:ANYF 1 "register_operand" " f")))] - "TARGET_HARD_FLOAT" + "TARGET_HARD_FLOAT || TARGET_ZFINX" "fabs.\t%0,%1" [(set_attr "type" "fmove") (set_attr "mode" "")]) @@ -1194,7 +1194,7 @@ (unspec:ANYF [(match_operand:ANYF 1 "register_operand" " f") (match_operand:ANYF 2 "register_operand" " f")] UNSPEC_COPYSIGN))] - "TARGET_HARD_FLOAT" + "TARGET_HARD_FLOAT || TARGET_ZFINX" "fsgnj.\t%0,%1,%2" [(set_attr "type" "fmove") (set_attr "mode" "")]) @@ -1202,7 +1202,7 @@ (define_insn "neg2" [(set (match_operand:ANYF 0 "register_operand" "=f") (neg:ANYF (match_operand:ANYF 1 "register_operand" " f")))] - "TARGET_HARD_FLOAT" + "TARGET_HARD_FLOAT || TARGET_ZFINX" "fneg.\t%0,%1" [(set_attr "type" "fmove") (set_attr "mode" "")]) @@ -1218,7 +1218,7 @@ [(set (match_operand:ANYF 0 "register_operand" "=f") (smin:ANYF (match_operand:ANYF 1 "register_operand" " f") (match_operand:ANYF 2 "register_operand" " f")))] - "TARGET_HARD_FLOAT" + "TARGET_HARD_FLOAT || TARGET_ZFINX" "fmin.\t%0,%1,%2" [(set_attr "type" "fmove") (set_attr "mode" "")]) @@ -1227,7 +1227,7 @@ [(set (match_operand:ANYF 0 "register_operand" "=f") (smax:ANYF (match_operand:ANYF 1 "register_operand" " f") (match_operand:ANYF 2 "register_operand" " f")))] - "TARGET_HARD_FLOAT" + "TARGET_HARD_FLOAT || TARGET_ZFINX" "fmax.\t%0,%1,%2" [(set_attr "type" "fmove") (set_attr "mode" "")]) @@ -1288,7 +1288,7 @@ [(set (match_operand:SF 0 "register_operand" "=f") (float_truncate:SF (match_operand:DF 1 "register_operand" " f")))] - "TARGET_DOUBLE_FLOAT" + "TARGET_DOUBLE_FLOAT || TARGET_ZDINX" "fcvt.s.d\t%0,%1" [(set_attr "type" "fcvt") (set_attr "mode" "SF")]) @@ -1414,7 +1414,7 @@ [(set (match_operand:DF 0 "register_operand" "=f") (float_extend:DF (match_operand:SF 1 "register_operand" " f")))] - "TARGET_DOUBLE_FLOAT" + "TARGET_DOUBLE_FLOAT || TARGET_ZDINX" "fcvt.d.s\t%0,%1" [(set_attr "type" "fcvt") (set_attr "mode" "DF")]) @@ -1430,7 +1430,7 @@ [(set (match_operand:GPR 0 "register_operand" "=r") (fix:GPR (match_operand:ANYF 1 "register_operand" " f")))] - "TARGET_HARD_FLOAT" + "TARGET_HARD_FLOAT || TARGET_ZFINX" "fcvt.. %0,%1,rtz" [(set_attr "type" "fcvt") (set_attr "mode" "")]) @@ -1439,7 +1439,7 @@ [(set (match_operand:GPR 0 "register_operand" "=r") (unsigned_fix:GPR (match_operand:ANYF 1 "register_operand" " f")))] - "TARGET_HARD_FLOAT" + "TARGET_HARD_FLOAT || TARGET_ZFINX" "fcvt.u. %0,%1,rtz" [(set_attr "type" "fcvt") (set_attr "mode" "")]) @@ -1448,7 +1448,7 @@ [(set (match_operand:ANYF 0 "register_operand" "= f") (float:ANYF (match_operand:GPR 1 "reg_or_0_operand" " rJ")))] - "TARGET_HARD_FLOAT" + "TARGET_HARD_FLOAT || TARGET_ZFINX" "fcvt..\t%0,%z1" [(set_attr "type" "fcvt") (set_attr "mode" "")]) @@ -1457,7 +1457,7 @@ [(set (match_operand:ANYF 0 "register_operand" "= f") (unsigned_float:ANYF (match_operand:GPR 1 "reg_or_0_operand" " rJ")))] - "TARGET_HARD_FLOAT" + "TARGET_HARD_FLOAT || TARGET_ZFINX" "fcvt..u\t%0,%z1" [(set_attr "type" "fcvt") (set_attr "mode" "")]) @@ -1467,7 +1467,7 @@ (unspec:GPR [(match_operand:ANYF 1 "register_operand" " f")] RINT))] - "TARGET_HARD_FLOAT" + "TARGET_HARD_FLOAT || TARGET_ZFINX" "fcvt.. %0,%1," [(set_attr "type" "fcvt") (set_attr "mode" "")]) @@ -1741,7 +1741,7 @@ (define_insn "*movdf_hardfloat_rv32" [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,m,m, *r,*r,*m") (match_operand:DF 1 "move_operand" " f,G,m,f,G,*r*G,*m,*r"))] - "!TARGET_64BIT && TARGET_DOUBLE_FLOAT + "!TARGET_64BIT && (TARGET_DOUBLE_FLOAT || TARGET_ZDINX) && (register_operand (operands[0], DFmode) || reg_or_0_operand (operands[1], DFmode))" { return riscv_output_move (operands[0], operands[1]); } @@ -2190,7 +2190,7 @@ (match_operand:ANYF 2 "register_operand")]) (label_ref (match_operand 3 "")) (pc)))] - "TARGET_HARD_FLOAT" + "TARGET_HARD_FLOAT || TARGET_ZFINX" { riscv_expand_conditional_branch (operands[3], GET_CODE (operands[0]), operands[1], operands[2]); @@ -2279,7 +2279,7 @@ (match_operator:SI 1 "fp_scc_comparison" [(match_operand:ANYF 2 "register_operand") (match_operand:ANYF 3 "register_operand")]))] - "TARGET_HARD_FLOAT" + "TARGET_HARD_FLOAT || TARGET_ZFINX" { riscv_expand_float_scc (operands[0], GET_CODE (operands[1]), operands[2], operands[3]); @@ -2291,7 +2291,7 @@ (match_operator:X 1 "fp_native_comparison" [(match_operand:ANYF 2 "register_operand" " f") (match_operand:ANYF 3 "register_operand" " f")]))] - "TARGET_HARD_FLOAT" + "TARGET_HARD_FLOAT || TARGET_ZFINX" "f%C1.\t%0,%2,%3" [(set_attr "type" "fcmp") (set_attr "mode" "")]) @@ -2303,7 +2303,7 @@ (match_operand:ANYF 2 "register_operand")] QUIET_COMPARISON)) (clobber (match_scratch:X 3))])] - "TARGET_HARD_FLOAT") + "TARGET_HARD_FLOAT || TARGET_ZFINX") (define_insn "*f_quiet4_default" [(set (match_operand:X 0 "register_operand" "=r") @@ -2312,7 +2312,7 @@ (match_operand:ANYF 2 "register_operand" " f")] QUIET_COMPARISON)) (clobber (match_scratch:X 3 "=&r"))] - "TARGET_HARD_FLOAT && ! HONOR_SNANS (mode)" + "(TARGET_HARD_FLOAT || TARGET_ZFINX) && ! HONOR_SNANS (mode)" "frflags\t%3\n\tf.\t%0,%1,%2\n\tfsflags %3" [(set_attr "type" "fcmp") (set_attr "mode" "") @@ -2325,7 +2325,7 @@ (match_operand:ANYF 2 "register_operand" " f")] QUIET_COMPARISON)) (clobber (match_scratch:X 3 "=&r"))] - "TARGET_HARD_FLOAT && HONOR_SNANS (mode)" + "(TARGET_HARD_FLOAT || TARGET_ZFINX) && HONOR_SNANS (mode)" "frflags\t%3\n\tf.\t%0,%1,%2\n\tfsflags %3\n\tfeq.\tzero,%1,%2" [(set_attr "type" "fcmp") (set_attr "mode" "") @@ -2729,12 +2729,12 @@ (define_insn "riscv_frflags" [(set (match_operand:SI 0 "register_operand" "=r") (unspec_volatile [(const_int 0)] UNSPECV_FRFLAGS))] - "TARGET_HARD_FLOAT" + "TARGET_HARD_FLOAT || TARGET_ZFINX" "frflags\t%0") (define_insn "riscv_fsflags" [(unspec_volatile [(match_operand:SI 0 "csr_operand" "rK")] UNSPECV_FSFLAGS)] - "TARGET_HARD_FLOAT" + "TARGET_HARD_FLOAT || TARGET_ZFINX" "fsflags\t%0") (define_insn "riscv_mret" From patchwork Fri Nov 5 13:00:59 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiawei X-Patchwork-Id: 47105 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 24E43385AC36 for ; Fri, 5 Nov 2021 13:02:45 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from cstnet.cn (smtp21.cstnet.cn [159.226.251.21]) by sourceware.org (Postfix) with ESMTP id C66293858D35 for ; Fri, 5 Nov 2021 13:01:24 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org C66293858D35 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=iscas.ac.cn Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=iscas.ac.cn Received: from localhost.localdomain (unknown [120.25.159.94]) by APP-01 (Coremail) with SMTP id qwCowAB3ECEYK4VhkKOhBg--.16147S5; Fri, 05 Nov 2021 21:01:16 +0800 (CST) From: jiawei To: gcc-patches@gcc.gnu.org Subject: [PATCH v2 3/3] RISC-V: Limit regs use for zfinx extension Date: Fri, 5 Nov 2021 21:00:59 +0800 Message-Id: <20211105130059.3332-4-jiawei@iscas.ac.cn> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211105130059.3332-1-jiawei@iscas.ac.cn> References: <20211105130059.3332-1-jiawei@iscas.ac.cn> MIME-Version: 1.0 X-CM-TRANSID: qwCowAB3ECEYK4VhkKOhBg--.16147S5 X-Coremail-Antispam: 1UD129KBjvJXoWxJw4kZFyfJr1ftw4xCry3Arb_yoW5WFyUpr s5Gw4YyFZ5JF1S9F4ftr18Jw13Zw1fGr15AryxA3yxAanxCrWktanFgw1Y9rZ7WF45Ary7 A3Z3Cay3Cw4UZa7anT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUPj14x267AKxVWrJVCq3wAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2048vs2IY020E87I2jVAFwI0_JrWl82xGYIkIc2 x26xkF7I0E14v26ryj6s0DM28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48ve4kI8wA2z4x0 Y4vE2Ix0cI8IcVAFwI0_Gr0_Xr1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI0_Cr0_Gr1UM2 8EF7xvwVC2z280aVAFwI0_Cr1j6rxdM28EF7xvwVC2z280aVCY1x0267AKxVW0oVCq3wAS 0I0E0xvYzxvE52x082IY62kv0487Mc02F40EFcxC0VAKzVAqx4xG6I80ewAv7VC0I7IYx2 IY67AKxVWUGVWUXwAv7VC2z280aVAFwI0_Jr0_Gr1lOx8S6xCaFVCjc4AY6r1j6r4UM4x0 Y48IcxkI7VAKI48JM4x0x7Aq67IIx4CEVc8vx2IErcIFxwACI402YVCY1x02628vn2kIc2 xKxwCF04k20xvY0x0EwIxGrwCFx2IqxVCFs4IE7xkEbVWUJVW8JwC20s026c02F40E14v2 6r1j6r18MI8I3I0E7480Y4vE14v26r106r1rMI8E67AF67kF1VAFwI0_Jw0_GFylIxkGc2 Ij64vIr41lIxAIcVC0I7IYx2IY67AKxVWUJVWUCwCI42IY6xIIjxv20xvEc7CjxVAFwI0_ Cr0_Gr1UMIIF0xvE42xK8VAvwI8IcIk0rVWUJVWUCwCI42IY6I8E87Iv67AKxVWUJVW8Jw CI42IY6I8E87Iv6xkF7I0E14v26r4j6r4UJbIYCTnIWIevJa73UjIFyTuYvjfUFfHUDUUU U X-Originating-IP: [120.25.159.94] X-CM-SenderInfo: 5mld4v3l6l2u1dvotugofq/1tbiCwkQAFz4kkNxUwAAsF X-Spam-Status: No, score=-12.4 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: tariq.kurd@huawei.com, cmuellner@ventanamicro.com, andrew@sifive.com, sinan@isrc.iscas.ac.cn, philipp.tomsich@vrull.eu, jiawei , nelson.chu@sifive.com, kito.cheng@sifive.com, shihua@iscas.ac.cn Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" Limit zfinx abi support with 'ilp32','ilp32e','lp64' only. Use GPR instead FPR when 'zfinx' enable, Only use even registers in RV32 when 'zdinx' enable. gcc/ChangeLog: * config/riscv/constraints.md (TARGET_HARD_FLOAT ? FP_REGS : ((TARGET_ZFINX || TARGET_ZDINX) ? GR_REGS : NO_REGS)): Use gpr when zfinx or zdinx enable. * config/riscv/riscv.c (riscv_hard_regno_mode_ok): Add TARGET_ZFINX. (riscv_option_override): Ditto. (riscv_abi): Add ABI limit for zfinx. Co-Authored-By: sinan --- gcc/config/riscv/constraints.md | 3 ++- gcc/config/riscv/riscv.c | 14 +++++++++++++- 2 files changed, 15 insertions(+), 2 deletions(-) diff --git a/gcc/config/riscv/constraints.md b/gcc/config/riscv/constraints.md index c87d5b796a5..a99b8ce277e 100644 --- a/gcc/config/riscv/constraints.md +++ b/gcc/config/riscv/constraints.md @@ -20,8 +20,9 @@ ;; . ;; Register constraints +;; Zfinx support need refuse FPR and use GPR -(define_register_constraint "f" "TARGET_HARD_FLOAT ? FP_REGS : NO_REGS" +(define_register_constraint "f" "TARGET_HARD_FLOAT ? FP_REGS : ((TARGET_ZFINX || TARGET_ZDINX) ? GR_REGS : NO_REGS)" "A floating-point register (if available).") (define_register_constraint "j" "SIBCALL_REGS" diff --git a/gcc/config/riscv/riscv.c b/gcc/config/riscv/riscv.c index a545dbf66f7..f4e0e46e1a7 100644 --- a/gcc/config/riscv/riscv.c +++ b/gcc/config/riscv/riscv.c @@ -4789,6 +4789,13 @@ riscv_hard_regno_mode_ok (unsigned int regno, machine_mode mode) != call_used_or_fixed_reg_p (regno + i)) return false; + /* Only use even registers in RV32 ZDINX */ + if (!TARGET_64BIT && TARGET_ZDINX){ + if (GET_MODE_CLASS (mode) == MODE_FLOAT && + GET_MODE_UNIT_SIZE (mode) == GET_MODE_SIZE (DFmode)) + return !(regno & 1); + } + return true; } @@ -4980,7 +4987,7 @@ riscv_option_override (void) error ("%<-mdiv%> requires %<-march%> to subsume the % extension"); /* Likewise floating-point division and square root. */ - if (TARGET_HARD_FLOAT && (target_flags_explicit & MASK_FDIV) == 0) + if ((TARGET_HARD_FLOAT || TARGET_ZFINX) && (target_flags_explicit & MASK_FDIV) == 0) target_flags |= MASK_FDIV; /* Handle -mtune, use -mcpu if -mtune is not given, and use default -mtune @@ -5026,6 +5033,11 @@ riscv_option_override (void) if (TARGET_RVE && riscv_abi != ABI_ILP32E) error ("rv32e requires ilp32e ABI"); + // Zfinx require abi ilp32,ilp32e or lp64. + if (TARGET_ZFINX && riscv_abi != ABI_ILP32 + && riscv_abi != ABI_LP64 && riscv_abi != ABI_ILP32E) + error ("z*inx requires ABI ilp32, ilp32e or lp64"); + /* We do not yet support ILP32 on RV64. */ if (BITS_PER_WORD != POINTER_SIZE) error ("ABI requires %<-march=rv%d%>", POINTER_SIZE);