From patchwork Fri Nov 5 13:00:59 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiawei X-Patchwork-Id: 47105 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 24E43385AC36 for ; Fri, 5 Nov 2021 13:02:45 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from cstnet.cn (smtp21.cstnet.cn [159.226.251.21]) by sourceware.org (Postfix) with ESMTP id C66293858D35 for ; Fri, 5 Nov 2021 13:01:24 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org C66293858D35 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=iscas.ac.cn Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=iscas.ac.cn Received: from localhost.localdomain (unknown [120.25.159.94]) by APP-01 (Coremail) with SMTP id qwCowAB3ECEYK4VhkKOhBg--.16147S5; Fri, 05 Nov 2021 21:01:16 +0800 (CST) From: jiawei To: gcc-patches@gcc.gnu.org Subject: [PATCH v2 3/3] RISC-V: Limit regs use for zfinx extension Date: Fri, 5 Nov 2021 21:00:59 +0800 Message-Id: <20211105130059.3332-4-jiawei@iscas.ac.cn> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211105130059.3332-1-jiawei@iscas.ac.cn> References: <20211105130059.3332-1-jiawei@iscas.ac.cn> MIME-Version: 1.0 X-CM-TRANSID: qwCowAB3ECEYK4VhkKOhBg--.16147S5 X-Coremail-Antispam: 1UD129KBjvJXoWxJw4kZFyfJr1ftw4xCry3Arb_yoW5WFyUpr s5Gw4YyFZ5JF1S9F4ftr18Jw13Zw1fGr15AryxA3yxAanxCrWktanFgw1Y9rZ7WF45Ary7 A3Z3Cay3Cw4UZa7anT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUPj14x267AKxVWrJVCq3wAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2048vs2IY020E87I2jVAFwI0_JrWl82xGYIkIc2 x26xkF7I0E14v26ryj6s0DM28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48ve4kI8wA2z4x0 Y4vE2Ix0cI8IcVAFwI0_Gr0_Xr1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI0_Cr0_Gr1UM2 8EF7xvwVC2z280aVAFwI0_Cr1j6rxdM28EF7xvwVC2z280aVCY1x0267AKxVW0oVCq3wAS 0I0E0xvYzxvE52x082IY62kv0487Mc02F40EFcxC0VAKzVAqx4xG6I80ewAv7VC0I7IYx2 IY67AKxVWUGVWUXwAv7VC2z280aVAFwI0_Jr0_Gr1lOx8S6xCaFVCjc4AY6r1j6r4UM4x0 Y48IcxkI7VAKI48JM4x0x7Aq67IIx4CEVc8vx2IErcIFxwACI402YVCY1x02628vn2kIc2 xKxwCF04k20xvY0x0EwIxGrwCFx2IqxVCFs4IE7xkEbVWUJVW8JwC20s026c02F40E14v2 6r1j6r18MI8I3I0E7480Y4vE14v26r106r1rMI8E67AF67kF1VAFwI0_Jw0_GFylIxkGc2 Ij64vIr41lIxAIcVC0I7IYx2IY67AKxVWUJVWUCwCI42IY6xIIjxv20xvEc7CjxVAFwI0_ Cr0_Gr1UMIIF0xvE42xK8VAvwI8IcIk0rVWUJVWUCwCI42IY6I8E87Iv67AKxVWUJVW8Jw CI42IY6I8E87Iv6xkF7I0E14v26r4j6r4UJbIYCTnIWIevJa73UjIFyTuYvjfUFfHUDUUU U X-Originating-IP: [120.25.159.94] X-CM-SenderInfo: 5mld4v3l6l2u1dvotugofq/1tbiCwkQAFz4kkNxUwAAsF X-Spam-Status: No, score=-12.4 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: tariq.kurd@huawei.com, cmuellner@ventanamicro.com, andrew@sifive.com, sinan@isrc.iscas.ac.cn, philipp.tomsich@vrull.eu, jiawei , nelson.chu@sifive.com, kito.cheng@sifive.com, shihua@iscas.ac.cn Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" Limit zfinx abi support with 'ilp32','ilp32e','lp64' only. Use GPR instead FPR when 'zfinx' enable, Only use even registers in RV32 when 'zdinx' enable. gcc/ChangeLog: * config/riscv/constraints.md (TARGET_HARD_FLOAT ? FP_REGS : ((TARGET_ZFINX || TARGET_ZDINX) ? GR_REGS : NO_REGS)): Use gpr when zfinx or zdinx enable. * config/riscv/riscv.c (riscv_hard_regno_mode_ok): Add TARGET_ZFINX. (riscv_option_override): Ditto. (riscv_abi): Add ABI limit for zfinx. Co-Authored-By: sinan --- gcc/config/riscv/constraints.md | 3 ++- gcc/config/riscv/riscv.c | 14 +++++++++++++- 2 files changed, 15 insertions(+), 2 deletions(-) diff --git a/gcc/config/riscv/constraints.md b/gcc/config/riscv/constraints.md index c87d5b796a5..a99b8ce277e 100644 --- a/gcc/config/riscv/constraints.md +++ b/gcc/config/riscv/constraints.md @@ -20,8 +20,9 @@ ;; . ;; Register constraints +;; Zfinx support need refuse FPR and use GPR -(define_register_constraint "f" "TARGET_HARD_FLOAT ? FP_REGS : NO_REGS" +(define_register_constraint "f" "TARGET_HARD_FLOAT ? FP_REGS : ((TARGET_ZFINX || TARGET_ZDINX) ? GR_REGS : NO_REGS)" "A floating-point register (if available).") (define_register_constraint "j" "SIBCALL_REGS" diff --git a/gcc/config/riscv/riscv.c b/gcc/config/riscv/riscv.c index a545dbf66f7..f4e0e46e1a7 100644 --- a/gcc/config/riscv/riscv.c +++ b/gcc/config/riscv/riscv.c @@ -4789,6 +4789,13 @@ riscv_hard_regno_mode_ok (unsigned int regno, machine_mode mode) != call_used_or_fixed_reg_p (regno + i)) return false; + /* Only use even registers in RV32 ZDINX */ + if (!TARGET_64BIT && TARGET_ZDINX){ + if (GET_MODE_CLASS (mode) == MODE_FLOAT && + GET_MODE_UNIT_SIZE (mode) == GET_MODE_SIZE (DFmode)) + return !(regno & 1); + } + return true; } @@ -4980,7 +4987,7 @@ riscv_option_override (void) error ("%<-mdiv%> requires %<-march%> to subsume the % extension"); /* Likewise floating-point division and square root. */ - if (TARGET_HARD_FLOAT && (target_flags_explicit & MASK_FDIV) == 0) + if ((TARGET_HARD_FLOAT || TARGET_ZFINX) && (target_flags_explicit & MASK_FDIV) == 0) target_flags |= MASK_FDIV; /* Handle -mtune, use -mcpu if -mtune is not given, and use default -mtune @@ -5026,6 +5033,11 @@ riscv_option_override (void) if (TARGET_RVE && riscv_abi != ABI_ILP32E) error ("rv32e requires ilp32e ABI"); + // Zfinx require abi ilp32,ilp32e or lp64. + if (TARGET_ZFINX && riscv_abi != ABI_ILP32 + && riscv_abi != ABI_LP64 && riscv_abi != ABI_ILP32E) + error ("z*inx requires ABI ilp32, ilp32e or lp64"); + /* We do not yet support ILP32 on RV64. */ if (BITS_PER_WORD != POINTER_SIZE) error ("ABI requires %<-march=rv%d%>", POINTER_SIZE);