[11/44] RISC-V/testsuite: Add branchless cases for integer cond-move operations
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Commit Message
Verify, for T-Head, Ventana and Zicond targets and the integer
conditional-move operations that already work as expected, if-conversion
to trigger via `noce_try_cmove' at the respective sufficiently high
`-mbranch-cost=' settings that make branchless code sequences produced
by if-conversion cheaper than their original branched equivalents, and
that extraneous instructions such as SNEZ, etc. are not present in
output. Cover all integer relational operations to make sure no corner
case escapes.
gcc/testsuite/
* gcc.target/riscv/movdieq-thead.c: New test.
* gcc.target/riscv/movdige-ventana.c: New test.
* gcc.target/riscv/movdige-zicond.c: New test.
* gcc.target/riscv/movdigeu-ventana.c: New test.
* gcc.target/riscv/movdigeu-zicond.c: New test.
* gcc.target/riscv/movdigt-ventana.c: New test.
* gcc.target/riscv/movdigt-zicond.c: New test.
* gcc.target/riscv/movdile-ventana.c: New test.
* gcc.target/riscv/movdile-zicond.c: New test.
* gcc.target/riscv/movdileu-ventana.c: New test.
* gcc.target/riscv/movdileu-zicond.c: New test.
* gcc.target/riscv/movdilt-ventana.c: New test.
* gcc.target/riscv/movdilt-zicond.c: New test.
* gcc.target/riscv/movdine-thead.c: New test.
* gcc.target/riscv/movsieq-thead.c: New test.
* gcc.target/riscv/movsige-ventana.c: New test.
* gcc.target/riscv/movsige-zicond.c: New test.
* gcc.target/riscv/movsigeu-ventana.c: New test.
* gcc.target/riscv/movsigeu-zicond.c: New test.
* gcc.target/riscv/movsigt-ventana.c: New test.
* gcc.target/riscv/movsigt-zicond.c: New test.
* gcc.target/riscv/movsile-ventana.c: New test.
* gcc.target/riscv/movsile-zicond.c: New test.
* gcc.target/riscv/movsileu-ventana.c: New test.
* gcc.target/riscv/movsileu-zicond.c: New test.
* gcc.target/riscv/movsilt-ventana.c: New test.
* gcc.target/riscv/movsilt-zicond.c: New test.
* gcc.target/riscv/movsine-thead.c: New test.
---
gcc/testsuite/gcc.target/riscv/movdieq-thead.c | 26 ++++++++++++++++++++
gcc/testsuite/gcc.target/riscv/movdige-ventana.c | 28 ++++++++++++++++++++++
gcc/testsuite/gcc.target/riscv/movdige-zicond.c | 28 ++++++++++++++++++++++
gcc/testsuite/gcc.target/riscv/movdigeu-ventana.c | 28 ++++++++++++++++++++++
gcc/testsuite/gcc.target/riscv/movdigeu-zicond.c | 28 ++++++++++++++++++++++
gcc/testsuite/gcc.target/riscv/movdigt-ventana.c | 28 ++++++++++++++++++++++
gcc/testsuite/gcc.target/riscv/movdigt-zicond.c | 28 ++++++++++++++++++++++
gcc/testsuite/gcc.target/riscv/movdile-ventana.c | 28 ++++++++++++++++++++++
gcc/testsuite/gcc.target/riscv/movdile-zicond.c | 28 ++++++++++++++++++++++
gcc/testsuite/gcc.target/riscv/movdileu-ventana.c | 28 ++++++++++++++++++++++
gcc/testsuite/gcc.target/riscv/movdileu-zicond.c | 28 ++++++++++++++++++++++
gcc/testsuite/gcc.target/riscv/movdilt-ventana.c | 28 ++++++++++++++++++++++
gcc/testsuite/gcc.target/riscv/movdilt-zicond.c | 28 ++++++++++++++++++++++
gcc/testsuite/gcc.target/riscv/movdine-thead.c | 26 ++++++++++++++++++++
gcc/testsuite/gcc.target/riscv/movsieq-thead.c | 26 ++++++++++++++++++++
gcc/testsuite/gcc.target/riscv/movsige-ventana.c | 28 ++++++++++++++++++++++
gcc/testsuite/gcc.target/riscv/movsige-zicond.c | 28 ++++++++++++++++++++++
gcc/testsuite/gcc.target/riscv/movsigeu-ventana.c | 28 ++++++++++++++++++++++
gcc/testsuite/gcc.target/riscv/movsigeu-zicond.c | 28 ++++++++++++++++++++++
gcc/testsuite/gcc.target/riscv/movsigt-ventana.c | 28 ++++++++++++++++++++++
gcc/testsuite/gcc.target/riscv/movsigt-zicond.c | 28 ++++++++++++++++++++++
gcc/testsuite/gcc.target/riscv/movsile-ventana.c | 28 ++++++++++++++++++++++
gcc/testsuite/gcc.target/riscv/movsile-zicond.c | 28 ++++++++++++++++++++++
gcc/testsuite/gcc.target/riscv/movsileu-ventana.c | 28 ++++++++++++++++++++++
gcc/testsuite/gcc.target/riscv/movsileu-zicond.c | 28 ++++++++++++++++++++++
gcc/testsuite/gcc.target/riscv/movsilt-ventana.c | 28 ++++++++++++++++++++++
gcc/testsuite/gcc.target/riscv/movsilt-zicond.c | 28 ++++++++++++++++++++++
gcc/testsuite/gcc.target/riscv/movsine-thead.c | 26 ++++++++++++++++++++
28 files changed, 776 insertions(+)
gcc-riscv-branch-cost-test-movcc.diff
Comments
LGTM.
Just one minor comment, I think we don't really need to check rv64 or
rv32 for those compiled without any header file test, but I am fine
with that.
On Sun, Nov 19, 2023 at 1:37 PM Maciej W. Rozycki <macro@embecosm.com> wrote:
>
> Verify, for T-Head, Ventana and Zicond targets and the integer
> conditional-move operations that already work as expected, if-conversion
> to trigger via `noce_try_cmove' at the respective sufficiently high
> `-mbranch-cost=' settings that make branchless code sequences produced
> by if-conversion cheaper than their original branched equivalents, and
> that extraneous instructions such as SNEZ, etc. are not present in
> output. Cover all integer relational operations to make sure no corner
> case escapes.
>
> gcc/testsuite/
> * gcc.target/riscv/movdieq-thead.c: New test.
> * gcc.target/riscv/movdige-ventana.c: New test.
> * gcc.target/riscv/movdige-zicond.c: New test.
> * gcc.target/riscv/movdigeu-ventana.c: New test.
> * gcc.target/riscv/movdigeu-zicond.c: New test.
> * gcc.target/riscv/movdigt-ventana.c: New test.
> * gcc.target/riscv/movdigt-zicond.c: New test.
> * gcc.target/riscv/movdile-ventana.c: New test.
> * gcc.target/riscv/movdile-zicond.c: New test.
> * gcc.target/riscv/movdileu-ventana.c: New test.
> * gcc.target/riscv/movdileu-zicond.c: New test.
> * gcc.target/riscv/movdilt-ventana.c: New test.
> * gcc.target/riscv/movdilt-zicond.c: New test.
> * gcc.target/riscv/movdine-thead.c: New test.
> * gcc.target/riscv/movsieq-thead.c: New test.
> * gcc.target/riscv/movsige-ventana.c: New test.
> * gcc.target/riscv/movsige-zicond.c: New test.
> * gcc.target/riscv/movsigeu-ventana.c: New test.
> * gcc.target/riscv/movsigeu-zicond.c: New test.
> * gcc.target/riscv/movsigt-ventana.c: New test.
> * gcc.target/riscv/movsigt-zicond.c: New test.
> * gcc.target/riscv/movsile-ventana.c: New test.
> * gcc.target/riscv/movsile-zicond.c: New test.
> * gcc.target/riscv/movsileu-ventana.c: New test.
> * gcc.target/riscv/movsileu-zicond.c: New test.
> * gcc.target/riscv/movsilt-ventana.c: New test.
> * gcc.target/riscv/movsilt-zicond.c: New test.
> * gcc.target/riscv/movsine-thead.c: New test.
> ---
> gcc/testsuite/gcc.target/riscv/movdieq-thead.c | 26 ++++++++++++++++++++
> gcc/testsuite/gcc.target/riscv/movdige-ventana.c | 28 ++++++++++++++++++++++
> gcc/testsuite/gcc.target/riscv/movdige-zicond.c | 28 ++++++++++++++++++++++
> gcc/testsuite/gcc.target/riscv/movdigeu-ventana.c | 28 ++++++++++++++++++++++
> gcc/testsuite/gcc.target/riscv/movdigeu-zicond.c | 28 ++++++++++++++++++++++
> gcc/testsuite/gcc.target/riscv/movdigt-ventana.c | 28 ++++++++++++++++++++++
> gcc/testsuite/gcc.target/riscv/movdigt-zicond.c | 28 ++++++++++++++++++++++
> gcc/testsuite/gcc.target/riscv/movdile-ventana.c | 28 ++++++++++++++++++++++
> gcc/testsuite/gcc.target/riscv/movdile-zicond.c | 28 ++++++++++++++++++++++
> gcc/testsuite/gcc.target/riscv/movdileu-ventana.c | 28 ++++++++++++++++++++++
> gcc/testsuite/gcc.target/riscv/movdileu-zicond.c | 28 ++++++++++++++++++++++
> gcc/testsuite/gcc.target/riscv/movdilt-ventana.c | 28 ++++++++++++++++++++++
> gcc/testsuite/gcc.target/riscv/movdilt-zicond.c | 28 ++++++++++++++++++++++
> gcc/testsuite/gcc.target/riscv/movdine-thead.c | 26 ++++++++++++++++++++
> gcc/testsuite/gcc.target/riscv/movsieq-thead.c | 26 ++++++++++++++++++++
> gcc/testsuite/gcc.target/riscv/movsige-ventana.c | 28 ++++++++++++++++++++++
> gcc/testsuite/gcc.target/riscv/movsige-zicond.c | 28 ++++++++++++++++++++++
> gcc/testsuite/gcc.target/riscv/movsigeu-ventana.c | 28 ++++++++++++++++++++++
> gcc/testsuite/gcc.target/riscv/movsigeu-zicond.c | 28 ++++++++++++++++++++++
> gcc/testsuite/gcc.target/riscv/movsigt-ventana.c | 28 ++++++++++++++++++++++
> gcc/testsuite/gcc.target/riscv/movsigt-zicond.c | 28 ++++++++++++++++++++++
> gcc/testsuite/gcc.target/riscv/movsile-ventana.c | 28 ++++++++++++++++++++++
> gcc/testsuite/gcc.target/riscv/movsile-zicond.c | 28 ++++++++++++++++++++++
> gcc/testsuite/gcc.target/riscv/movsileu-ventana.c | 28 ++++++++++++++++++++++
> gcc/testsuite/gcc.target/riscv/movsileu-zicond.c | 28 ++++++++++++++++++++++
> gcc/testsuite/gcc.target/riscv/movsilt-ventana.c | 28 ++++++++++++++++++++++
> gcc/testsuite/gcc.target/riscv/movsilt-zicond.c | 28 ++++++++++++++++++++++
> gcc/testsuite/gcc.target/riscv/movsine-thead.c | 26 ++++++++++++++++++++
> 28 files changed, 776 insertions(+)
>
> gcc-riscv-branch-cost-test-movcc.diff
> Index: gcc/gcc/testsuite/gcc.target/riscv/movdieq-thead.c
> ===================================================================
> --- /dev/null
> +++ gcc/gcc/testsuite/gcc.target/riscv/movdieq-thead.c
> @@ -0,0 +1,26 @@
> +/* { dg-do compile } */
> +/* { dg-require-effective-target rv64 } */
> +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
> +/* { dg-options "-march=rv64gc_xtheadcondmov -mtune=thead-c906 -mbranch-cost=2 -fdump-rtl-ce1" } */
> +
> +typedef int __attribute__ ((mode (DI))) int_t;
> +
> +int_t
> +movdieq (int_t w, int_t x, int_t y, int_t z)
> +{
> + return w == x ? y : z;
> +}
> +
> +/* Expect branchless assembly like:
> +
> + sub a0,a0,a1
> + th.mvnez a2,a3,a0
> + mv a0,a2
> + */
> +
> +/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */
> +/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */
> +/* { dg-final { scan-assembler-times "\\ssub\\s" 1 } } */
> +/* { dg-final { scan-assembler-times "\\s(?:th\\.mveqz|th\\.mvnez)\\s" 1 } } */
> +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
> +/* { dg-final { scan-assembler-not "\\s(?:beq|bne)\\s" } } */
> Index: gcc/gcc/testsuite/gcc.target/riscv/movdige-ventana.c
> ===================================================================
> --- /dev/null
> +++ gcc/gcc/testsuite/gcc.target/riscv/movdige-ventana.c
> @@ -0,0 +1,28 @@
> +/* { dg-do compile } */
> +/* { dg-require-effective-target rv64 } */
> +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
> +/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=4 -fdump-rtl-ce1" } */
> +
> +typedef int __attribute__ ((mode (DI))) int_t;
> +
> +int_t
> +movdige (int_t w, int_t x, int_t y, int_t z)
> +{
> + return w >= x ? y : z;
> +}
> +
> +/* Expect branchless assembly like:
> +
> + slt a1,a0,a1
> + vt.maskc a3,a3,a1
> + vt.maskcn a1,a2,a1
> + or a0,a1,a3
> + */
> +
> +/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */
> +/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */
> +/* { dg-final { scan-assembler-times "\\s(?:sgt|slt)\\s" 1 } } */
> +/* { dg-final { scan-assembler-times "\\svt\\.maskc\\s" 1 } } */
> +/* { dg-final { scan-assembler-times "\\svt\\.maskcn\\s" 1 } } */
> +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
> +/* { dg-final { scan-assembler-not "\\s(?:bge|bgt|ble|blt)\\s" } } */
> Index: gcc/gcc/testsuite/gcc.target/riscv/movdige-zicond.c
> ===================================================================
> --- /dev/null
> +++ gcc/gcc/testsuite/gcc.target/riscv/movdige-zicond.c
> @@ -0,0 +1,28 @@
> +/* { dg-do compile } */
> +/* { dg-require-effective-target rv64 } */
> +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
> +/* { dg-options "-march=rv64gc_zicond -mtune=rocket -mbranch-cost=4 -fdump-rtl-ce1" } */
> +
> +typedef int __attribute__ ((mode (DI))) int_t;
> +
> +int_t
> +movdige (int_t w, int_t x, int_t y, int_t z)
> +{
> + return w >= x ? y : z;
> +}
> +
> +/* Expect branchless assembly like:
> +
> + slt a1,a0,a1
> + czero.eqz a3,a3,a1
> + czero.nez a1,a2,a1
> + or a0,a1,a3
> + */
> +
> +/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */
> +/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */
> +/* { dg-final { scan-assembler-times "\\s(?:sgt|slt)\\s" 1 } } */
> +/* { dg-final { scan-assembler-times "\\sczero\\.eqz\\s" 1 } } */
> +/* { dg-final { scan-assembler-times "\\sczero\\.nez\\s" 1 } } */
> +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
> +/* { dg-final { scan-assembler-not "\\s(?:bge|bgt|ble|blt)\\s" } } */
> Index: gcc/gcc/testsuite/gcc.target/riscv/movdigeu-ventana.c
> ===================================================================
> --- /dev/null
> +++ gcc/gcc/testsuite/gcc.target/riscv/movdigeu-ventana.c
> @@ -0,0 +1,28 @@
> +/* { dg-do compile } */
> +/* { dg-require-effective-target rv64 } */
> +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
> +/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=4 -fdump-rtl-ce1" } */
> +
> +typedef unsigned int __attribute__ ((mode (DI))) int_t;
> +
> +int_t
> +movdigeu (int_t w, int_t x, int_t y, int_t z)
> +{
> + return w >= x ? y : z;
> +}
> +
> +/* Expect branchless assembly like:
> +
> + sltu a1,a0,a1
> + vt.maskc a3,a3,a1
> + vt.maskcn a1,a2,a1
> + or a0,a1,a3
> + */
> +
> +/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */
> +/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */
> +/* { dg-final { scan-assembler-times "\\s(?:sgtu|sltu)\\s" 1 } } */
> +/* { dg-final { scan-assembler-times "\\svt\\.maskc\\s" 1 } } */
> +/* { dg-final { scan-assembler-times "\\svt\\.maskcn\\s" 1 } } */
> +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
> +/* { dg-final { scan-assembler-not "\\s(?:bgeu|bgtu|bleu|bltu)\\s" } } */
> Index: gcc/gcc/testsuite/gcc.target/riscv/movdigeu-zicond.c
> ===================================================================
> --- /dev/null
> +++ gcc/gcc/testsuite/gcc.target/riscv/movdigeu-zicond.c
> @@ -0,0 +1,28 @@
> +/* { dg-do compile } */
> +/* { dg-require-effective-target rv64 } */
> +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
> +/* { dg-options "-march=rv64gc_zicond -mtune=rocket -mbranch-cost=4 -fdump-rtl-ce1" } */
> +
> +typedef unsigned int __attribute__ ((mode (DI))) int_t;
> +
> +int_t
> +movdigeu (int_t w, int_t x, int_t y, int_t z)
> +{
> + return w >= x ? y : z;
> +}
> +
> +/* Expect branchless assembly like:
> +
> + sltu a1,a0,a1
> + czero.eqz a3,a3,a1
> + czero.nez a1,a2,a1
> + or a0,a1,a3
> + */
> +
> +/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */
> +/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */
> +/* { dg-final { scan-assembler-times "\\s(?:sgtu|sltu)\\s" 1 } } */
> +/* { dg-final { scan-assembler-times "\\sczero\\.eqz\\s" 1 } } */
> +/* { dg-final { scan-assembler-times "\\sczero\\.nez\\s" 1 } } */
> +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
> +/* { dg-final { scan-assembler-not "\\s(?:bgeu|bgtu|bleu|bltu)\\s" } } */
> Index: gcc/gcc/testsuite/gcc.target/riscv/movdigt-ventana.c
> ===================================================================
> --- /dev/null
> +++ gcc/gcc/testsuite/gcc.target/riscv/movdigt-ventana.c
> @@ -0,0 +1,28 @@
> +/* { dg-do compile } */
> +/* { dg-require-effective-target rv64 } */
> +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
> +/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=4 -fdump-rtl-ce1" } */
> +
> +typedef int __attribute__ ((mode (DI))) int_t;
> +
> +int_t
> +movdigt (int_t w, int_t x, int_t y, int_t z)
> +{
> + return w > x ? y : z;
> +}
> +
> +/* Expect branchless assembly like:
> +
> + sgt a1,a0,a1
> + vt.maskcn a3,a3,a1
> + vt.maskc a1,a2,a1
> + or a0,a1,a3
> + */
> +
> +/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */
> +/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */
> +/* { dg-final { scan-assembler-times "\\s(?:sgt|slt)\\s" 1 } } */
> +/* { dg-final { scan-assembler-times "\\svt\\.maskc\\s" 1 } } */
> +/* { dg-final { scan-assembler-times "\\svt\\.maskcn\\s" 1 } } */
> +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
> +/* { dg-final { scan-assembler-not "\\s(?:bge|bgt|ble|blt)\\s" } } */
> Index: gcc/gcc/testsuite/gcc.target/riscv/movdigt-zicond.c
> ===================================================================
> --- /dev/null
> +++ gcc/gcc/testsuite/gcc.target/riscv/movdigt-zicond.c
> @@ -0,0 +1,28 @@
> +/* { dg-do compile } */
> +/* { dg-require-effective-target rv64 } */
> +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
> +/* { dg-options "-march=rv64gc_zicond -mtune=rocket -mbranch-cost=4 -fdump-rtl-ce1" } */
> +
> +typedef int __attribute__ ((mode (DI))) int_t;
> +
> +int_t
> +movdigt (int_t w, int_t x, int_t y, int_t z)
> +{
> + return w > x ? y : z;
> +}
> +
> +/* Expect branchless assembly like:
> +
> + sgt a1,a0,a1
> + czero.nez a3,a3,a1
> + czero.eqz a1,a2,a1
> + or a0,a1,a3
> + */
> +
> +/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */
> +/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */
> +/* { dg-final { scan-assembler-times "\\s(?:sgt|slt)\\s" 1 } } */
> +/* { dg-final { scan-assembler-times "\\sczero\\.eqz\\s" 1 } } */
> +/* { dg-final { scan-assembler-times "\\sczero\\.nez\\s" 1 } } */
> +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
> +/* { dg-final { scan-assembler-not "\\s(?:bge|bgt|ble|blt)\\s" } } */
> Index: gcc/gcc/testsuite/gcc.target/riscv/movdile-ventana.c
> ===================================================================
> --- /dev/null
> +++ gcc/gcc/testsuite/gcc.target/riscv/movdile-ventana.c
> @@ -0,0 +1,28 @@
> +/* { dg-do compile } */
> +/* { dg-require-effective-target rv64 } */
> +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
> +/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=4 -fdump-rtl-ce1" } */
> +
> +typedef int __attribute__ ((mode (DI))) int_t;
> +
> +int_t
> +movdile (int_t w, int_t x, int_t y, int_t z)
> +{
> + return w <= x ? y : z;
> +}
> +
> +/* Expect branchless assembly like:
> +
> + sgt a1,a0,a1
> + vt.maskc a3,a3,a1
> + vt.maskcn a1,a2,a1
> + or a0,a1,a3
> + */
> +
> +/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */
> +/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */
> +/* { dg-final { scan-assembler-times "\\s(?:sgt|slt)\\s" 1 } } */
> +/* { dg-final { scan-assembler-times "\\svt\\.maskc\\s" 1 } } */
> +/* { dg-final { scan-assembler-times "\\svt\\.maskcn\\s" 1 } } */
> +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
> +/* { dg-final { scan-assembler-not "\\s(?:bge|bgt|ble|blt)\\s" } } */
> Index: gcc/gcc/testsuite/gcc.target/riscv/movdile-zicond.c
> ===================================================================
> --- /dev/null
> +++ gcc/gcc/testsuite/gcc.target/riscv/movdile-zicond.c
> @@ -0,0 +1,28 @@
> +/* { dg-do compile } */
> +/* { dg-require-effective-target rv64 } */
> +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
> +/* { dg-options "-march=rv64gc_zicond -mtune=rocket -mbranch-cost=4 -fdump-rtl-ce1" } */
> +
> +typedef int __attribute__ ((mode (DI))) int_t;
> +
> +int_t
> +movdile (int_t w, int_t x, int_t y, int_t z)
> +{
> + return w <= x ? y : z;
> +}
> +
> +/* Expect branchless assembly like:
> +
> + sgt a1,a0,a1
> + czero.eqz a3,a3,a1
> + czero.nez a1,a2,a1
> + or a0,a1,a3
> + */
> +
> +/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */
> +/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */
> +/* { dg-final { scan-assembler-times "\\s(?:sgt|slt)\\s" 1 } } */
> +/* { dg-final { scan-assembler-times "\\sczero\\.eqz\\s" 1 } } */
> +/* { dg-final { scan-assembler-times "\\sczero\\.nez\\s" 1 } } */
> +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
> +/* { dg-final { scan-assembler-not "\\s(?:bge|bgt|ble|blt)\\s" } } */
> Index: gcc/gcc/testsuite/gcc.target/riscv/movdileu-ventana.c
> ===================================================================
> --- /dev/null
> +++ gcc/gcc/testsuite/gcc.target/riscv/movdileu-ventana.c
> @@ -0,0 +1,28 @@
> +/* { dg-do compile } */
> +/* { dg-require-effective-target rv64 } */
> +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
> +/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=4 -fdump-rtl-ce1" } */
> +
> +typedef unsigned int __attribute__ ((mode (DI))) int_t;
> +
> +int_t
> +movdileu (int_t w, int_t x, int_t y, int_t z)
> +{
> + return w <= x ? y : z;
> +}
> +
> +/* Expect branchless assembly like:
> +
> + sgtu a1,a0,a1
> + vt.maskc a3,a3,a1
> + vt.maskcn a1,a2,a1
> + or a0,a1,a3
> + */
> +
> +/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */
> +/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */
> +/* { dg-final { scan-assembler-times "\\s(?:sgtu|sltu)\\s" 1 } } */
> +/* { dg-final { scan-assembler-times "\\svt\\.maskc\\s" 1 } } */
> +/* { dg-final { scan-assembler-times "\\svt\\.maskcn\\s" 1 } } */
> +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
> +/* { dg-final { scan-assembler-not "\\s(?:bgeu|bgtu|bleu|bltu)\\s" } } */
> Index: gcc/gcc/testsuite/gcc.target/riscv/movdileu-zicond.c
> ===================================================================
> --- /dev/null
> +++ gcc/gcc/testsuite/gcc.target/riscv/movdileu-zicond.c
> @@ -0,0 +1,28 @@
> +/* { dg-do compile } */
> +/* { dg-require-effective-target rv64 } */
> +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
> +/* { dg-options "-march=rv64gc_zicond -mtune=rocket -mbranch-cost=4 -fdump-rtl-ce1" } */
> +
> +typedef unsigned int __attribute__ ((mode (DI))) int_t;
> +
> +int_t
> +movdileu (int_t w, int_t x, int_t y, int_t z)
> +{
> + return w <= x ? y : z;
> +}
> +
> +/* Expect branchless assembly like:
> +
> + sgtu a1,a0,a1
> + czero.eqz a3,a3,a1
> + czero.nez a1,a2,a1
> + or a0,a1,a3
> + */
> +
> +/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */
> +/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */
> +/* { dg-final { scan-assembler-times "\\s(?:sgtu|sltu)\\s" 1 } } */
> +/* { dg-final { scan-assembler-times "\\sczero\\.eqz\\s" 1 } } */
> +/* { dg-final { scan-assembler-times "\\sczero\\.nez\\s" 1 } } */
> +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
> +/* { dg-final { scan-assembler-not "\\s(?:bgeu|bgtu|bleu|bltu)\\s" } } */
> Index: gcc/gcc/testsuite/gcc.target/riscv/movdilt-ventana.c
> ===================================================================
> --- /dev/null
> +++ gcc/gcc/testsuite/gcc.target/riscv/movdilt-ventana.c
> @@ -0,0 +1,28 @@
> +/* { dg-do compile } */
> +/* { dg-require-effective-target rv64 } */
> +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
> +/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=4 -fdump-rtl-ce1" } */
> +
> +typedef int __attribute__ ((mode (DI))) int_t;
> +
> +int_t
> +movdilt (int_t w, int_t x, int_t y, int_t z)
> +{
> + return w < x ? y : z;
> +}
> +
> +/* Expect branchless assembly like:
> +
> + slt a1,a0,a1
> + vt.maskcn a3,a3,a1
> + vt.maskc a1,a2,a1
> + or a0,a1,a3
> + */
> +
> +/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */
> +/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */
> +/* { dg-final { scan-assembler-times "\\s(?:sgt|slt)\\s" 1 } } */
> +/* { dg-final { scan-assembler-times "\\svt\\.maskc\\s" 1 } } */
> +/* { dg-final { scan-assembler-times "\\svt\\.maskcn\\s" 1 } } */
> +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
> +/* { dg-final { scan-assembler-not "\\s(?:bge|bgt|ble|blt)\\s" } } */
> Index: gcc/gcc/testsuite/gcc.target/riscv/movdilt-zicond.c
> ===================================================================
> --- /dev/null
> +++ gcc/gcc/testsuite/gcc.target/riscv/movdilt-zicond.c
> @@ -0,0 +1,28 @@
> +/* { dg-do compile } */
> +/* { dg-require-effective-target rv64 } */
> +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
> +/* { dg-options "-march=rv64gc_zicond -mtune=rocket -mbranch-cost=4 -fdump-rtl-ce1" } */
> +
> +typedef int __attribute__ ((mode (DI))) int_t;
> +
> +int_t
> +movdilt (int_t w, int_t x, int_t y, int_t z)
> +{
> + return w < x ? y : z;
> +}
> +
> +/* Expect branchless assembly like:
> +
> + slt a1,a0,a1
> + czero.nez a3,a3,a1
> + czero.eqz a1,a2,a1
> + or a0,a1,a3
> + */
> +
> +/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */
> +/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */
> +/* { dg-final { scan-assembler-times "\\s(?:sgt|slt)\\s" 1 } } */
> +/* { dg-final { scan-assembler-times "\\sczero\\.eqz\\s" 1 } } */
> +/* { dg-final { scan-assembler-times "\\sczero\\.nez\\s" 1 } } */
> +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
> +/* { dg-final { scan-assembler-not "\\s(?:bge|bgt|ble|blt)\\s" } } */
> Index: gcc/gcc/testsuite/gcc.target/riscv/movdine-thead.c
> ===================================================================
> --- /dev/null
> +++ gcc/gcc/testsuite/gcc.target/riscv/movdine-thead.c
> @@ -0,0 +1,26 @@
> +/* { dg-do compile } */
> +/* { dg-require-effective-target rv64 } */
> +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
> +/* { dg-options "-march=rv64gc_xtheadcondmov -mtune=thead-c906 -mbranch-cost=2 -fdump-rtl-ce1" } */
> +
> +typedef int __attribute__ ((mode (DI))) int_t;
> +
> +int_t
> +movdine (int_t w, int_t x, int_t y, int_t z)
> +{
> + return w != x ? y : z;
> +}
> +
> +/* Expect branchless assembly like:
> +
> + sub a1,a0,a1
> + th.mveqz a2,a3,a1
> + mv a0,a2
> + */
> +
> +/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */
> +/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */
> +/* { dg-final { scan-assembler-times "\\ssub\\s" 1 } } */
> +/* { dg-final { scan-assembler-times "\\s(?:th\\.mveqz|th\\.mvnez)\\s" 1 } } */
> +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
> +/* { dg-final { scan-assembler-not "\\s(?:beq|bne)\\s" } } */
> Index: gcc/gcc/testsuite/gcc.target/riscv/movsieq-thead.c
> ===================================================================
> --- /dev/null
> +++ gcc/gcc/testsuite/gcc.target/riscv/movsieq-thead.c
> @@ -0,0 +1,26 @@
> +/* { dg-do compile } */
> +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
> +/* { dg-options "-march=rv64gc_xtheadcondmov -mtune=thead-c906 -mbranch-cost=2 -fdump-rtl-ce1" { target { rv64 } } } */
> +/* { dg-options "-march=rv32gc_xtheadcondmov -mtune=thead-c906 -mbranch-cost=2 -fdump-rtl-ce1" { target { rv32 } } } */
> +
> +typedef int __attribute__ ((mode (SI))) int_t;
> +
> +int_t
> +movsieq (int_t w, int_t x, int_t y, int_t z)
> +{
> + return w == x ? y : z;
> +}
> +
> +/* Expect branchless assembly like:
> +
> + sub a0,a0,a1
> + th.mvnez a2,a3,a0
> + mv a0,a2
> + */
> +
> +/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */
> +/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */
> +/* { dg-final { scan-assembler-times "\\ssub\\s" 1 } } */
> +/* { dg-final { scan-assembler-times "\\s(?:th\\.mveqz|th\\.mvnez)\\s" 1 } } */
> +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
> +/* { dg-final { scan-assembler-not "\\s(?:beq|bne)\\s" } } */
> Index: gcc/gcc/testsuite/gcc.target/riscv/movsige-ventana.c
> ===================================================================
> --- /dev/null
> +++ gcc/gcc/testsuite/gcc.target/riscv/movsige-ventana.c
> @@ -0,0 +1,28 @@
> +/* { dg-do compile } */
> +/* { dg-require-effective-target rv64 } */
> +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
> +/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=4 -fdump-rtl-ce1" } */
> +
> +typedef int __attribute__ ((mode (SI))) int_t;
> +
> +int_t
> +movsige (int_t w, int_t x, int_t y, int_t z)
> +{
> + return w >= x ? y : z;
> +}
> +
> +/* Expect branchless assembly like:
> +
> + slt a1,a0,a1
> + vt.maskc a3,a3,a1
> + vt.maskcn a1,a2,a1
> + or a0,a1,a3
> + */
> +
> +/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */
> +/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */
> +/* { dg-final { scan-assembler-times "\\s(?:sgt|slt)\\s" 1 } } */
> +/* { dg-final { scan-assembler-times "\\svt\\.maskc\\s" 1 } } */
> +/* { dg-final { scan-assembler-times "\\svt\\.maskcn\\s" 1 } } */
> +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
> +/* { dg-final { scan-assembler-not "\\s(?:bge|bgt|ble|blt)\\s" } } */
> Index: gcc/gcc/testsuite/gcc.target/riscv/movsige-zicond.c
> ===================================================================
> --- /dev/null
> +++ gcc/gcc/testsuite/gcc.target/riscv/movsige-zicond.c
> @@ -0,0 +1,28 @@
> +/* { dg-do compile } */
> +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
> +/* { dg-options "-march=rv64gc_zicond -mtune=rocket -mbranch-cost=4 -fdump-rtl-ce1" { target { rv64 } } } */
> +/* { dg-options "-march=rv32gc_zicond -mtune=rocket -mbranch-cost=4 -fdump-rtl-ce1" { target { rv32 } } } */
> +
> +typedef int __attribute__ ((mode (SI))) int_t;
> +
> +int_t
> +movsige (int_t w, int_t x, int_t y, int_t z)
> +{
> + return w >= x ? y : z;
> +}
> +
> +/* Expect branchless assembly like:
> +
> + slt a1,a0,a1
> + czero.eqz a3,a3,a1
> + czero.nez a1,a2,a1
> + or a0,a1,a3
> + */
> +
> +/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */
> +/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */
> +/* { dg-final { scan-assembler-times "\\s(?:sgt|slt)\\s" 1 } } */
> +/* { dg-final { scan-assembler-times "\\sczero\\.eqz\\s" 1 } } */
> +/* { dg-final { scan-assembler-times "\\sczero\\.nez\\s" 1 } } */
> +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
> +/* { dg-final { scan-assembler-not "\\s(?:bge|bgt|ble|blt)\\s" } } */
> Index: gcc/gcc/testsuite/gcc.target/riscv/movsigeu-ventana.c
> ===================================================================
> --- /dev/null
> +++ gcc/gcc/testsuite/gcc.target/riscv/movsigeu-ventana.c
> @@ -0,0 +1,28 @@
> +/* { dg-do compile } */
> +/* { dg-require-effective-target rv64 } */
> +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
> +/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=4 -fdump-rtl-ce1" } */
> +
> +typedef unsigned int __attribute__ ((mode (SI))) int_t;
> +
> +int_t
> +movsigeu (int_t w, int_t x, int_t y, int_t z)
> +{
> + return w >= x ? y : z;
> +}
> +
> +/* Expect branchless assembly like:
> +
> + sltu a1,a0,a1
> + vt.maskc a3,a3,a1
> + vt.maskcn a1,a2,a1
> + or a0,a1,a3
> + */
> +
> +/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */
> +/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */
> +/* { dg-final { scan-assembler-times "\\s(?:sgtu|sltu)\\s" 1 } } */
> +/* { dg-final { scan-assembler-times "\\svt\\.maskc\\s" 1 } } */
> +/* { dg-final { scan-assembler-times "\\svt\\.maskcn\\s" 1 } } */
> +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
> +/* { dg-final { scan-assembler-not "\\s(?:bgeu|bgtu|bleu|bltu)\\s" } } */
> Index: gcc/gcc/testsuite/gcc.target/riscv/movsigeu-zicond.c
> ===================================================================
> --- /dev/null
> +++ gcc/gcc/testsuite/gcc.target/riscv/movsigeu-zicond.c
> @@ -0,0 +1,28 @@
> +/* { dg-do compile } */
> +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
> +/* { dg-options "-march=rv64gc_zicond -mtune=rocket -mbranch-cost=4 -fdump-rtl-ce1" { target { rv64 } } } */
> +/* { dg-options "-march=rv32gc_zicond -mtune=rocket -mbranch-cost=4 -fdump-rtl-ce1" { target { rv32 } } } */
> +
> +typedef unsigned int __attribute__ ((mode (SI))) int_t;
> +
> +int_t
> +movsigeu (int_t w, int_t x, int_t y, int_t z)
> +{
> + return w >= x ? y : z;
> +}
> +
> +/* Expect branchless assembly like:
> +
> + sltu a1,a0,a1
> + czero.eqz a3,a3,a1
> + czero.nez a1,a2,a1
> + or a0,a1,a3
> + */
> +
> +/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */
> +/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */
> +/* { dg-final { scan-assembler-times "\\s(?:sgtu|sltu)\\s" 1 } } */
> +/* { dg-final { scan-assembler-times "\\sczero\\.eqz\\s" 1 } } */
> +/* { dg-final { scan-assembler-times "\\sczero\\.nez\\s" 1 } } */
> +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
> +/* { dg-final { scan-assembler-not "\\s(?:bgeu|bgtu|bleu|bltu)\\s" } } */
> Index: gcc/gcc/testsuite/gcc.target/riscv/movsigt-ventana.c
> ===================================================================
> --- /dev/null
> +++ gcc/gcc/testsuite/gcc.target/riscv/movsigt-ventana.c
> @@ -0,0 +1,28 @@
> +/* { dg-do compile } */
> +/* { dg-require-effective-target rv64 } */
> +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
> +/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=4 -fdump-rtl-ce1" } */
> +
> +typedef int __attribute__ ((mode (SI))) int_t;
> +
> +int_t
> +movsigt (int_t w, int_t x, int_t y, int_t z)
> +{
> + return w > x ? y : z;
> +}
> +
> +/* Expect branchless assembly like:
> +
> + sgt a1,a0,a1
> + vt.maskcn a3,a3,a1
> + vt.maskc a1,a2,a1
> + or a0,a1,a3
> + */
> +
> +/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */
> +/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */
> +/* { dg-final { scan-assembler-times "\\s(?:sgt|slt)\\s" 1 } } */
> +/* { dg-final { scan-assembler-times "\\svt\\.maskc\\s" 1 } } */
> +/* { dg-final { scan-assembler-times "\\svt\\.maskcn\\s" 1 } } */
> +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
> +/* { dg-final { scan-assembler-not "\\s(?:bge|bgt|ble|blt)\\s" } } */
> Index: gcc/gcc/testsuite/gcc.target/riscv/movsigt-zicond.c
> ===================================================================
> --- /dev/null
> +++ gcc/gcc/testsuite/gcc.target/riscv/movsigt-zicond.c
> @@ -0,0 +1,28 @@
> +/* { dg-do compile } */
> +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
> +/* { dg-options "-march=rv64gc_zicond -mtune=rocket -mbranch-cost=4 -fdump-rtl-ce1" { target { rv64 } } } */
> +/* { dg-options "-march=rv32gc_zicond -mtune=rocket -mbranch-cost=4 -fdump-rtl-ce1" { target { rv32 } } } */
> +
> +typedef int __attribute__ ((mode (SI))) int_t;
> +
> +int_t
> +movsigt (int_t w, int_t x, int_t y, int_t z)
> +{
> + return w > x ? y : z;
> +}
> +
> +/* Expect branchless assembly like:
> +
> + sgt a1,a0,a1
> + czero.nez a3,a3,a1
> + czero.eqz a1,a2,a1
> + or a0,a1,a3
> + */
> +
> +/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */
> +/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */
> +/* { dg-final { scan-assembler-times "\\s(?:sgt|slt)\\s" 1 } } */
> +/* { dg-final { scan-assembler-times "\\sczero\\.eqz\\s" 1 } } */
> +/* { dg-final { scan-assembler-times "\\sczero\\.nez\\s" 1 } } */
> +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
> +/* { dg-final { scan-assembler-not "\\s(?:bge|bgt|ble|blt)\\s" } } */
> Index: gcc/gcc/testsuite/gcc.target/riscv/movsile-ventana.c
> ===================================================================
> --- /dev/null
> +++ gcc/gcc/testsuite/gcc.target/riscv/movsile-ventana.c
> @@ -0,0 +1,28 @@
> +/* { dg-do compile } */
> +/* { dg-require-effective-target rv64 } */
> +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
> +/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=4 -fdump-rtl-ce1" } */
> +
> +typedef int __attribute__ ((mode (SI))) int_t;
> +
> +int_t
> +movsile (int_t w, int_t x, int_t y, int_t z)
> +{
> + return w <= x ? y : z;
> +}
> +
> +/* Expect branchless assembly like:
> +
> + sgt a1,a0,a1
> + vt.maskc a3,a3,a1
> + vt.maskcn a1,a2,a1
> + or a0,a1,a3
> + */
> +
> +/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */
> +/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */
> +/* { dg-final { scan-assembler-times "\\s(?:sgt|slt)\\s" 1 } } */
> +/* { dg-final { scan-assembler-times "\\svt\\.maskc\\s" 1 } } */
> +/* { dg-final { scan-assembler-times "\\svt\\.maskcn\\s" 1 } } */
> +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
> +/* { dg-final { scan-assembler-not "\\s(?:bge|bgt|ble|blt)\\s" } } */
> Index: gcc/gcc/testsuite/gcc.target/riscv/movsile-zicond.c
> ===================================================================
> --- /dev/null
> +++ gcc/gcc/testsuite/gcc.target/riscv/movsile-zicond.c
> @@ -0,0 +1,28 @@
> +/* { dg-do compile } */
> +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
> +/* { dg-options "-march=rv64gc_zicond -mtune=rocket -mbranch-cost=4 -fdump-rtl-ce1" { target { rv64 } } } */
> +/* { dg-options "-march=rv32gc_zicond -mtune=rocket -mbranch-cost=4 -fdump-rtl-ce1" { target { rv32 } } } */
> +
> +typedef int __attribute__ ((mode (SI))) int_t;
> +
> +int_t
> +movsile (int_t w, int_t x, int_t y, int_t z)
> +{
> + return w <= x ? y : z;
> +}
> +
> +/* Expect branchless assembly like:
> +
> + sgt a1,a0,a1
> + czero.eqz a3,a3,a1
> + czero.nez a1,a2,a1
> + or a0,a1,a3
> + */
> +
> +/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */
> +/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */
> +/* { dg-final { scan-assembler-times "\\s(?:sgt|slt)\\s" 1 } } */
> +/* { dg-final { scan-assembler-times "\\sczero\\.eqz\\s" 1 } } */
> +/* { dg-final { scan-assembler-times "\\sczero\\.nez\\s" 1 } } */
> +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
> +/* { dg-final { scan-assembler-not "\\s(?:bge|bgt|ble|blt)\\s" } } */
> Index: gcc/gcc/testsuite/gcc.target/riscv/movsileu-ventana.c
> ===================================================================
> --- /dev/null
> +++ gcc/gcc/testsuite/gcc.target/riscv/movsileu-ventana.c
> @@ -0,0 +1,28 @@
> +/* { dg-do compile } */
> +/* { dg-require-effective-target rv64 } */
> +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
> +/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=4 -fdump-rtl-ce1" } */
> +
> +typedef unsigned int __attribute__ ((mode (SI))) int_t;
> +
> +int_t
> +movsileu (int_t w, int_t x, int_t y, int_t z)
> +{
> + return w <= x ? y : z;
> +}
> +
> +/* Expect branchless assembly like:
> +
> + sgtu a1,a0,a1
> + vt.maskc a3,a3,a1
> + vt.maskcn a1,a2,a1
> + or a0,a1,a3
> + */
> +
> +/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */
> +/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */
> +/* { dg-final { scan-assembler-times "\\s(?:sgtu|sltu)\\s" 1 } } */
> +/* { dg-final { scan-assembler-times "\\svt\\.maskc\\s" 1 } } */
> +/* { dg-final { scan-assembler-times "\\svt\\.maskcn\\s" 1 } } */
> +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
> +/* { dg-final { scan-assembler-not "\\s(?:bgeu|bgtu|bleu|bltu)\\s" } } */
> Index: gcc/gcc/testsuite/gcc.target/riscv/movsileu-zicond.c
> ===================================================================
> --- /dev/null
> +++ gcc/gcc/testsuite/gcc.target/riscv/movsileu-zicond.c
> @@ -0,0 +1,28 @@
> +/* { dg-do compile } */
> +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
> +/* { dg-options "-march=rv64gc_zicond -mtune=rocket -mbranch-cost=4 -fdump-rtl-ce1" { target { rv64 } } } */
> +/* { dg-options "-march=rv32gc_zicond -mtune=rocket -mbranch-cost=4 -fdump-rtl-ce1" { target { rv32 } } } */
> +
> +typedef unsigned int __attribute__ ((mode (SI))) int_t;
> +
> +int_t
> +movsileu (int_t w, int_t x, int_t y, int_t z)
> +{
> + return w <= x ? y : z;
> +}
> +
> +/* Expect branchless assembly like:
> +
> + sgtu a1,a0,a1
> + czero.eqz a3,a3,a1
> + czero.nez a1,a2,a1
> + or a0,a1,a3
> + */
> +
> +/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */
> +/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */
> +/* { dg-final { scan-assembler-times "\\s(?:sgtu|sltu)\\s" 1 } } */
> +/* { dg-final { scan-assembler-times "\\sczero\\.eqz\\s" 1 } } */
> +/* { dg-final { scan-assembler-times "\\sczero\\.nez\\s" 1 } } */
> +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
> +/* { dg-final { scan-assembler-not "\\s(?:bgeu|bgtu|bleu|bltu)\\s" } } */
> Index: gcc/gcc/testsuite/gcc.target/riscv/movsilt-ventana.c
> ===================================================================
> --- /dev/null
> +++ gcc/gcc/testsuite/gcc.target/riscv/movsilt-ventana.c
> @@ -0,0 +1,28 @@
> +/* { dg-do compile } */
> +/* { dg-require-effective-target rv64 } */
> +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
> +/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=4 -fdump-rtl-ce1" } */
> +
> +typedef int __attribute__ ((mode (SI))) int_t;
> +
> +int_t
> +movsilt (int_t w, int_t x, int_t y, int_t z)
> +{
> + return w < x ? y : z;
> +}
> +
> +/* Expect branchless assembly like:
> +
> + slt a1,a0,a1
> + vt.maskcn a3,a3,a1
> + vt.maskc a1,a2,a1
> + or a0,a1,a3
> + */
> +
> +/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */
> +/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */
> +/* { dg-final { scan-assembler-times "\\s(?:sgt|slt)\\s" 1 } } */
> +/* { dg-final { scan-assembler-times "\\svt\\.maskc\\s" 1 } } */
> +/* { dg-final { scan-assembler-times "\\svt\\.maskcn\\s" 1 } } */
> +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
> +/* { dg-final { scan-assembler-not "\\s(?:bge|bgt|ble|blt)\\s" } } */
> Index: gcc/gcc/testsuite/gcc.target/riscv/movsilt-zicond.c
> ===================================================================
> --- /dev/null
> +++ gcc/gcc/testsuite/gcc.target/riscv/movsilt-zicond.c
> @@ -0,0 +1,28 @@
> +/* { dg-do compile } */
> +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
> +/* { dg-options "-march=rv64gc_zicond -mtune=rocket -mbranch-cost=4 -fdump-rtl-ce1" { target { rv64 } } } */
> +/* { dg-options "-march=rv32gc_zicond -mtune=rocket -mbranch-cost=4 -fdump-rtl-ce1" { target { rv32 } } } */
> +
> +typedef int __attribute__ ((mode (SI))) int_t;
> +
> +int_t
> +movsilt (int_t w, int_t x, int_t y, int_t z)
> +{
> + return w < x ? y : z;
> +}
> +
> +/* Expect branchless assembly like:
> +
> + slt a1,a0,a1
> + czero.nez a3,a3,a1
> + czero.eqz a1,a2,a1
> + or a0,a1,a3
> + */
> +
> +/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */
> +/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */
> +/* { dg-final { scan-assembler-times "\\s(?:sgt|slt)\\s" 1 } } */
> +/* { dg-final { scan-assembler-times "\\sczero\\.eqz\\s" 1 } } */
> +/* { dg-final { scan-assembler-times "\\sczero\\.nez\\s" 1 } } */
> +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
> +/* { dg-final { scan-assembler-not "\\s(?:bge|bgt|ble|blt)\\s" } } */
> Index: gcc/gcc/testsuite/gcc.target/riscv/movsine-thead.c
> ===================================================================
> --- /dev/null
> +++ gcc/gcc/testsuite/gcc.target/riscv/movsine-thead.c
> @@ -0,0 +1,26 @@
> +/* { dg-do compile } */
> +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
> +/* { dg-options "-march=rv64gc_xtheadcondmov -mtune=thead-c906 -mbranch-cost=2 -fdump-rtl-ce1" { target { rv64 } } } */
> +/* { dg-options "-march=rv32gc_xtheadcondmov -mtune=thead-c906 -mbranch-cost=2 -fdump-rtl-ce1" { target { rv32 } } } */
> +
> +typedef int __attribute__ ((mode (SI))) int_t;
> +
> +int_t
> +movsine (int_t w, int_t x, int_t y, int_t z)
> +{
> + return w != x ? y : z;
> +}
> +
> +/* Expect branchless assembly like:
> +
> + sub a1,a0,a1
> + th.mveqz a2,a3,a1
> + mv a0,a2
> + */
> +
> +/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */
> +/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */
> +/* { dg-final { scan-assembler-times "\\ssub\\s" 1 } } */
> +/* { dg-final { scan-assembler-times "\\s(?:th\\.mveqz|th\\.mvnez)\\s" 1 } } */
> +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
> +/* { dg-final { scan-assembler-not "\\s(?:beq|bne)\\s" } } */
On Sun, 19 Nov 2023, Kito Cheng wrote:
> Just one minor comment, I think we don't really need to check rv64 or
> rv32 for those compiled without any header file test, but I am fine
> with that.
We need to set `-march=' differently depending on whether verifying for
rv64 or rv32, and then we don't want to limit testing to one of these
subarchitectures only, because different code paths are covered in some
cases depending on the machine word size. This is especially clear with
the cases that succeed for rv64 and currently fail for rv32, but it is
also true elsewhere, e.g. where a SImode intermediate SCC result is
widened to DImode with rv64, but kept intact with rv64.
Maciej
===================================================================
@@ -0,0 +1,26 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target rv64 } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
+/* { dg-options "-march=rv64gc_xtheadcondmov -mtune=thead-c906 -mbranch-cost=2 -fdump-rtl-ce1" } */
+
+typedef int __attribute__ ((mode (DI))) int_t;
+
+int_t
+movdieq (int_t w, int_t x, int_t y, int_t z)
+{
+ return w == x ? y : z;
+}
+
+/* Expect branchless assembly like:
+
+ sub a0,a0,a1
+ th.mvnez a2,a3,a0
+ mv a0,a2
+ */
+
+/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */
+/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */
+/* { dg-final { scan-assembler-times "\\ssub\\s" 1 } } */
+/* { dg-final { scan-assembler-times "\\s(?:th\\.mveqz|th\\.mvnez)\\s" 1 } } */
+/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
+/* { dg-final { scan-assembler-not "\\s(?:beq|bne)\\s" } } */
===================================================================
@@ -0,0 +1,28 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target rv64 } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
+/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=4 -fdump-rtl-ce1" } */
+
+typedef int __attribute__ ((mode (DI))) int_t;
+
+int_t
+movdige (int_t w, int_t x, int_t y, int_t z)
+{
+ return w >= x ? y : z;
+}
+
+/* Expect branchless assembly like:
+
+ slt a1,a0,a1
+ vt.maskc a3,a3,a1
+ vt.maskcn a1,a2,a1
+ or a0,a1,a3
+ */
+
+/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */
+/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */
+/* { dg-final { scan-assembler-times "\\s(?:sgt|slt)\\s" 1 } } */
+/* { dg-final { scan-assembler-times "\\svt\\.maskc\\s" 1 } } */
+/* { dg-final { scan-assembler-times "\\svt\\.maskcn\\s" 1 } } */
+/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
+/* { dg-final { scan-assembler-not "\\s(?:bge|bgt|ble|blt)\\s" } } */
===================================================================
@@ -0,0 +1,28 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target rv64 } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
+/* { dg-options "-march=rv64gc_zicond -mtune=rocket -mbranch-cost=4 -fdump-rtl-ce1" } */
+
+typedef int __attribute__ ((mode (DI))) int_t;
+
+int_t
+movdige (int_t w, int_t x, int_t y, int_t z)
+{
+ return w >= x ? y : z;
+}
+
+/* Expect branchless assembly like:
+
+ slt a1,a0,a1
+ czero.eqz a3,a3,a1
+ czero.nez a1,a2,a1
+ or a0,a1,a3
+ */
+
+/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */
+/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */
+/* { dg-final { scan-assembler-times "\\s(?:sgt|slt)\\s" 1 } } */
+/* { dg-final { scan-assembler-times "\\sczero\\.eqz\\s" 1 } } */
+/* { dg-final { scan-assembler-times "\\sczero\\.nez\\s" 1 } } */
+/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
+/* { dg-final { scan-assembler-not "\\s(?:bge|bgt|ble|blt)\\s" } } */
===================================================================
@@ -0,0 +1,28 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target rv64 } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
+/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=4 -fdump-rtl-ce1" } */
+
+typedef unsigned int __attribute__ ((mode (DI))) int_t;
+
+int_t
+movdigeu (int_t w, int_t x, int_t y, int_t z)
+{
+ return w >= x ? y : z;
+}
+
+/* Expect branchless assembly like:
+
+ sltu a1,a0,a1
+ vt.maskc a3,a3,a1
+ vt.maskcn a1,a2,a1
+ or a0,a1,a3
+ */
+
+/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */
+/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */
+/* { dg-final { scan-assembler-times "\\s(?:sgtu|sltu)\\s" 1 } } */
+/* { dg-final { scan-assembler-times "\\svt\\.maskc\\s" 1 } } */
+/* { dg-final { scan-assembler-times "\\svt\\.maskcn\\s" 1 } } */
+/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
+/* { dg-final { scan-assembler-not "\\s(?:bgeu|bgtu|bleu|bltu)\\s" } } */
===================================================================
@@ -0,0 +1,28 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target rv64 } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
+/* { dg-options "-march=rv64gc_zicond -mtune=rocket -mbranch-cost=4 -fdump-rtl-ce1" } */
+
+typedef unsigned int __attribute__ ((mode (DI))) int_t;
+
+int_t
+movdigeu (int_t w, int_t x, int_t y, int_t z)
+{
+ return w >= x ? y : z;
+}
+
+/* Expect branchless assembly like:
+
+ sltu a1,a0,a1
+ czero.eqz a3,a3,a1
+ czero.nez a1,a2,a1
+ or a0,a1,a3
+ */
+
+/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */
+/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */
+/* { dg-final { scan-assembler-times "\\s(?:sgtu|sltu)\\s" 1 } } */
+/* { dg-final { scan-assembler-times "\\sczero\\.eqz\\s" 1 } } */
+/* { dg-final { scan-assembler-times "\\sczero\\.nez\\s" 1 } } */
+/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
+/* { dg-final { scan-assembler-not "\\s(?:bgeu|bgtu|bleu|bltu)\\s" } } */
===================================================================
@@ -0,0 +1,28 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target rv64 } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
+/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=4 -fdump-rtl-ce1" } */
+
+typedef int __attribute__ ((mode (DI))) int_t;
+
+int_t
+movdigt (int_t w, int_t x, int_t y, int_t z)
+{
+ return w > x ? y : z;
+}
+
+/* Expect branchless assembly like:
+
+ sgt a1,a0,a1
+ vt.maskcn a3,a3,a1
+ vt.maskc a1,a2,a1
+ or a0,a1,a3
+ */
+
+/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */
+/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */
+/* { dg-final { scan-assembler-times "\\s(?:sgt|slt)\\s" 1 } } */
+/* { dg-final { scan-assembler-times "\\svt\\.maskc\\s" 1 } } */
+/* { dg-final { scan-assembler-times "\\svt\\.maskcn\\s" 1 } } */
+/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
+/* { dg-final { scan-assembler-not "\\s(?:bge|bgt|ble|blt)\\s" } } */
===================================================================
@@ -0,0 +1,28 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target rv64 } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
+/* { dg-options "-march=rv64gc_zicond -mtune=rocket -mbranch-cost=4 -fdump-rtl-ce1" } */
+
+typedef int __attribute__ ((mode (DI))) int_t;
+
+int_t
+movdigt (int_t w, int_t x, int_t y, int_t z)
+{
+ return w > x ? y : z;
+}
+
+/* Expect branchless assembly like:
+
+ sgt a1,a0,a1
+ czero.nez a3,a3,a1
+ czero.eqz a1,a2,a1
+ or a0,a1,a3
+ */
+
+/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */
+/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */
+/* { dg-final { scan-assembler-times "\\s(?:sgt|slt)\\s" 1 } } */
+/* { dg-final { scan-assembler-times "\\sczero\\.eqz\\s" 1 } } */
+/* { dg-final { scan-assembler-times "\\sczero\\.nez\\s" 1 } } */
+/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
+/* { dg-final { scan-assembler-not "\\s(?:bge|bgt|ble|blt)\\s" } } */
===================================================================
@@ -0,0 +1,28 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target rv64 } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
+/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=4 -fdump-rtl-ce1" } */
+
+typedef int __attribute__ ((mode (DI))) int_t;
+
+int_t
+movdile (int_t w, int_t x, int_t y, int_t z)
+{
+ return w <= x ? y : z;
+}
+
+/* Expect branchless assembly like:
+
+ sgt a1,a0,a1
+ vt.maskc a3,a3,a1
+ vt.maskcn a1,a2,a1
+ or a0,a1,a3
+ */
+
+/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */
+/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */
+/* { dg-final { scan-assembler-times "\\s(?:sgt|slt)\\s" 1 } } */
+/* { dg-final { scan-assembler-times "\\svt\\.maskc\\s" 1 } } */
+/* { dg-final { scan-assembler-times "\\svt\\.maskcn\\s" 1 } } */
+/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
+/* { dg-final { scan-assembler-not "\\s(?:bge|bgt|ble|blt)\\s" } } */
===================================================================
@@ -0,0 +1,28 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target rv64 } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
+/* { dg-options "-march=rv64gc_zicond -mtune=rocket -mbranch-cost=4 -fdump-rtl-ce1" } */
+
+typedef int __attribute__ ((mode (DI))) int_t;
+
+int_t
+movdile (int_t w, int_t x, int_t y, int_t z)
+{
+ return w <= x ? y : z;
+}
+
+/* Expect branchless assembly like:
+
+ sgt a1,a0,a1
+ czero.eqz a3,a3,a1
+ czero.nez a1,a2,a1
+ or a0,a1,a3
+ */
+
+/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */
+/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */
+/* { dg-final { scan-assembler-times "\\s(?:sgt|slt)\\s" 1 } } */
+/* { dg-final { scan-assembler-times "\\sczero\\.eqz\\s" 1 } } */
+/* { dg-final { scan-assembler-times "\\sczero\\.nez\\s" 1 } } */
+/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
+/* { dg-final { scan-assembler-not "\\s(?:bge|bgt|ble|blt)\\s" } } */
===================================================================
@@ -0,0 +1,28 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target rv64 } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
+/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=4 -fdump-rtl-ce1" } */
+
+typedef unsigned int __attribute__ ((mode (DI))) int_t;
+
+int_t
+movdileu (int_t w, int_t x, int_t y, int_t z)
+{
+ return w <= x ? y : z;
+}
+
+/* Expect branchless assembly like:
+
+ sgtu a1,a0,a1
+ vt.maskc a3,a3,a1
+ vt.maskcn a1,a2,a1
+ or a0,a1,a3
+ */
+
+/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */
+/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */
+/* { dg-final { scan-assembler-times "\\s(?:sgtu|sltu)\\s" 1 } } */
+/* { dg-final { scan-assembler-times "\\svt\\.maskc\\s" 1 } } */
+/* { dg-final { scan-assembler-times "\\svt\\.maskcn\\s" 1 } } */
+/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
+/* { dg-final { scan-assembler-not "\\s(?:bgeu|bgtu|bleu|bltu)\\s" } } */
===================================================================
@@ -0,0 +1,28 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target rv64 } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
+/* { dg-options "-march=rv64gc_zicond -mtune=rocket -mbranch-cost=4 -fdump-rtl-ce1" } */
+
+typedef unsigned int __attribute__ ((mode (DI))) int_t;
+
+int_t
+movdileu (int_t w, int_t x, int_t y, int_t z)
+{
+ return w <= x ? y : z;
+}
+
+/* Expect branchless assembly like:
+
+ sgtu a1,a0,a1
+ czero.eqz a3,a3,a1
+ czero.nez a1,a2,a1
+ or a0,a1,a3
+ */
+
+/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */
+/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */
+/* { dg-final { scan-assembler-times "\\s(?:sgtu|sltu)\\s" 1 } } */
+/* { dg-final { scan-assembler-times "\\sczero\\.eqz\\s" 1 } } */
+/* { dg-final { scan-assembler-times "\\sczero\\.nez\\s" 1 } } */
+/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
+/* { dg-final { scan-assembler-not "\\s(?:bgeu|bgtu|bleu|bltu)\\s" } } */
===================================================================
@@ -0,0 +1,28 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target rv64 } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
+/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=4 -fdump-rtl-ce1" } */
+
+typedef int __attribute__ ((mode (DI))) int_t;
+
+int_t
+movdilt (int_t w, int_t x, int_t y, int_t z)
+{
+ return w < x ? y : z;
+}
+
+/* Expect branchless assembly like:
+
+ slt a1,a0,a1
+ vt.maskcn a3,a3,a1
+ vt.maskc a1,a2,a1
+ or a0,a1,a3
+ */
+
+/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */
+/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */
+/* { dg-final { scan-assembler-times "\\s(?:sgt|slt)\\s" 1 } } */
+/* { dg-final { scan-assembler-times "\\svt\\.maskc\\s" 1 } } */
+/* { dg-final { scan-assembler-times "\\svt\\.maskcn\\s" 1 } } */
+/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
+/* { dg-final { scan-assembler-not "\\s(?:bge|bgt|ble|blt)\\s" } } */
===================================================================
@@ -0,0 +1,28 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target rv64 } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
+/* { dg-options "-march=rv64gc_zicond -mtune=rocket -mbranch-cost=4 -fdump-rtl-ce1" } */
+
+typedef int __attribute__ ((mode (DI))) int_t;
+
+int_t
+movdilt (int_t w, int_t x, int_t y, int_t z)
+{
+ return w < x ? y : z;
+}
+
+/* Expect branchless assembly like:
+
+ slt a1,a0,a1
+ czero.nez a3,a3,a1
+ czero.eqz a1,a2,a1
+ or a0,a1,a3
+ */
+
+/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */
+/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */
+/* { dg-final { scan-assembler-times "\\s(?:sgt|slt)\\s" 1 } } */
+/* { dg-final { scan-assembler-times "\\sczero\\.eqz\\s" 1 } } */
+/* { dg-final { scan-assembler-times "\\sczero\\.nez\\s" 1 } } */
+/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
+/* { dg-final { scan-assembler-not "\\s(?:bge|bgt|ble|blt)\\s" } } */
===================================================================
@@ -0,0 +1,26 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target rv64 } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
+/* { dg-options "-march=rv64gc_xtheadcondmov -mtune=thead-c906 -mbranch-cost=2 -fdump-rtl-ce1" } */
+
+typedef int __attribute__ ((mode (DI))) int_t;
+
+int_t
+movdine (int_t w, int_t x, int_t y, int_t z)
+{
+ return w != x ? y : z;
+}
+
+/* Expect branchless assembly like:
+
+ sub a1,a0,a1
+ th.mveqz a2,a3,a1
+ mv a0,a2
+ */
+
+/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */
+/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */
+/* { dg-final { scan-assembler-times "\\ssub\\s" 1 } } */
+/* { dg-final { scan-assembler-times "\\s(?:th\\.mveqz|th\\.mvnez)\\s" 1 } } */
+/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
+/* { dg-final { scan-assembler-not "\\s(?:beq|bne)\\s" } } */
===================================================================
@@ -0,0 +1,26 @@
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
+/* { dg-options "-march=rv64gc_xtheadcondmov -mtune=thead-c906 -mbranch-cost=2 -fdump-rtl-ce1" { target { rv64 } } } */
+/* { dg-options "-march=rv32gc_xtheadcondmov -mtune=thead-c906 -mbranch-cost=2 -fdump-rtl-ce1" { target { rv32 } } } */
+
+typedef int __attribute__ ((mode (SI))) int_t;
+
+int_t
+movsieq (int_t w, int_t x, int_t y, int_t z)
+{
+ return w == x ? y : z;
+}
+
+/* Expect branchless assembly like:
+
+ sub a0,a0,a1
+ th.mvnez a2,a3,a0
+ mv a0,a2
+ */
+
+/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */
+/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */
+/* { dg-final { scan-assembler-times "\\ssub\\s" 1 } } */
+/* { dg-final { scan-assembler-times "\\s(?:th\\.mveqz|th\\.mvnez)\\s" 1 } } */
+/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
+/* { dg-final { scan-assembler-not "\\s(?:beq|bne)\\s" } } */
===================================================================
@@ -0,0 +1,28 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target rv64 } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
+/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=4 -fdump-rtl-ce1" } */
+
+typedef int __attribute__ ((mode (SI))) int_t;
+
+int_t
+movsige (int_t w, int_t x, int_t y, int_t z)
+{
+ return w >= x ? y : z;
+}
+
+/* Expect branchless assembly like:
+
+ slt a1,a0,a1
+ vt.maskc a3,a3,a1
+ vt.maskcn a1,a2,a1
+ or a0,a1,a3
+ */
+
+/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */
+/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */
+/* { dg-final { scan-assembler-times "\\s(?:sgt|slt)\\s" 1 } } */
+/* { dg-final { scan-assembler-times "\\svt\\.maskc\\s" 1 } } */
+/* { dg-final { scan-assembler-times "\\svt\\.maskcn\\s" 1 } } */
+/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
+/* { dg-final { scan-assembler-not "\\s(?:bge|bgt|ble|blt)\\s" } } */
===================================================================
@@ -0,0 +1,28 @@
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
+/* { dg-options "-march=rv64gc_zicond -mtune=rocket -mbranch-cost=4 -fdump-rtl-ce1" { target { rv64 } } } */
+/* { dg-options "-march=rv32gc_zicond -mtune=rocket -mbranch-cost=4 -fdump-rtl-ce1" { target { rv32 } } } */
+
+typedef int __attribute__ ((mode (SI))) int_t;
+
+int_t
+movsige (int_t w, int_t x, int_t y, int_t z)
+{
+ return w >= x ? y : z;
+}
+
+/* Expect branchless assembly like:
+
+ slt a1,a0,a1
+ czero.eqz a3,a3,a1
+ czero.nez a1,a2,a1
+ or a0,a1,a3
+ */
+
+/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */
+/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */
+/* { dg-final { scan-assembler-times "\\s(?:sgt|slt)\\s" 1 } } */
+/* { dg-final { scan-assembler-times "\\sczero\\.eqz\\s" 1 } } */
+/* { dg-final { scan-assembler-times "\\sczero\\.nez\\s" 1 } } */
+/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
+/* { dg-final { scan-assembler-not "\\s(?:bge|bgt|ble|blt)\\s" } } */
===================================================================
@@ -0,0 +1,28 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target rv64 } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
+/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=4 -fdump-rtl-ce1" } */
+
+typedef unsigned int __attribute__ ((mode (SI))) int_t;
+
+int_t
+movsigeu (int_t w, int_t x, int_t y, int_t z)
+{
+ return w >= x ? y : z;
+}
+
+/* Expect branchless assembly like:
+
+ sltu a1,a0,a1
+ vt.maskc a3,a3,a1
+ vt.maskcn a1,a2,a1
+ or a0,a1,a3
+ */
+
+/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */
+/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */
+/* { dg-final { scan-assembler-times "\\s(?:sgtu|sltu)\\s" 1 } } */
+/* { dg-final { scan-assembler-times "\\svt\\.maskc\\s" 1 } } */
+/* { dg-final { scan-assembler-times "\\svt\\.maskcn\\s" 1 } } */
+/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
+/* { dg-final { scan-assembler-not "\\s(?:bgeu|bgtu|bleu|bltu)\\s" } } */
===================================================================
@@ -0,0 +1,28 @@
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
+/* { dg-options "-march=rv64gc_zicond -mtune=rocket -mbranch-cost=4 -fdump-rtl-ce1" { target { rv64 } } } */
+/* { dg-options "-march=rv32gc_zicond -mtune=rocket -mbranch-cost=4 -fdump-rtl-ce1" { target { rv32 } } } */
+
+typedef unsigned int __attribute__ ((mode (SI))) int_t;
+
+int_t
+movsigeu (int_t w, int_t x, int_t y, int_t z)
+{
+ return w >= x ? y : z;
+}
+
+/* Expect branchless assembly like:
+
+ sltu a1,a0,a1
+ czero.eqz a3,a3,a1
+ czero.nez a1,a2,a1
+ or a0,a1,a3
+ */
+
+/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */
+/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */
+/* { dg-final { scan-assembler-times "\\s(?:sgtu|sltu)\\s" 1 } } */
+/* { dg-final { scan-assembler-times "\\sczero\\.eqz\\s" 1 } } */
+/* { dg-final { scan-assembler-times "\\sczero\\.nez\\s" 1 } } */
+/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
+/* { dg-final { scan-assembler-not "\\s(?:bgeu|bgtu|bleu|bltu)\\s" } } */
===================================================================
@@ -0,0 +1,28 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target rv64 } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
+/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=4 -fdump-rtl-ce1" } */
+
+typedef int __attribute__ ((mode (SI))) int_t;
+
+int_t
+movsigt (int_t w, int_t x, int_t y, int_t z)
+{
+ return w > x ? y : z;
+}
+
+/* Expect branchless assembly like:
+
+ sgt a1,a0,a1
+ vt.maskcn a3,a3,a1
+ vt.maskc a1,a2,a1
+ or a0,a1,a3
+ */
+
+/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */
+/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */
+/* { dg-final { scan-assembler-times "\\s(?:sgt|slt)\\s" 1 } } */
+/* { dg-final { scan-assembler-times "\\svt\\.maskc\\s" 1 } } */
+/* { dg-final { scan-assembler-times "\\svt\\.maskcn\\s" 1 } } */
+/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
+/* { dg-final { scan-assembler-not "\\s(?:bge|bgt|ble|blt)\\s" } } */
===================================================================
@@ -0,0 +1,28 @@
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
+/* { dg-options "-march=rv64gc_zicond -mtune=rocket -mbranch-cost=4 -fdump-rtl-ce1" { target { rv64 } } } */
+/* { dg-options "-march=rv32gc_zicond -mtune=rocket -mbranch-cost=4 -fdump-rtl-ce1" { target { rv32 } } } */
+
+typedef int __attribute__ ((mode (SI))) int_t;
+
+int_t
+movsigt (int_t w, int_t x, int_t y, int_t z)
+{
+ return w > x ? y : z;
+}
+
+/* Expect branchless assembly like:
+
+ sgt a1,a0,a1
+ czero.nez a3,a3,a1
+ czero.eqz a1,a2,a1
+ or a0,a1,a3
+ */
+
+/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */
+/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */
+/* { dg-final { scan-assembler-times "\\s(?:sgt|slt)\\s" 1 } } */
+/* { dg-final { scan-assembler-times "\\sczero\\.eqz\\s" 1 } } */
+/* { dg-final { scan-assembler-times "\\sczero\\.nez\\s" 1 } } */
+/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
+/* { dg-final { scan-assembler-not "\\s(?:bge|bgt|ble|blt)\\s" } } */
===================================================================
@@ -0,0 +1,28 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target rv64 } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
+/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=4 -fdump-rtl-ce1" } */
+
+typedef int __attribute__ ((mode (SI))) int_t;
+
+int_t
+movsile (int_t w, int_t x, int_t y, int_t z)
+{
+ return w <= x ? y : z;
+}
+
+/* Expect branchless assembly like:
+
+ sgt a1,a0,a1
+ vt.maskc a3,a3,a1
+ vt.maskcn a1,a2,a1
+ or a0,a1,a3
+ */
+
+/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */
+/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */
+/* { dg-final { scan-assembler-times "\\s(?:sgt|slt)\\s" 1 } } */
+/* { dg-final { scan-assembler-times "\\svt\\.maskc\\s" 1 } } */
+/* { dg-final { scan-assembler-times "\\svt\\.maskcn\\s" 1 } } */
+/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
+/* { dg-final { scan-assembler-not "\\s(?:bge|bgt|ble|blt)\\s" } } */
===================================================================
@@ -0,0 +1,28 @@
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
+/* { dg-options "-march=rv64gc_zicond -mtune=rocket -mbranch-cost=4 -fdump-rtl-ce1" { target { rv64 } } } */
+/* { dg-options "-march=rv32gc_zicond -mtune=rocket -mbranch-cost=4 -fdump-rtl-ce1" { target { rv32 } } } */
+
+typedef int __attribute__ ((mode (SI))) int_t;
+
+int_t
+movsile (int_t w, int_t x, int_t y, int_t z)
+{
+ return w <= x ? y : z;
+}
+
+/* Expect branchless assembly like:
+
+ sgt a1,a0,a1
+ czero.eqz a3,a3,a1
+ czero.nez a1,a2,a1
+ or a0,a1,a3
+ */
+
+/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */
+/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */
+/* { dg-final { scan-assembler-times "\\s(?:sgt|slt)\\s" 1 } } */
+/* { dg-final { scan-assembler-times "\\sczero\\.eqz\\s" 1 } } */
+/* { dg-final { scan-assembler-times "\\sczero\\.nez\\s" 1 } } */
+/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
+/* { dg-final { scan-assembler-not "\\s(?:bge|bgt|ble|blt)\\s" } } */
===================================================================
@@ -0,0 +1,28 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target rv64 } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
+/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=4 -fdump-rtl-ce1" } */
+
+typedef unsigned int __attribute__ ((mode (SI))) int_t;
+
+int_t
+movsileu (int_t w, int_t x, int_t y, int_t z)
+{
+ return w <= x ? y : z;
+}
+
+/* Expect branchless assembly like:
+
+ sgtu a1,a0,a1
+ vt.maskc a3,a3,a1
+ vt.maskcn a1,a2,a1
+ or a0,a1,a3
+ */
+
+/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */
+/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */
+/* { dg-final { scan-assembler-times "\\s(?:sgtu|sltu)\\s" 1 } } */
+/* { dg-final { scan-assembler-times "\\svt\\.maskc\\s" 1 } } */
+/* { dg-final { scan-assembler-times "\\svt\\.maskcn\\s" 1 } } */
+/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
+/* { dg-final { scan-assembler-not "\\s(?:bgeu|bgtu|bleu|bltu)\\s" } } */
===================================================================
@@ -0,0 +1,28 @@
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
+/* { dg-options "-march=rv64gc_zicond -mtune=rocket -mbranch-cost=4 -fdump-rtl-ce1" { target { rv64 } } } */
+/* { dg-options "-march=rv32gc_zicond -mtune=rocket -mbranch-cost=4 -fdump-rtl-ce1" { target { rv32 } } } */
+
+typedef unsigned int __attribute__ ((mode (SI))) int_t;
+
+int_t
+movsileu (int_t w, int_t x, int_t y, int_t z)
+{
+ return w <= x ? y : z;
+}
+
+/* Expect branchless assembly like:
+
+ sgtu a1,a0,a1
+ czero.eqz a3,a3,a1
+ czero.nez a1,a2,a1
+ or a0,a1,a3
+ */
+
+/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */
+/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */
+/* { dg-final { scan-assembler-times "\\s(?:sgtu|sltu)\\s" 1 } } */
+/* { dg-final { scan-assembler-times "\\sczero\\.eqz\\s" 1 } } */
+/* { dg-final { scan-assembler-times "\\sczero\\.nez\\s" 1 } } */
+/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
+/* { dg-final { scan-assembler-not "\\s(?:bgeu|bgtu|bleu|bltu)\\s" } } */
===================================================================
@@ -0,0 +1,28 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target rv64 } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
+/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=4 -fdump-rtl-ce1" } */
+
+typedef int __attribute__ ((mode (SI))) int_t;
+
+int_t
+movsilt (int_t w, int_t x, int_t y, int_t z)
+{
+ return w < x ? y : z;
+}
+
+/* Expect branchless assembly like:
+
+ slt a1,a0,a1
+ vt.maskcn a3,a3,a1
+ vt.maskc a1,a2,a1
+ or a0,a1,a3
+ */
+
+/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */
+/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */
+/* { dg-final { scan-assembler-times "\\s(?:sgt|slt)\\s" 1 } } */
+/* { dg-final { scan-assembler-times "\\svt\\.maskc\\s" 1 } } */
+/* { dg-final { scan-assembler-times "\\svt\\.maskcn\\s" 1 } } */
+/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
+/* { dg-final { scan-assembler-not "\\s(?:bge|bgt|ble|blt)\\s" } } */
===================================================================
@@ -0,0 +1,28 @@
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
+/* { dg-options "-march=rv64gc_zicond -mtune=rocket -mbranch-cost=4 -fdump-rtl-ce1" { target { rv64 } } } */
+/* { dg-options "-march=rv32gc_zicond -mtune=rocket -mbranch-cost=4 -fdump-rtl-ce1" { target { rv32 } } } */
+
+typedef int __attribute__ ((mode (SI))) int_t;
+
+int_t
+movsilt (int_t w, int_t x, int_t y, int_t z)
+{
+ return w < x ? y : z;
+}
+
+/* Expect branchless assembly like:
+
+ slt a1,a0,a1
+ czero.nez a3,a3,a1
+ czero.eqz a1,a2,a1
+ or a0,a1,a3
+ */
+
+/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */
+/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */
+/* { dg-final { scan-assembler-times "\\s(?:sgt|slt)\\s" 1 } } */
+/* { dg-final { scan-assembler-times "\\sczero\\.eqz\\s" 1 } } */
+/* { dg-final { scan-assembler-times "\\sczero\\.nez\\s" 1 } } */
+/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
+/* { dg-final { scan-assembler-not "\\s(?:bge|bgt|ble|blt)\\s" } } */
===================================================================
@@ -0,0 +1,26 @@
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
+/* { dg-options "-march=rv64gc_xtheadcondmov -mtune=thead-c906 -mbranch-cost=2 -fdump-rtl-ce1" { target { rv64 } } } */
+/* { dg-options "-march=rv32gc_xtheadcondmov -mtune=thead-c906 -mbranch-cost=2 -fdump-rtl-ce1" { target { rv32 } } } */
+
+typedef int __attribute__ ((mode (SI))) int_t;
+
+int_t
+movsine (int_t w, int_t x, int_t y, int_t z)
+{
+ return w != x ? y : z;
+}
+
+/* Expect branchless assembly like:
+
+ sub a1,a0,a1
+ th.mveqz a2,a3,a1
+ mv a0,a2
+ */
+
+/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */
+/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */
+/* { dg-final { scan-assembler-times "\\ssub\\s" 1 } } */
+/* { dg-final { scan-assembler-times "\\s(?:th\\.mveqz|th\\.mvnez)\\s" 1 } } */
+/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
+/* { dg-final { scan-assembler-not "\\s(?:beq|bne)\\s" } } */