@@ -181,6 +181,18 @@ struct riscv_arg_info {
/* The offset of the first register used, provided num_fprs is nonzero. */
unsigned int fpr_offset;
+
+ /* The number of vector registers allocated to this argument. */
+ unsigned int num_vrs;
+
+ /* The offset of the first register used, provided num_vrs is nonzero. */
+ unsigned int vr_offset;
+
+ /* The number of mask registers allocated to this argument. */
+ unsigned int num_mrs;
+
+ /* The offset of the first register used, provided num_mrs is nonzero. */
+ unsigned int mr_offset;
};
/* Information about an address described by riscv_address_type.
@@ -3225,11 +3237,13 @@ riscv_get_arg_info (struct riscv_arg_info *info, const CUMULATIVE_ARGS *cum,
unsigned num_bytes, num_words;
unsigned fpr_base = return_p ? FP_RETURN : FP_ARG_FIRST;
unsigned gpr_base = return_p ? GP_RETURN : GP_ARG_FIRST;
+ unsigned vr_base = return_p ? V_RETURN : V_ARG_FIRST;
unsigned alignment = riscv_function_arg_boundary (mode, type);
memset (info, 0, sizeof (*info));
info->gpr_offset = cum->num_gprs;
info->fpr_offset = cum->num_fprs;
+ info->mr_offset = cum->num_mrs;
if (named)
{
@@ -3292,6 +3306,67 @@ riscv_get_arg_info (struct riscv_arg_info *info, const CUMULATIVE_ARGS *cum,
gregno, TYPE_MODE (fields[1].type),
fields[1].offset);
}
+ /* Pass vectors in VRs. For the argument contain scalable vectors,
+ for example: foo (vint8m1_t a), we pass this in VRs to reduce
+ redundant register spills. The maximum vector arg registers is
+ MAX_ARGS_IN_VECTOR_REGISTERS. */
+ if (rvv_mode_p (mode))
+ {
+ /* For return vector register, we use V_RETURN as default. */
+ if (return_p)
+ {
+ if (GET_MODE_CLASS (mode) == MODE_VECTOR_BOOL)
+ return gen_rtx_REG (mode, V_REG_FIRST);
+ else
+ return gen_rtx_REG (mode, vr_base);
+ }
+ /* The first mask register in argument we use is v0, the res of them
+ we use v8,v9,.....etc same as vector registers. */
+ if (GET_MODE_CLASS (mode) == MODE_VECTOR_BOOL)
+ {
+ info->num_mrs = 1;
+
+ if (info->mr_offset + info->num_mrs <= MAX_ARGS_IN_MASK_REGISTERS)
+ return gen_rtx_REG (mode, V_REG_FIRST);
+ }
+ /* The number of vectors to pass in the function arg.
+ When the mode size is less than a full vector, we
+ use 1 vector to pass. */
+ int nvecs;
+ nvecs = known_le (GET_MODE_SIZE (mode), BYTES_PER_RISCV_VECTOR) ? 1 :
+ exact_div (GET_MODE_SIZE (mode), BYTES_PER_RISCV_VECTOR).to_constant ();
+ int align = rvv_regsize (mode);
+ for (int i = 0; i + nvecs <= MAX_ARGS_IN_VECTOR_REGISTERS; i += 1)
+ {
+ if (!cum->used_vrs[i] && (i + 8) % align == 0)
+ {
+ bool find_space = true;
+ int j = 1;
+ for (; j < nvecs; j += 1)
+ {
+ if (cum->used_vrs[i + j])
+ {
+ find_space = false;
+ break;
+ }
+ }
+ if (find_space)
+ {
+ info->num_vrs = nvecs;
+ info->vr_offset = i;
+ return gen_rtx_REG(mode, vr_base + i);
+ }
+ else
+ {
+ /* skip the j num registers which can not be used */
+ i += j;
+ }
+ }
+ }
+ info->num_vrs = 0;
+ info->num_mrs = 0;
+ return NULL_RTX;
+ }
}
/* Work out the size of the argument. */
@@ -3344,6 +3419,15 @@ riscv_function_arg_advance (cumulative_args_t cum_v,
argument on the stack. */
cum->num_fprs = info.fpr_offset + info.num_fprs;
cum->num_gprs = info.gpr_offset + info.num_gprs;
+ if (info.num_vrs > 0)
+ {
+ for (unsigned int i = 0; i < info.num_vrs; i += 1)
+ {
+ /* set current used vector registers */
+ cum->used_vrs[info.vr_offset + i] = true;
+ }
+ }
+ cum->num_mrs = info.mr_offset + info.num_mrs;
}
/* Implement TARGET_ARG_PARTIAL_BYTES. */
@@ -3401,6 +3485,12 @@ riscv_pass_by_reference (cumulative_args_t cum_v, const function_arg_info &arg)
/* Don't pass by reference if we can use a floating-point register. */
riscv_get_arg_info (&info, cum, arg.mode, arg.type, arg.named, false);
if (info.num_fprs)
+ return false;
+ /* Don't pass by reference if we can use a RVV vector register. */
+ if (info.num_vrs)
+ return false;
+ /* Don't pass by reference if we can use a RVV mask register. */
+ if (info.num_mrs)
return false;
}
@@ -22,6 +22,7 @@ along with GCC; see the file COPYING3. If not see
#ifndef GCC_RISCV_H
#define GCC_RISCV_H
+#include <stdbool.h>
#include "config/riscv/riscv-opts.h"
/* Target CPU builtins. */
@@ -620,8 +621,13 @@ enum reg_class
#define GP_RETURN GP_ARG_FIRST
#define FP_RETURN (UNITS_PER_FP_ARG == 0 ? GP_RETURN : FP_ARG_FIRST)
+#define V_RETURN V_ARG_FIRST
#define MAX_ARGS_IN_REGISTERS (riscv_abi == ABI_ILP32E ? 6 : 8)
+/* Follow the calling convention in LLVM,
+ maximum 16 vector registers and 1 mask register in function arg. */
+#define MAX_ARGS_IN_VECTOR_REGISTERS (16)
+#define MAX_ARGS_IN_MASK_REGISTERS (1)
/* Symbolic macros for the first/last argument registers. */
@@ -630,6 +636,8 @@ enum reg_class
#define GP_TEMP_FIRST (GP_REG_FIRST + 5)
#define FP_ARG_FIRST (FP_REG_FIRST + 10)
#define FP_ARG_LAST (FP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
+#define V_ARG_FIRST (V_REG_FIRST + 8)
+#define V_ARG_LAST (V_ARG_FIRST + MAX_ARGS_IN_VECTOR_REGISTERS - 1)
#define CALLEE_SAVED_REG_NUMBER(REGNO) \
((REGNO) >= 8 && (REGNO) <= 9 ? (REGNO) - 8 : \
@@ -657,6 +665,12 @@ typedef struct {
/* Number of floating-point registers used so far, likewise. */
unsigned int num_fprs;
+
+ /* The used state of args in vectors, 1 for used by prev arg, initial to 0 */
+ bool used_vrs[MAX_ARGS_IN_VECTOR_REGISTERS];
+
+ /* Number of mask registers used so far, up to MAX_ARGS_IN_MASK_REGISTERS. */
+ unsigned int num_mrs;
} CUMULATIVE_ARGS;
/* Initialize a variable CUM of type CUMULATIVE_ARGS
new file mode 100644
@@ -0,0 +1,46 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-O3" } */
+
+#include <stddef.h>
+#include <riscv_vector.h>
+
+void
+test (
+ vint8mf2_t a, vint8m4_t c, vint8m4_t d,vint8m2_t e, vint8m2_t b,
+ vint8m1_t f,vint8m1_t f2, vint8m1_t f3, vint8m1_t f4, vint8m2_t g, vint8m2_t h,
+ vbool16_t m1, vbool4_t m2,
+ int8_t *a1, int8_t *b1, int8_t *c1,
+ size_t vl)
+{
+ /* f4 => a0, g => a1, h => a2, m2 => a3,
+ a1 => a4, b1 => a5, c1 => a6, vl => a7
+
+ m1 => v0
+ a => v8, c => v12, d => v16, e => v10,
+ b => v20, f => v9, f2 => v22, f3 => v23 */
+
+ vse8_v_i8mf2_m(m1, a1, a, vl);
+
+ vse8_v_i8m2_m(m2, b1, b, vl);
+
+ vse8_v_i8m4(c1, c, vl);
+ vse8_v_i8m4(c1, d, vl);
+
+ vse8_v_i8m2(c1, e, vl);
+
+ vse8_v_i8m1(c1, f, vl);
+ vse8_v_i8m1(c1, f2, vl);
+ vse8_v_i8m1(c1, f3, vl);
+ vse8_v_i8m1(c1, f4, vl);
+
+ vse8_v_i8m2(c1, g, vl);
+ vse8_v_i8m2(c1, h, vl);
+}
+/* { dg-final { scan-assembler-times {vse8.v\s+v8,\s*\(a4\),\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vse8.v\s+v20,\s*\(a5\),\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vse8.v\s+v12,\s*\(a6\)} 1 } } */
+/* { dg-final { scan-assembler-times {vse8.v\s+v16,\s*\(a6\)} 1 } } */
+/* { dg-final { scan-assembler-times {vse8.v\s+v10,\s*\(a6\)} 1 } } */
+/* { dg-final { scan-assembler-times {vse8.v\s+v9,\s*\(a6\)} 1 } } */
+/* { dg-final { scan-assembler-times {vse8.v\s+v22,\s*\(a6\)} 1 } } */
+/* { dg-final { scan-assembler-times {vse8.v\s+v23,\s*\(a6\)} 1 } } */
\ No newline at end of file
new file mode 100644
@@ -0,0 +1,47 @@
+# Copyright (C) 2022-2022 Free Software Foundation, Inc.
+
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with GCC; see the file COPYING3. If not see
+# <http://www.gnu.org/licenses/>.
+
+# GCC testsuite that uses the `dg.exp' driver.
+
+# Exit immediately if this isn't a RISC-V target.
+if ![istarget riscv*-*-*] then {
+ return
+}
+
+# Load support procs.
+load_lib gcc-dg.exp
+
+# If a testcase doesn't have special options, use these.
+global DEFAULT_CFLAGS
+if ![info exists DEFAULT_CFLAGS] then {
+ set DEFAULT_CFLAGS "-pedantic-errors -ansi"
+}
+
+set gcc_march "rv64gcv_zfh"
+if [istarget riscv32-*-*] then {
+ set gcc_march "rv32gcv_zfh"
+}
+
+# Initialize `dg'.
+dg-init
+
+# Main loop.
+set CFLAGS "$DEFAULT_CFLAGS -march=$gcc_march -std=gnu11"
+dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.c]] \
+ "" $CFLAGS
+
+# All done.
+dg-finish
\ No newline at end of file