diff mbox series

[09/21] Add misc function intrinsic support

Message ID	20220531085012.269719-10-juzhe.zhong@rivai.ai
State	Committed
Headers	DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org BF53238356AE From: juzhe.zhong@rivai.ai To: gcc-patches@gcc.gnu.org Subject: [PATCH 09/21] Add misc function intrinsic support Date: Tue, 31 May 2022 16:50:00 +0800 Message-Id: <20220531085012.269719-10-juzhe.zhong@rivai.ai> In-Reply-To: <20220531085012.269719-1-juzhe.zhong@rivai.ai> References: <20220531085012.269719-1-juzhe.zhong@rivai.ai> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Feedback-ID: bizesmtp:rivai.ai:qybgforeign:qybgforeign9 Precedence: list Cc: kito.cheng@gmail.com, juzhe.zhong@rivai.ai Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" <gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org>
Series	* Add RVV (RISC-V 'V' Extension) support * \| [00/21] * Add RVV (RISC-V 'V' Extension) support * [01/21] Add RVV modes and support scalable vector [02/21] Add RVV intrinsic framework [03/21] Add RVV datatypes [04/21] Add RVV intrinsic enable #pragma riscv intrinsic "vector" and introduce RVV header "riscv_v… [05/21] Add RVV configuration intrinsic [06/21] Add insert-vsetvl pass [07/21] Add register spilling support [08/21] Add poly manipulation [09/21] Add misc function intrinsic support [11/21] Add calling function support [12/21] Add set get intrinsic support [13/21] Adjust scalable frame and full testcases [15/21] Add integer intrinsics [18/21] Add rest intrinsic support

Commit Message

juzhe.zhong@rivai.ai May 31, 2022, 8:50 a.m. UTC

  From: zhongjuzhe <juzhe.zhong@rivai.ai>

gcc/ChangeLog:

        * config/riscv/predicates.md (vector_any_register_operand): New predicate.
        * config/riscv/riscv-protos.h (riscv_regmode_natural_size): New function.
        * config/riscv/riscv-vector-builtins-functions.cc (get_pred_str): New function.
        (get_operation_str): New function.
        (is_dt_ptr): New function.
        (is_dt_unsigned): New function.
        (is_dt_const): New function.
        (intrinsic_rename): New function.
        (get_dt_t_with_index): New function.
        (misc::assemble_name): New function.
        (misc::get_return_type): New function.
        (misc::get_argument_types): New function.
        (vreinterpret::expand): New function.
        (vlmul_ext::assemble_name): New function.
        (vlmul_ext::expand): New function.
        (vlmul_trunc::assemble_name): New function.
        (vlmul_trunc::expand): New function.
        (vundefined::assemble_name): New function.
        (vundefined::get_argument_types): New function.
        (vundefined::expand): New function.
        * config/riscv/riscv-vector-builtins-functions.def (vreinterpret): New macro definition.
        (vlmul_ext): New macro definition.
        (vlmul_trunc): New macro definition.
        (vundefined): New macro definition.
        * config/riscv/riscv-vector-builtins-functions.h (class misc): New class.
        (class vreinterpret): New class.
        (class vlmul_ext): New class.
        (class vlmul_trunc): New class.
        (class vundefined): New class.
        * config/riscv/riscv-vector-builtins-iterators.def (VCONVERFI): New iterator.
        (VCONVERI): New iterator.
        (VCONVERI2): New iterator.
        (VCONVERI3): New iterator.
        (VCONVERF): New iterator.
        (VSETI): New iterator.
        (VSETF): New iterator.
        (VGETI): New iterator.
        (VGETF): New iterator.
        (VLMULEXT): New iterator.
        (VLMULTRUNC): New iterator.
        * config/riscv/riscv.cc (riscv_hard_regno_mode_ok): Fix register allocation.
        (riscv_class_max_nregs): Fix register allocation.
        (riscv_can_change_mode_class): Add RVV mode can change support.
        (riscv_regmode_natural_size): New function.
        * config/riscv/riscv.h (REGMODE_NATURAL_SIZE): New targethook.
        * config/riscv/vector-iterators.md: New iterators and attributes.
        * config/riscv/vector.md (@vreinterpret<mode>): New pattern.
        (@vlmul_ext<mode>): New pattern.
        (*vlmul_ext<VLMULEXT:mode><V:mode>): New pattern.
        (@vlmul_trunc<mode>): New pattern.
        (@vset<mode>): New pattern.
        (@vget<mode>): New pattern.

gcc/testsuite/ChangeLog:

        * g++.target/riscv/rvv/misc_func.C: New test.
        * g++.target/riscv/rvv/rvv-intrinsic.exp: New test.
        * gcc.target/riscv/rvv/intrinsic/misc_func.c: New test.
        
---
 gcc/config/riscv/predicates.md                |    7 +
 gcc/config/riscv/riscv-protos.h               |    1 +
 .../riscv/riscv-vector-builtins-functions.cc  |  288 ++
 .../riscv/riscv-vector-builtins-functions.def |   22 +
 .../riscv/riscv-vector-builtins-functions.h   |   62 +
 .../riscv/riscv-vector-builtins-iterators.def |  171 +
 gcc/config/riscv/riscv.cc                     |   33 +-
 gcc/config/riscv/riscv.h                      |    2 +
 gcc/config/riscv/vector-iterators.md          |  142 +
 gcc/config/riscv/vector.md                    |  133 +
 .../g++.target/riscv/rvv/misc_func.C          | 2597 +++++++++++++++
 .../g++.target/riscv/rvv/rvv-intrinsic.exp    |   39 +
 .../riscv/rvv/intrinsic/misc_func.c           | 2921 +++++++++++++++++
 13 files changed, 6414 insertions(+), 4 deletions(-)
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/misc_func.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/rvv-intrinsic.exp
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/intrinsic/misc_func.c

diff mbox series

Patch

diff --git a/gcc/config/riscv/predicates.md b/gcc/config/riscv/predicates.md
index 7a101676538..e31c829bf5b 100644
--- a/gcc/config/riscv/predicates.md
+++ b/gcc/config/riscv/predicates.md
@@ -257,6 +257,13 @@ 
   return GET_MODE (op) == Pmode;
 })
 
+;; A special predicate that doesn't match a particular mode.
+(define_special_predicate "vector_any_register_operand"
+  (match_code "reg, subreg")
+{
+  return VECTOR_MODE_P (GET_MODE (op));
+})
+
 (define_predicate "vector_reg_or_const0_operand"
   (ior (match_operand 0 "register_operand")
        (match_test "op == const0_rtx && !VECTOR_MODE_P (GET_MODE (op))")))
diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h
index 2d63fe76930..fd8906e47de 100644
--- a/gcc/config/riscv/riscv-protos.h
+++ b/gcc/config/riscv/riscv-protos.h
@@ -75,6 +75,7 @@  extern bool riscv_store_data_bypass_p (rtx_insn *, rtx_insn *);
 extern rtx riscv_gen_gpr_save_insn (struct riscv_frame_info *);
 extern bool riscv_gpr_save_operation_p (rtx);
 extern rtx riscv_add_offset (rtx, rtx, HOST_WIDE_INT);
+extern poly_uint64 riscv_regmode_natural_size (machine_mode);
 
 /* Routines implemented in riscv-c.cc.  */
 void riscv_cpu_cpp_builtins (cpp_reader *);
diff --git a/gcc/config/riscv/riscv-vector-builtins-functions.cc b/gcc/config/riscv/riscv-vector-builtins-functions.cc
index 0acda8f671e..a25f167f40e 100644
--- a/gcc/config/riscv/riscv-vector-builtins-functions.cc
+++ b/gcc/config/riscv/riscv-vector-builtins-functions.cc
@@ -143,6 +143,131 @@  get_vtype_for_mode (machine_mode mode)
   gcc_unreachable ();
 }
 
+static const char *
+get_pred_str (enum predication_index pred, bool overloaded_p = false)
+{
+  switch (pred)
+    {
+    case PRED_void:
+    case PRED_none:
+      return "";
+
+    case PRED_m:
+      return overloaded_p ? "" : "_m";
+
+    case PRED_tam:
+      return "_tam";
+
+    case PRED_tum:
+      return "_tum";
+
+    case PRED_tu:
+      return "_tu";
+
+    case PRED_ta:
+      return "_ta";
+
+    case PRED_ma:
+      return "_ma";
+
+    case PRED_mu:
+      return "_mu";
+
+    case PRED_tama:
+      return "_tama";
+
+    case PRED_tamu:
+      return "_tamu";
+
+    case PRED_tuma:
+      return "_tuma";
+
+    case PRED_tumu:
+      return "_tumu";
+
+    default:
+      gcc_unreachable ();
+    }
+}
+
+static const char *
+get_operation_str (enum operation_index op)
+{
+  switch (op)
+    {
+    case OP_vv:
+      return "_vv";
+
+    case OP_vx:
+      return "_vx";
+
+    case OP_v:
+      return "_v";
+
+    case OP_wv:
+      return "_wv";
+
+    case OP_wx:
+      return "_wx";
+
+    case OP_x_x_v:
+      return "_x_x_v";
+
+    case OP_vf2:
+      return "_vf2";
+
+    case OP_vf4:
+      return "_vf4";
+
+    case OP_vf8:
+      return "_vf8";
+
+    case OP_vvm:
+      return "_vvm";
+
+    case OP_vxm:
+      return "_vxm";
+
+    case OP_x_x_w:
+      return "_x_x_w";
+
+    case OP_v_v:
+      return "_v_v";
+
+    case OP_v_x:
+      return "_v_x";
+
+    case OP_v_f:
+      return "_v_f";
+
+    case OP_vs:
+      return "_vs";
+
+    case OP_vf:
+      return "_vf";
+
+    case OP_wf:
+      return "_wf";
+
+    case OP_vfm:
+      return "_vfm";
+
+    case OP_vm:
+      return "_vm";
+
+    case OP_mm:
+      return "_mm";
+
+    case OP_m:
+      return "_m";
+
+    default:
+      break;
+    }
+
+  return "";
+}
+
 static const char *
 mode2data_type_str (machine_mode mode, bool u, bool ie)
 {
@@ -300,6 +425,53 @@  get_dt_t (machine_mode mode, bool u, bool ptr = false, bool c = false)
   return type;
 }
 
+/* Helper functions to get datatype of arg. */
+
+static bool
+is_dt_ptr (enum data_type_index dt)
+{
+  return dt == DT_ptr || dt == DT_uptr || dt == DT_c_ptr || dt == DT_c_uptr;
+}
+
+static bool
+is_dt_unsigned (enum data_type_index dt)
+{
+  return dt == DT_unsigned || dt == DT_uptr || dt == DT_c_uptr;
+}
+
+static bool
+is_dt_const (enum data_type_index dt)
+{
+  return dt == DT_c_ptr || dt == DT_c_uptr;
+}
+
+/* Helper functions for builder implementation. */
+static void
+intrinsic_rename (function_instance &instance, int index1, int index2)
+{
+  machine_mode dst_mode = instance.get_arg_pattern ().arg_list[index1];
+  machine_mode src_mode = instance.get_arg_pattern ().arg_list[index2];
+  bool dst_unsigned_p = instance.get_data_type_list ()[index1] == DT_unsigned;
+  bool src_unsigned_p = instance.get_data_type_list ()[index2] == DT_unsigned;
+  const char *name = instance.get_base_name ();
+  const char *op = get_operation_str (instance.get_operation ());
+  const char *src_suffix = mode2data_type_str (src_mode, src_unsigned_p, false);
+  const char *dst_suffix = mode2data_type_str (dst_mode, dst_unsigned_p, false);
+  const char *pred = get_pred_str (instance.get_pred ());
+  snprintf (instance.function_name, NAME_MAXLEN, "%s%s%s%s%s", name, op, src_suffix, dst_suffix, pred);
+}
+
+static tree
+get_dt_t_with_index (const function_instance &instance, int index)
+{
+  machine_mode mode = instance.get_arg_pattern ().arg_list[index];
+  bool unsigned_p = is_dt_unsigned (instance.get_data_type_list ()[index]);
+  bool ptr_p = is_dt_ptr (instance.get_data_type_list ()[index]);
+  bool c_p = is_dt_const (instance.get_data_type_list ()[index]);
+  return get_dt_t (mode, unsigned_p, ptr_p, c_p);
+}
+
+
 /* Return true if the function has no return value.  */
 static bool
 function_returns_void_p (tree fndecl)
@@ -1222,6 +1394,122 @@  vsetvlmax::expand (const function_instance &instance, tree exp, rtx target) cons
                                 !function_returns_void_p (fndecl));
 }
 
+/* A function implementation for Miscellaneous functions.  */
+char *
+misc::assemble_name (function_instance &instance)
+{
+  machine_mode mode = instance.get_arg_pattern ().arg_list[0];
+  bool unsigned_p = instance.get_data_type_list ()[0] == DT_unsigned;
+  intrinsic_rename (instance, 0, 1);
+  append_name (instance.get_base_name ());
+  append_name (mode2data_type_str (mode, unsigned_p, false));
+  return finish_name ();
+}
+
+tree
+misc::get_return_type (const function_instance &instance) const
+{
+  return get_dt_t_with_index (instance, 0);
+}
+
+void
+misc::get_argument_types (const function_instance &instance,
+                          vec<tree> &argument_types) const
+{
+  argument_types.quick_push (get_dt_t_with_index (instance, 1));
+}
+
+/* A function implementation for vreinterpret functions.  */
+rtx
+vreinterpret::expand (const function_instance &instance, tree exp, rtx target) const
+{
+  enum insn_code icode = code_for_vreinterpret (instance.get_arg_pattern ().arg_list[0]);
+  return expand_builtin_insn (icode, exp, target, instance);
+}
+
+/* A function implementation for vlmul_ext functions.  */
+char *
+vlmul_ext::assemble_name (function_instance &instance)
+{
+  machine_mode tmode = instance.get_arg_pattern ().arg_list[0];
+  machine_mode smode = instance.get_arg_pattern ().arg_list[1];
+  if (GET_MODE_INNER (tmode) != GET_MODE_INNER (smode))
+    return nullptr;
+
+  if (tmode == smode)
+    return nullptr;
+  
+  if (known_lt (GET_MODE_SIZE (tmode), GET_MODE_SIZE (smode)))
+    return nullptr;
+
+  bool unsigned_p = instance.get_data_type_list ()[0] == DT_unsigned;
+  intrinsic_rename (instance, 0, 1);
+  append_name (instance.get_base_name ());
+  append_name (mode2data_type_str (tmode, unsigned_p, false));
+  return finish_name ();
+}
+
+rtx
+vlmul_ext::expand (const function_instance &instance, tree exp, rtx target) const
+{
+  enum insn_code icode = code_for_vlmul_ext (instance.get_arg_pattern ().arg_list[0]);
+  return expand_builtin_insn (icode, exp, target, instance);
+}
+
+/* A function implementation for vlmul_trunc functions.  */
+char *
+vlmul_trunc::assemble_name (function_instance &instance)
+{
+  machine_mode tmode = instance.get_arg_pattern ().arg_list[0];
+  machine_mode smode = instance.get_arg_pattern ().arg_list[1];
+  if (GET_MODE_INNER (tmode) != GET_MODE_INNER (smode))
+    return nullptr;
+
+  if (tmode == smode)
+    return nullptr;
+  
+  if (known_gt (GET_MODE_SIZE (tmode), GET_MODE_SIZE (smode)))
+    return nullptr;
+
+  bool unsigned_p = instance.get_data_type_list ()[0] == DT_unsigned;
+  intrinsic_rename (instance, 0, 1);
+  append_name (instance.get_base_name ());
+  append_name (mode2data_type_str (tmode, unsigned_p, false));
+  return finish_name ();
+}
+
+rtx
+vlmul_trunc::expand (const function_instance &instance, tree exp, rtx target) const
+{
+  enum insn_code icode = code_for_vlmul_trunc (instance.get_arg_pattern ().arg_list[0]);
+  return expand_builtin_insn (icode, exp, target, instance);
+}
+
+/* A function implementation for vundefined functions.  */
+char *
+vundefined::assemble_name (function_instance &instance)
+{
+  const char *name = instance.get_base_name ();
+  machine_mode mode = instance.get_arg_pattern ().arg_list[0];
+  bool unsigned_p = instance.get_data_type_list ()[0] == DT_unsigned;
+  const char *dt = mode2data_type_str (mode, unsigned_p, false);
+  snprintf (instance.function_name, NAME_MAXLEN, "%s%s", name, dt);
+  return nullptr;
+}
+
+void
+vundefined::get_argument_types (const function_instance &,
+                          vec<tree> &) const
+{
+}
+
+rtx
+vundefined::expand (const function_instance &, tree, rtx target) const
+{
+  emit_clobber (copy_rtx (target));
+  return target;
+}
+
 } // end namespace riscv_vector
 
 using namespace riscv_vector;
diff --git a/gcc/config/riscv/riscv-vector-builtins-functions.def b/gcc/config/riscv/riscv-vector-builtins-functions.def
index 666e8503d81..86130e02381 100644
--- a/gcc/config/riscv/riscv-vector-builtins-functions.def
+++ b/gcc/config/riscv/riscv-vector-builtins-functions.def
@@ -34,6 +34,28 @@  along with GCC; see the file COPYING3. If not see
 /* 6. Configuration-Setting Instructions. */
 DEF_RVV_FUNCTION(vsetvl, vsetvl, (1, VITER(VI, signed)), PAT_none, PRED_none, OP_none)
 DEF_RVV_FUNCTION(vsetvlmax, vsetvlmax, (1, VITER(VI, signed)), PAT_none, PRED_none, OP_none)
+/* Helper misc intrinsics for software programmer. */
+DEF_RVV_FUNCTION(vreinterpret, vreinterpret, (2, VITER(VI, unsigned), VATTR(0, VI, signed)), PAT_none, PRED_none, OP_v)
+DEF_RVV_FUNCTION(vreinterpret, vreinterpret, (2, VITER(VI, signed), VATTR(0, VI, unsigned)), PAT_none, PRED_none, OP_v)
+DEF_RVV_FUNCTION(vreinterpret, vreinterpret, (2, VATTR(1, VCONVERFI, signed), VITER(VCONVERF, signed)), PAT_none, PRED_none, OP_v)
+DEF_RVV_FUNCTION(vreinterpret, vreinterpret, (2, VATTR(1, VCONVERFI, unsigned), VITER(VCONVERF, signed)), PAT_none, PRED_none, OP_v)
+DEF_RVV_FUNCTION(vreinterpret, vreinterpret, (2, VITER(VCONVERF, signed), VATTR(0, VCONVERFI, signed)), PAT_none, PRED_none, OP_v)
+DEF_RVV_FUNCTION(vreinterpret, vreinterpret, (2, VITER(VCONVERF, signed), VATTR(0, VCONVERFI, unsigned)), PAT_none, PRED_none, OP_v)
+DEF_RVV_FUNCTION(vreinterpret, vreinterpret, (2, VITER(VCONVERI, signed), VATTR(0, VCONVERI, signed)), PAT_none, PRED_none, OP_v)
+DEF_RVV_FUNCTION(vreinterpret, vreinterpret, (2, VITER(VCONVERI, unsigned), VATTR(0, VCONVERI, unsigned)), PAT_none, PRED_none, OP_v)
+DEF_RVV_FUNCTION(vreinterpret, vreinterpret, (2, VITER(VCONVERI2, signed), VATTR(0, VCONVERI2, signed)), PAT_none, PRED_none, OP_v)
+DEF_RVV_FUNCTION(vreinterpret, vreinterpret, (2, VITER(VCONVERI2, unsigned), VATTR(0, VCONVERI2, unsigned)), PAT_none, PRED_none, OP_v)
+DEF_RVV_FUNCTION(vreinterpret, vreinterpret, (2, VITER(VCONVERI3, signed), VATTR(0, VCONVERI3, signed)), PAT_none, PRED_none, OP_v)
+DEF_RVV_FUNCTION(vreinterpret, vreinterpret, (2, VITER(VCONVERI3, unsigned), VATTR(0, VCONVERI3, unsigned)), PAT_none, PRED_none, OP_v)
+DEF_RVV_FUNCTION(vlmul_ext, vlmul_ext, (2, VITER(VLMULEXT, signed), VITER(VI, signed)), PAT_none, PRED_none, OP_v)
+DEF_RVV_FUNCTION(vlmul_ext, vlmul_ext, (2, VITER(VLMULEXT, unsigned), VITER(VI, unsigned)), PAT_none, PRED_none, OP_v)
+DEF_RVV_FUNCTION(vlmul_ext, vlmul_ext, (2, VITER(VLMULEXT, signed), VITER(VF, signed)), PAT_none, PRED_none, OP_v)
+DEF_RVV_FUNCTION(vlmul_trunc, vlmul_trunc, (2, VITER(VLMULTRUNC, signed), VITER(VI, signed)), PAT_none, PRED_none, OP_v)
+DEF_RVV_FUNCTION(vlmul_trunc, vlmul_trunc, (2, VITER(VLMULTRUNC, unsigned), VITER(VI, unsigned)), PAT_none, PRED_none, OP_v)
+DEF_RVV_FUNCTION(vlmul_trunc, vlmul_trunc, (2, VITER(VLMULTRUNC, signed), VITER(VF, signed)), PAT_none, PRED_none, OP_v)
+DEF_RVV_FUNCTION(vundefined, vundefined, (1, VITER(VI, signed)), PAT_none, PRED_none, OP_none)
+DEF_RVV_FUNCTION(vundefined, vundefined, (1, VITER(VI, unsigned)), PAT_none, PRED_none, OP_none)
+DEF_RVV_FUNCTION(vundefined, vundefined, (1, VITER(VF, signed)), PAT_none, PRED_none, OP_none)
 #undef REQUIRED_EXTENSIONS
 #undef DEF_RVV_FUNCTION
 #undef VITER
diff --git a/gcc/config/riscv/riscv-vector-builtins-functions.h b/gcc/config/riscv/riscv-vector-builtins-functions.h
index 9846ded1155..85e4af5f079 100644
--- a/gcc/config/riscv/riscv-vector-builtins-functions.h
+++ b/gcc/config/riscv/riscv-vector-builtins-functions.h
@@ -522,6 +522,68 @@  public:
   virtual rtx expand (const function_instance &, tree, rtx) const override;
 };
 
+/* A function_base for Miscellaneous functions.  */
+class misc : public function_builder
+{
+public:
+  // use the same construction function as the function_builder
+  using function_builder::function_builder;
+
+  virtual char * assemble_name (function_instance &) override;
+  
+  virtual void get_argument_types (const function_instance &, vec<tree> &) const override;
+
+  virtual tree get_return_type (const function_instance &) const override;
+};
+
+/* A function_base for vreinterpret functions.  */
+class vreinterpret : public misc
+{
+public:
+  // use the same construction function as the misc
+  using misc::misc;
+  
+  virtual rtx expand (const function_instance &, tree, rtx) const override;
+};
+
+/* A function_base for vlmul_ext functions.  */
+class vlmul_ext : public misc
+{
+public:
+  // use the same construction function as the misc
+  using misc::misc;
+  
+  virtual char * assemble_name (function_instance &) override;
+  
+  virtual rtx expand (const function_instance &, tree, rtx) const override;
+};
+
+/* A function_base for vlmul_trunc functions.  */
+class vlmul_trunc : public misc
+{
+public:
+  // use the same construction function as the misc
+  using misc::misc;
+  
+  virtual char * assemble_name (function_instance &) override;
+  
+  virtual rtx expand (const function_instance &, tree, rtx) const override;
+};
+
+/* A function_base for vundefined functions.  */
+class vundefined : public misc
+{
+public:
+  // use the same construction function as the misc
+  using misc::misc;
+
+  virtual char * assemble_name (function_instance &) override;
+  
+  virtual void get_argument_types (const function_instance &, vec<tree> &) const override;
+  
+  virtual rtx expand (const function_instance &, tree, rtx) const override;
+};
+
 } // namespace riscv_vector
 
 #endif // end GCC_RISCV_VECTOR_BUILTINS_FUNCTIONS_H
\ No newline at end of file
diff --git a/gcc/config/riscv/riscv-vector-builtins-iterators.def b/gcc/config/riscv/riscv-vector-builtins-iterators.def
index 77a391c7630..8f2ea912804 100644
--- a/gcc/config/riscv/riscv-vector-builtins-iterators.def
+++ b/gcc/config/riscv/riscv-vector-builtins-iterators.def
@@ -118,6 +118,177 @@  DEF_RISCV_ARG_MODE_ATTR(V64BITI, 0, VNx2DI, VNx2DI, TARGET_ANY)
 DEF_RISCV_ARG_MODE_ATTR(V64BITI, 1, VNx4DI, VNx4DI, TARGET_ANY)
 DEF_RISCV_ARG_MODE_ATTR(V64BITI, 2, VNx8DI, VNx8DI, TARGET_ANY)
 DEF_RISCV_ARG_MODE_ATTR(V64BITI, 3, VNx16DI, VNx16DI, TARGET_ANY)
+DEF_RISCV_ARG_MODE_ATTR_VARIABLE(VCONVERFI, 9)
+DEF_RISCV_ARG_MODE_ATTR(VCONVERFI, 0, VNx2SF, VNx2SI, TARGET_ANY)
+DEF_RISCV_ARG_MODE_ATTR(VCONVERFI, 1, VNx4SF, VNx4SI, TARGET_ANY)
+DEF_RISCV_ARG_MODE_ATTR(VCONVERFI, 2, VNx8SF, VNx8SI, TARGET_ANY)
+DEF_RISCV_ARG_MODE_ATTR(VCONVERFI, 3, VNx16SF, VNx16SI, TARGET_ANY)
+DEF_RISCV_ARG_MODE_ATTR(VCONVERFI, 4, VNx32SF, VNx32SI, TARGET_ANY)
+DEF_RISCV_ARG_MODE_ATTR(VCONVERFI, 5, VNx2DF, VNx2DI, TARGET_ANY)
+DEF_RISCV_ARG_MODE_ATTR(VCONVERFI, 6, VNx4DF, VNx4DI, TARGET_ANY)
+DEF_RISCV_ARG_MODE_ATTR(VCONVERFI, 7, VNx8DF, VNx8DI, TARGET_ANY)
+DEF_RISCV_ARG_MODE_ATTR(VCONVERFI, 8, VNx16DF, VNx16DI, TARGET_ANY)
+DEF_RISCV_ARG_MODE_ATTR_VARIABLE(VCONVERI, 21)
+DEF_RISCV_ARG_MODE_ATTR(VCONVERI, 0, VNx2HI, VNx4QI, TARGET_ANY)
+DEF_RISCV_ARG_MODE_ATTR(VCONVERI, 1, VNx4HI, VNx8QI, TARGET_ANY)
+DEF_RISCV_ARG_MODE_ATTR(VCONVERI, 2, VNx8HI, VNx16QI, TARGET_ANY)
+DEF_RISCV_ARG_MODE_ATTR(VCONVERI, 3, VNx16HI, VNx32QI, TARGET_ANY)
+DEF_RISCV_ARG_MODE_ATTR(VCONVERI, 4, VNx32HI, VNx64QI, TARGET_ANY)
+DEF_RISCV_ARG_MODE_ATTR(VCONVERI, 5, VNx64HI, VNx128QI, TARGET_ANY)
+DEF_RISCV_ARG_MODE_ATTR(VCONVERI, 6, VNx2SI, VNx8QI, TARGET_ANY)
+DEF_RISCV_ARG_MODE_ATTR(VCONVERI, 7, VNx4SI, VNx16QI, TARGET_ANY)
+DEF_RISCV_ARG_MODE_ATTR(VCONVERI, 8, VNx8SI, VNx32QI, TARGET_ANY)
+DEF_RISCV_ARG_MODE_ATTR(VCONVERI, 9, VNx16SI, VNx64QI, TARGET_ANY)
+DEF_RISCV_ARG_MODE_ATTR(VCONVERI, 10, VNx32SI, VNx128QI, TARGET_ANY)
+DEF_RISCV_ARG_MODE_ATTR(VCONVERI, 11, VNx2DI, VNx16QI, TARGET_ANY)
+DEF_RISCV_ARG_MODE_ATTR(VCONVERI, 12, VNx4DI, VNx32QI, TARGET_ANY)
+DEF_RISCV_ARG_MODE_ATTR(VCONVERI, 13, VNx8DI, VNx64QI, TARGET_ANY)
+DEF_RISCV_ARG_MODE_ATTR(VCONVERI, 14, VNx16DI, VNx128QI, TARGET_ANY)
+DEF_RISCV_ARG_MODE_ATTR(VCONVERI, 15, VNx4QI, VNx2HI, TARGET_ANY)
+DEF_RISCV_ARG_MODE_ATTR(VCONVERI, 16, VNx8QI, VNx4HI, TARGET_ANY)
+DEF_RISCV_ARG_MODE_ATTR(VCONVERI, 17, VNx16QI, VNx8HI, TARGET_ANY)
+DEF_RISCV_ARG_MODE_ATTR(VCONVERI, 18, VNx32QI, VNx16HI, TARGET_ANY)
+DEF_RISCV_ARG_MODE_ATTR(VCONVERI, 19, VNx64QI, VNx32HI, TARGET_ANY)
+DEF_RISCV_ARG_MODE_ATTR(VCONVERI, 20, VNx128QI, VNx64HI, TARGET_ANY)
+DEF_RISCV_ARG_MODE_ATTR_VARIABLE(VCONVERI2, 19)
+DEF_RISCV_ARG_MODE_ATTR(VCONVERI2, 0, VNx2SI, VNx4HI, TARGET_ANY)
+DEF_RISCV_ARG_MODE_ATTR(VCONVERI2, 1, VNx4SI, VNx8HI, TARGET_ANY)
+DEF_RISCV_ARG_MODE_ATTR(VCONVERI2, 2, VNx8SI, VNx16HI, TARGET_ANY)
+DEF_RISCV_ARG_MODE_ATTR(VCONVERI2, 3, VNx16SI, VNx32HI, TARGET_ANY)
+DEF_RISCV_ARG_MODE_ATTR(VCONVERI2, 4, VNx32SI, VNx64HI, TARGET_ANY)
+DEF_RISCV_ARG_MODE_ATTR(VCONVERI2, 5, VNx2DI, VNx8HI, TARGET_ANY)
+DEF_RISCV_ARG_MODE_ATTR(VCONVERI2, 6, VNx4DI, VNx16HI, TARGET_ANY)
+DEF_RISCV_ARG_MODE_ATTR(VCONVERI2, 7, VNx8DI, VNx32HI, TARGET_ANY)
+DEF_RISCV_ARG_MODE_ATTR(VCONVERI2, 8, VNx16DI, VNx64HI, TARGET_ANY)
+DEF_RISCV_ARG_MODE_ATTR(VCONVERI2, 9, VNx8QI, VNx2SI, TARGET_ANY)
+DEF_RISCV_ARG_MODE_ATTR(VCONVERI2, 10, VNx16QI, VNx4SI, TARGET_ANY)
+DEF_RISCV_ARG_MODE_ATTR(VCONVERI2, 11, VNx32QI, VNx8SI, TARGET_ANY)
+DEF_RISCV_ARG_MODE_ATTR(VCONVERI2, 12, VNx64QI, VNx16SI, TARGET_ANY)
+DEF_RISCV_ARG_MODE_ATTR(VCONVERI2, 13, VNx128QI, VNx32SI, TARGET_ANY)
+DEF_RISCV_ARG_MODE_ATTR(VCONVERI2, 14, VNx4HI, VNx2SI, TARGET_ANY)
+DEF_RISCV_ARG_MODE_ATTR(VCONVERI2, 15, VNx8HI, VNx4SI, TARGET_ANY)
+DEF_RISCV_ARG_MODE_ATTR(VCONVERI2, 16, VNx16HI, VNx8SI, TARGET_ANY)
+DEF_RISCV_ARG_MODE_ATTR(VCONVERI2, 17, VNx32HI, VNx16SI, TARGET_ANY)
+DEF_RISCV_ARG_MODE_ATTR(VCONVERI2, 18, VNx64HI, VNx32SI, TARGET_ANY)
+DEF_RISCV_ARG_MODE_ATTR_VARIABLE(VCONVERI3, 16)
+DEF_RISCV_ARG_MODE_ATTR(VCONVERI3, 0, VNx2DI, VNx4SI, TARGET_ANY)
+DEF_RISCV_ARG_MODE_ATTR(VCONVERI3, 1, VNx4DI, VNx8SI, TARGET_ANY)
+DEF_RISCV_ARG_MODE_ATTR(VCONVERI3, 2, VNx8DI, VNx16SI, TARGET_ANY)
+DEF_RISCV_ARG_MODE_ATTR(VCONVERI3, 3, VNx16DI, VNx32SI, TARGET_ANY)
+DEF_RISCV_ARG_MODE_ATTR(VCONVERI3, 4, VNx16QI, VNx2DI, TARGET_ANY)
+DEF_RISCV_ARG_MODE_ATTR(VCONVERI3, 5, VNx32QI, VNx4DI, TARGET_ANY)
+DEF_RISCV_ARG_MODE_ATTR(VCONVERI3, 6, VNx64QI, VNx8DI, TARGET_ANY)
+DEF_RISCV_ARG_MODE_ATTR(VCONVERI3, 7, VNx128QI, VNx16DI, TARGET_ANY)
+DEF_RISCV_ARG_MODE_ATTR(VCONVERI3, 8, VNx8HI, VNx2DI, TARGET_ANY)
+DEF_RISCV_ARG_MODE_ATTR(VCONVERI3, 9, VNx16HI, VNx4DI, TARGET_ANY)
+DEF_RISCV_ARG_MODE_ATTR(VCONVERI3, 10, VNx32HI, VNx8DI, TARGET_ANY)
+DEF_RISCV_ARG_MODE_ATTR(VCONVERI3, 11, VNx64HI, VNx16DI, TARGET_ANY)
+DEF_RISCV_ARG_MODE_ATTR(VCONVERI3, 12, VNx4SI, VNx2DI, TARGET_ANY)
+DEF_RISCV_ARG_MODE_ATTR(VCONVERI3, 13, VNx8SI, VNx4DI, TARGET_ANY)
+DEF_RISCV_ARG_MODE_ATTR(VCONVERI3, 14, VNx16SI, VNx8DI, TARGET_ANY)
+DEF_RISCV_ARG_MODE_ATTR(VCONVERI3, 15, VNx32SI, VNx16DI, TARGET_ANY)
+DEF_RISCV_ARG_MODE_ATTR_VARIABLE(VCONVERF, 9)
+DEF_RISCV_ARG_MODE_ATTR(VCONVERF, 0, VNx2SF, VNx2SF, TARGET_HARD_FLOAT)
+DEF_RISCV_ARG_MODE_ATTR(VCONVERF, 1, VNx4SF, VNx4SF, TARGET_HARD_FLOAT)
+DEF_RISCV_ARG_MODE_ATTR(VCONVERF, 2, VNx8SF, VNx8SF, TARGET_HARD_FLOAT)
+DEF_RISCV_ARG_MODE_ATTR(VCONVERF, 3, VNx16SF, VNx16SF, TARGET_HARD_FLOAT)
+DEF_RISCV_ARG_MODE_ATTR(VCONVERF, 4, VNx32SF, VNx32SF, TARGET_HARD_FLOAT)
+DEF_RISCV_ARG_MODE_ATTR(VCONVERF, 5, VNx2DF, VNx2DF, TARGET_DOUBLE_FLOAT)
+DEF_RISCV_ARG_MODE_ATTR(VCONVERF, 6, VNx4DF, VNx4DF, TARGET_DOUBLE_FLOAT)
+DEF_RISCV_ARG_MODE_ATTR(VCONVERF, 7, VNx8DF, VNx8DF, TARGET_DOUBLE_FLOAT)
+DEF_RISCV_ARG_MODE_ATTR(VCONVERF, 8, VNx16DF, VNx16DF, TARGET_DOUBLE_FLOAT)
+DEF_RISCV_ARG_MODE_ATTR_VARIABLE(VSETI, 12)
+DEF_RISCV_ARG_MODE_ATTR(VSETI, 0, VNx32QI, VNx32QI, TARGET_ANY)
+DEF_RISCV_ARG_MODE_ATTR(VSETI, 1, VNx64QI, VNx64QI, TARGET_ANY)
+DEF_RISCV_ARG_MODE_ATTR(VSETI, 2, VNx128QI, VNx128QI, TARGET_ANY)
+DEF_RISCV_ARG_MODE_ATTR(VSETI, 3, VNx16HI, VNx16HI, TARGET_ANY)
+DEF_RISCV_ARG_MODE_ATTR(VSETI, 4, VNx32HI, VNx32HI, TARGET_ANY)
+DEF_RISCV_ARG_MODE_ATTR(VSETI, 5, VNx64HI, VNx64HI, TARGET_ANY)
+DEF_RISCV_ARG_MODE_ATTR(VSETI, 6, VNx8SI, VNx8SI, TARGET_ANY)
+DEF_RISCV_ARG_MODE_ATTR(VSETI, 7, VNx16SI, VNx16SI, TARGET_ANY)
+DEF_RISCV_ARG_MODE_ATTR(VSETI, 8, VNx32SI, VNx32SI, TARGET_ANY)
+DEF_RISCV_ARG_MODE_ATTR(VSETI, 9, VNx4DI, VNx4DI, TARGET_ANY)
+DEF_RISCV_ARG_MODE_ATTR(VSETI, 10, VNx8DI, VNx8DI, TARGET_ANY)
+DEF_RISCV_ARG_MODE_ATTR(VSETI, 11, VNx16DI, VNx16DI, TARGET_ANY)
+DEF_RISCV_ARG_MODE_ATTR_VARIABLE(VSETF, 6)
+DEF_RISCV_ARG_MODE_ATTR(VSETF, 0, VNx8SF, VNx8SF, TARGET_HARD_FLOAT)
+DEF_RISCV_ARG_MODE_ATTR(VSETF, 1, VNx16SF, VNx16SF, TARGET_HARD_FLOAT)
+DEF_RISCV_ARG_MODE_ATTR(VSETF, 2, VNx32SF, VNx32SF, TARGET_HARD_FLOAT)
+DEF_RISCV_ARG_MODE_ATTR(VSETF, 3, VNx4DF, VNx4DF, TARGET_DOUBLE_FLOAT)
+DEF_RISCV_ARG_MODE_ATTR(VSETF, 4, VNx8DF, VNx8DF, TARGET_DOUBLE_FLOAT)
+DEF_RISCV_ARG_MODE_ATTR(VSETF, 5, VNx16DF, VNx16DF, TARGET_DOUBLE_FLOAT)
+DEF_RISCV_ARG_MODE_ATTR_VARIABLE(VGETI, 12)
+DEF_RISCV_ARG_MODE_ATTR(VGETI, 0, VNx16QI, VNx16QI, TARGET_ANY)
+DEF_RISCV_ARG_MODE_ATTR(VGETI, 1, VNx32QI, VNx32QI, TARGET_ANY)
+DEF_RISCV_ARG_MODE_ATTR(VGETI, 2, VNx64QI, VNx64QI, TARGET_ANY)
+DEF_RISCV_ARG_MODE_ATTR(VGETI, 3, VNx8HI, VNx8HI, TARGET_ANY)
+DEF_RISCV_ARG_MODE_ATTR(VGETI, 4, VNx16HI, VNx16HI, TARGET_ANY)
+DEF_RISCV_ARG_MODE_ATTR(VGETI, 5, VNx32HI, VNx32HI, TARGET_ANY)
+DEF_RISCV_ARG_MODE_ATTR(VGETI, 6, VNx4SI, VNx4SI, TARGET_ANY)
+DEF_RISCV_ARG_MODE_ATTR(VGETI, 7, VNx8SI, VNx8SI, TARGET_ANY)
+DEF_RISCV_ARG_MODE_ATTR(VGETI, 8, VNx16SI, VNx16SI, TARGET_ANY)
+DEF_RISCV_ARG_MODE_ATTR(VGETI, 9, VNx2DI, VNx2DI, TARGET_ANY)
+DEF_RISCV_ARG_MODE_ATTR(VGETI, 10, VNx4DI, VNx4DI, TARGET_ANY)
+DEF_RISCV_ARG_MODE_ATTR(VGETI, 11, VNx8DI, VNx8DI, TARGET_ANY)
+DEF_RISCV_ARG_MODE_ATTR_VARIABLE(VGETF, 6)
+DEF_RISCV_ARG_MODE_ATTR(VGETF, 0, VNx4SF, VNx4SF, TARGET_HARD_FLOAT)
+DEF_RISCV_ARG_MODE_ATTR(VGETF, 1, VNx8SF, VNx8SF, TARGET_HARD_FLOAT)
+DEF_RISCV_ARG_MODE_ATTR(VGETF, 2, VNx16SF, VNx16SF, TARGET_HARD_FLOAT)
+DEF_RISCV_ARG_MODE_ATTR(VGETF, 3, VNx2DF, VNx2DF, TARGET_DOUBLE_FLOAT)
+DEF_RISCV_ARG_MODE_ATTR(VGETF, 4, VNx4DF, VNx4DF, TARGET_DOUBLE_FLOAT)
+DEF_RISCV_ARG_MODE_ATTR(VGETF, 5, VNx8DF, VNx8DF, TARGET_DOUBLE_FLOAT)
+DEF_RISCV_ARG_MODE_ATTR_VARIABLE(VLMULEXT, 25)
+DEF_RISCV_ARG_MODE_ATTR(VLMULEXT, 0, VNx4QI, VNx4QI, TARGET_ANY)
+DEF_RISCV_ARG_MODE_ATTR(VLMULEXT, 1, VNx8QI, VNx8QI, TARGET_ANY)
+DEF_RISCV_ARG_MODE_ATTR(VLMULEXT, 2, VNx16QI, VNx16QI, TARGET_ANY)
+DEF_RISCV_ARG_MODE_ATTR(VLMULEXT, 3, VNx32QI, VNx32QI, TARGET_ANY)
+DEF_RISCV_ARG_MODE_ATTR(VLMULEXT, 4, VNx64QI, VNx64QI, TARGET_ANY)
+DEF_RISCV_ARG_MODE_ATTR(VLMULEXT, 5, VNx128QI, VNx128QI, TARGET_ANY)
+DEF_RISCV_ARG_MODE_ATTR(VLMULEXT, 6, VNx4HI, VNx4HI, TARGET_ANY)
+DEF_RISCV_ARG_MODE_ATTR(VLMULEXT, 7, VNx8HI, VNx8HI, TARGET_ANY)
+DEF_RISCV_ARG_MODE_ATTR(VLMULEXT, 8, VNx16HI, VNx16HI, TARGET_ANY)
+DEF_RISCV_ARG_MODE_ATTR(VLMULEXT, 9, VNx32HI, VNx32HI, TARGET_ANY)
+DEF_RISCV_ARG_MODE_ATTR(VLMULEXT, 10, VNx64HI, VNx64HI, TARGET_ANY)
+DEF_RISCV_ARG_MODE_ATTR(VLMULEXT, 11, VNx4SI, VNx4SI, TARGET_ANY)
+DEF_RISCV_ARG_MODE_ATTR(VLMULEXT, 12, VNx8SI, VNx8SI, TARGET_ANY)
+DEF_RISCV_ARG_MODE_ATTR(VLMULEXT, 13, VNx16SI, VNx16SI, TARGET_ANY)
+DEF_RISCV_ARG_MODE_ATTR(VLMULEXT, 14, VNx32SI, VNx32SI, TARGET_ANY)
+DEF_RISCV_ARG_MODE_ATTR(VLMULEXT, 15, VNx4DI, VNx4DI, TARGET_ANY)
+DEF_RISCV_ARG_MODE_ATTR(VLMULEXT, 16, VNx8DI, VNx8DI, TARGET_ANY)
+DEF_RISCV_ARG_MODE_ATTR(VLMULEXT, 17, VNx16DI, VNx16DI, TARGET_ANY)
+DEF_RISCV_ARG_MODE_ATTR(VLMULEXT, 18, VNx4SF, VNx4SF, TARGET_HARD_FLOAT)
+DEF_RISCV_ARG_MODE_ATTR(VLMULEXT, 19, VNx8SF, VNx8SF, TARGET_HARD_FLOAT)
+DEF_RISCV_ARG_MODE_ATTR(VLMULEXT, 20, VNx16SF, VNx16SF, TARGET_HARD_FLOAT)
+DEF_RISCV_ARG_MODE_ATTR(VLMULEXT, 21, VNx32SF, VNx32SF, TARGET_HARD_FLOAT)
+DEF_RISCV_ARG_MODE_ATTR(VLMULEXT, 22, VNx4DF, VNx4DF, TARGET_DOUBLE_FLOAT)
+DEF_RISCV_ARG_MODE_ATTR(VLMULEXT, 23, VNx8DF, VNx8DF, TARGET_DOUBLE_FLOAT)
+DEF_RISCV_ARG_MODE_ATTR(VLMULEXT, 24, VNx16DF, VNx16DF, TARGET_DOUBLE_FLOAT)
+DEF_RISCV_ARG_MODE_ATTR_VARIABLE(VLMULTRUNC, 25)
+DEF_RISCV_ARG_MODE_ATTR(VLMULTRUNC, 0, VNx2QI, VNx2QI, TARGET_ANY)
+DEF_RISCV_ARG_MODE_ATTR(VLMULTRUNC, 1, VNx4QI, VNx4QI, TARGET_ANY)
+DEF_RISCV_ARG_MODE_ATTR(VLMULTRUNC, 2, VNx8QI, VNx8QI, TARGET_ANY)
+DEF_RISCV_ARG_MODE_ATTR(VLMULTRUNC, 3, VNx16QI, VNx16QI, TARGET_ANY)
+DEF_RISCV_ARG_MODE_ATTR(VLMULTRUNC, 4, VNx32QI, VNx32QI, TARGET_ANY)
+DEF_RISCV_ARG_MODE_ATTR(VLMULTRUNC, 5, VNx64QI, VNx64QI, TARGET_ANY)
+DEF_RISCV_ARG_MODE_ATTR(VLMULTRUNC, 6, VNx2HI, VNx2HI, TARGET_ANY)
+DEF_RISCV_ARG_MODE_ATTR(VLMULTRUNC, 7, VNx4HI, VNx4HI, TARGET_ANY)
+DEF_RISCV_ARG_MODE_ATTR(VLMULTRUNC, 8, VNx8HI, VNx8HI, TARGET_ANY)
+DEF_RISCV_ARG_MODE_ATTR(VLMULTRUNC, 9, VNx16HI, VNx16HI, TARGET_ANY)
+DEF_RISCV_ARG_MODE_ATTR(VLMULTRUNC, 10, VNx32HI, VNx32HI, TARGET_ANY)
+DEF_RISCV_ARG_MODE_ATTR(VLMULTRUNC, 11, VNx2SI, VNx2SI, TARGET_ANY)
+DEF_RISCV_ARG_MODE_ATTR(VLMULTRUNC, 12, VNx4SI, VNx4SI, TARGET_ANY)
+DEF_RISCV_ARG_MODE_ATTR(VLMULTRUNC, 13, VNx8SI, VNx8SI, TARGET_ANY)
+DEF_RISCV_ARG_MODE_ATTR(VLMULTRUNC, 14, VNx16SI, VNx16SI, TARGET_ANY)
+DEF_RISCV_ARG_MODE_ATTR(VLMULTRUNC, 15, VNx2DI, VNx2DI, TARGET_ANY)
+DEF_RISCV_ARG_MODE_ATTR(VLMULTRUNC, 16, VNx4DI, VNx4DI, TARGET_ANY)
+DEF_RISCV_ARG_MODE_ATTR(VLMULTRUNC, 17, VNx8DI, VNx8DI, TARGET_ANY)
+DEF_RISCV_ARG_MODE_ATTR(VLMULTRUNC, 18, VNx2SF, VNx2SF, TARGET_HARD_FLOAT)
+DEF_RISCV_ARG_MODE_ATTR(VLMULTRUNC, 19, VNx4SF, VNx4SF, TARGET_HARD_FLOAT)
+DEF_RISCV_ARG_MODE_ATTR(VLMULTRUNC, 20, VNx8SF, VNx8SF, TARGET_HARD_FLOAT)
+DEF_RISCV_ARG_MODE_ATTR(VLMULTRUNC, 21, VNx16SF, VNx16SF, TARGET_HARD_FLOAT)
+DEF_RISCV_ARG_MODE_ATTR(VLMULTRUNC, 22, VNx2DF, VNx2DF, TARGET_DOUBLE_FLOAT)
+DEF_RISCV_ARG_MODE_ATTR(VLMULTRUNC, 23, VNx4DF, VNx4DF, TARGET_DOUBLE_FLOAT)
+DEF_RISCV_ARG_MODE_ATTR(VLMULTRUNC, 24, VNx8DF, VNx8DF, TARGET_DOUBLE_FLOAT)
 DEF_RISCV_ARG_MODE_ATTR_VARIABLE(VM, 69)
 DEF_RISCV_ARG_MODE_ATTR(VM, 0, VNx2BI, VNx2BI, TARGET_ANY)
 DEF_RISCV_ARG_MODE_ATTR(VM, 1, VNx4BI, VNx4BI, TARGET_ANY)
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 7a1f19b32ee..e88057e992a 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -5009,6 +5009,9 @@  riscv_hard_regno_mode_ok (unsigned int regno, machine_mode mode)
       if (rvv_mode_p (mode))
 	return false;
 	
+      if (!FLOAT_MODE_P (mode))
+	return false;
+	
       if (!FP_REG_P (regno + nregs - 1))
 	return false;
 
@@ -5073,13 +5076,13 @@  riscv_class_max_nregs (reg_class_t rclass, machine_mode mode)
   if (reg_class_subset_p (rclass, GR_REGS))
     return riscv_hard_regno_nregs (GP_REG_FIRST, mode);
 		
-  if (reg_class_subset_p (V_REGS, rclass))
+  if (reg_class_subset_p (rclass, V_REGS))
     return riscv_hard_regno_nregs (V_REG_FIRST, mode);
 
-  if (reg_class_subset_p (VL_REGS, rclass))
+  if (reg_class_subset_p (rclass, VL_REGS))
     return 1;
 
-  if (reg_class_subset_p (VTYPE_REGS, rclass))
+  if (reg_class_subset_p (rclass, VTYPE_REGS))
     return 1;
 		
   return 0;
@@ -5718,8 +5721,11 @@  riscv_slow_unaligned_access (machine_mode, unsigned int)
 /* Implement TARGET_CAN_CHANGE_MODE_CLASS.  */
 
 static bool
-riscv_can_change_mode_class (machine_mode, machine_mode, reg_class_t rclass)
+riscv_can_change_mode_class (machine_mode from, machine_mode to, reg_class_t rclass)
 {
+	if (rvv_mode_p (from) && rvv_mode_p (to))
+    return true;
+		
   return !reg_classes_intersect_p (FP_REGS, rclass);
 }
 
@@ -6003,6 +6009,25 @@  riscv_mangle_type (const_tree type)
   return NULL;
 }
 
+/* Implement REGMODE_NATURAL_SIZE.  */
+
+poly_uint64
+riscv_regmode_natural_size (machine_mode mode)
+{
+  /* The natural size for RVV data modes is one RVV data vector,
+     and similarly for predicates.  We can't independently modify
+     anything smaller than that.  */
+  /* ??? For now, only do this for variable-width RVV registers.
+     Doing it for constant-sized registers breaks lower-subreg.c.  */
+  /* For partial tuple vector, we should
+     use the mode of the vector subpart,
+     in case of segment loads and stores. */
+  if (!riscv_vector_chunks.is_constant () && rvv_mode_p (mode))
+    return BYTES_PER_RISCV_VECTOR;
+
+  return UNITS_PER_WORD;
+}
+
 /* Initialize the GCC target structure.  */
 #undef TARGET_ASM_ALIGNED_HI_OP
 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h
index cb4cfc0f73e..c54c984e70b 100644
--- a/gcc/config/riscv/riscv.h
+++ b/gcc/config/riscv/riscv.h
@@ -1069,4 +1069,6 @@  extern void riscv_remove_unneeded_save_restore_calls (void);
 
 #define REGISTER_TARGET_PRAGMAS() riscv_register_pragmas ()
 
+#define REGMODE_NATURAL_SIZE(MODE) riscv_regmode_natural_size (MODE)
+
 #endif /* ! GCC_RISCV_H */
diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector-iterators.md
index e01305ef3fc..df9011ee901 100644
--- a/gcc/config/riscv/vector-iterators.md
+++ b/gcc/config/riscv/vector-iterators.md
@@ -23,6 +23,18 @@ 
   UNSPEC_VSETVLI
   ;; RVV instructions.
   UNSPEC_RVV
+   ;; reinterpret
+  UNSPEC_REINTERPRET
+  ;; lmul_ext
+  UNSPEC_LMUL_EXT
+  ;; lmul_trunc
+  UNSPEC_LMUL_TRUNC
+  ;; set a vector
+  UNSPEC_SET_VECTOR
+  ;; get a vector
+  UNSPEC_GET_VECTOR
+  ;; vec_duplicate
+  UNSPEC_VEC_DUPLICATE
   ;; vector select
   UNSPEC_SELECT
   
@@ -85,6 +97,136 @@ 
 ;; All vector modes supported for integer sew = 64.
 (define_mode_iterator V64BITI [VNx2DI VNx4DI VNx8DI VNx16DI])
 
+;; vector integer and float-point mode interconversion.
+(define_mode_attr VCONVERFI [
+  (VNx2SF "VNx2SI")
+  (VNx4SF "VNx4SI")
+  (VNx8SF "VNx8SI")
+  (VNx16SF "VNx16SI")
+  (VNx32SF "VNx32SI")
+  (VNx2DF "VNx2DI")
+  (VNx4DF "VNx4DI")
+  (VNx8DF "VNx8DI")
+  (VNx16DF "VNx16DI")])
+
+;; vector integer same lmul but different sew interconversion.
+(define_mode_attr VCONVERI [
+  (VNx2HI "VNx4QI")
+  (VNx4HI "VNx8QI")
+  (VNx8HI "VNx16QI")
+  (VNx16HI "VNx32QI")
+  (VNx32HI "VNx64QI")
+  (VNx64HI "VNx128QI")
+  (VNx2SI "VNx8QI")
+  (VNx4SI "VNx16QI")
+  (VNx8SI "VNx32QI")
+  (VNx16SI "VNx64QI")
+  (VNx32SI "VNx128QI")
+  (VNx2DI "VNx16QI")
+  (VNx4DI "VNx32QI")
+  (VNx8DI "VNx64QI")
+  (VNx16DI "VNx128QI")
+  (VNx4QI "VNx2HI")
+  (VNx8QI "VNx4HI")
+  (VNx16QI "VNx8HI")
+  (VNx32QI "VNx16HI")
+  (VNx64QI "VNx32HI")
+  (VNx128QI "VNx64HI")])
+
+(define_mode_attr VCONVERI2 [
+  (VNx2SI "VNx4HI")
+  (VNx4SI "VNx8HI")
+  (VNx8SI "VNx16HI")
+  (VNx16SI "VNx32HI")
+  (VNx32SI "VNx64HI")
+  (VNx2DI "VNx8HI")
+  (VNx4DI "VNx16HI")
+  (VNx8DI "VNx32HI")
+  (VNx16DI "VNx64HI")
+  (VNx8QI "VNx2SI")
+  (VNx16QI "VNx4SI")
+  (VNx32QI "VNx8SI")
+  (VNx64QI "VNx16SI")
+  (VNx128QI "VNx32SI")
+  (VNx4HI "VNx2SI")
+  (VNx8HI "VNx4SI")
+  (VNx16HI "VNx8SI")
+  (VNx32HI "VNx16SI")
+  (VNx64HI "VNx32SI")])
+
+(define_mode_attr VCONVERI3 [
+  (VNx2DI "VNx4SI")
+  (VNx4DI "VNx8SI")
+  (VNx8DI "VNx16SI")
+  (VNx16DI "VNx32SI")
+  (VNx16QI "VNx2DI")
+  (VNx32QI "VNx4DI")
+  (VNx64QI "VNx8DI")
+  (VNx128QI "VNx16DI")
+  (VNx8HI "VNx2DI")
+  (VNx16HI "VNx4DI")
+  (VNx32HI "VNx8DI")
+  (VNx64HI "VNx16DI")
+  (VNx4SI "VNx2DI")
+  (VNx8SI "VNx4DI")
+  (VNx16SI "VNx8DI")
+  (VNx32SI "VNx16DI")])
+
+;; vector iterator integer and float-point mode interconversion.
+(define_mode_iterator VCONVERF [
+  (VNx2SF "TARGET_HARD_FLOAT")
+  (VNx4SF "TARGET_HARD_FLOAT")
+  (VNx8SF "TARGET_HARD_FLOAT")
+  (VNx16SF "TARGET_HARD_FLOAT")
+  (VNx32SF "TARGET_HARD_FLOAT")
+  (VNx2DF "TARGET_DOUBLE_FLOAT")
+  (VNx4DF "TARGET_DOUBLE_FLOAT")
+  (VNx8DF "TARGET_DOUBLE_FLOAT")
+  (VNx16DF "TARGET_DOUBLE_FLOAT")])
+
+;; vector modes can be set.
+(define_mode_iterator VSETI [
+  VNx32QI VNx64QI VNx128QI
+  VNx16HI VNx32HI VNx64HI
+  VNx8SI VNx16SI VNx32SI
+  VNx4DI VNx8DI VNx16DI])
+
+(define_mode_iterator VSETF [
+  (VNx8SF "TARGET_HARD_FLOAT") (VNx16SF "TARGET_HARD_FLOAT") (VNx32SF "TARGET_HARD_FLOAT")
+  (VNx4DF "TARGET_DOUBLE_FLOAT") (VNx8DF "TARGET_DOUBLE_FLOAT") (VNx16DF "TARGET_DOUBLE_FLOAT")])
+
+;; vector modes can be get.
+(define_mode_iterator VGETI [
+  VNx16QI VNx32QI VNx64QI
+  VNx8HI VNx16HI VNx32HI
+  VNx4SI VNx8SI VNx16SI
+  VNx2DI VNx4DI VNx8DI])
+
+(define_mode_iterator VGETF [
+  (VNx4SF "TARGET_HARD_FLOAT") (VNx8SF "TARGET_HARD_FLOAT") (VNx16SF "TARGET_HARD_FLOAT")
+  (VNx2DF "TARGET_DOUBLE_FLOAT") (VNx4DF "TARGET_DOUBLE_FLOAT") (VNx8DF "TARGET_DOUBLE_FLOAT")])
+
+;; All vector extend modes supported.
+(define_mode_iterator VLMULEXT [
+  VNx4QI VNx8QI VNx16QI VNx32QI VNx64QI VNx128QI
+  VNx4HI VNx8HI VNx16HI VNx32HI VNx64HI
+  VNx4SI VNx8SI VNx16SI VNx32SI
+  VNx4DI VNx8DI VNx16DI
+  (VNx4SF "TARGET_HARD_FLOAT") (VNx8SF "TARGET_HARD_FLOAT")
+  (VNx16SF "TARGET_HARD_FLOAT") (VNx32SF "TARGET_HARD_FLOAT")
+  (VNx4DF "TARGET_DOUBLE_FLOAT") (VNx8DF "TARGET_DOUBLE_FLOAT")
+  (VNx16DF "TARGET_DOUBLE_FLOAT")])
+
+;; All vector truncate modes supported.
+(define_mode_iterator VLMULTRUNC [
+  VNx2QI VNx4QI VNx8QI VNx16QI VNx32QI VNx64QI
+  VNx2HI VNx4HI VNx8HI VNx16HI VNx32HI
+  VNx2SI VNx4SI VNx8SI VNx16SI
+  VNx2DI VNx4DI VNx8DI
+  (VNx2SF "TARGET_HARD_FLOAT") (VNx4SF "TARGET_HARD_FLOAT") (VNx8SF "TARGET_HARD_FLOAT")
+  (VNx16SF "TARGET_HARD_FLOAT")
+  (VNx2DF "TARGET_DOUBLE_FLOAT") (VNx4DF "TARGET_DOUBLE_FLOAT") (VNx8DF "TARGET_DOUBLE_FLOAT")])
+
 ;; Map a vector int or float mode to a vector compare mode.
 (define_mode_attr VM [
   (VNx2BI "VNx2BI") (VNx4BI "VNx4BI") (VNx8BI "VNx8BI") (VNx16BI "VNx16BI")
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index 1731d969372..54e68aa165b 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -349,6 +349,139 @@ 
   [(set_attr "type" "vsetvl")
    (set_attr "mode" "none")])
 
+;; -------------------------------------------------------------------------
+;; ---- [INT,FP] Vector Misc Functions
+;; -------------------------------------------------------------------------
+;; Includes:
+;; - Reinterpret between different vector modes
+;; - Vector LMUL extension
+;; - Vector LMUL truncation
+;; - insert a vector to a vector group
+;; - get a vector from a vector group
+;; -------------------------------------------------------------------------
+
+;; Reinterpret operand 1 in operand 0's mode, without changing its contents.
+;; This is equivalent to a subreg on little-endian targets but not for
+;; big-endian; see the comment at the head of the file for details.
+(define_expand "@vreinterpret<mode>"
+  [(set (match_operand:V 0 "register_operand")
+    (unspec:V
+      [(match_operand 1 "vector_any_register_operand")] UNSPEC_REINTERPRET))]
+  "TARGET_VECTOR"
+{
+  machine_mode src_mode = GET_MODE (operands[1]);
+  if (targetm.can_change_mode_class (<MODE>mode, src_mode, FP_REGS))
+    {
+      emit_move_insn (operands[0], gen_lowpart (<MODE>mode, operands[1]));
+      DONE;
+    }
+})
+
+;; Vector LMUL extension
+(define_expand "@vlmul_ext<mode>"
+  [(set (match_operand:VLMULEXT 0 "register_operand")
+    (unspec:VLMULEXT
+      [(match_operand 1 "vector_any_register_operand")] UNSPEC_LMUL_EXT))]
+  "TARGET_VECTOR"
+{
+})
+
+(define_insn_and_split "*vlmul_ext<VLMULEXT:mode><V:mode>"
+  [(set (match_operand:VLMULEXT 0 "register_operand" "=vr, ?&vr")
+    (unspec:VLMULEXT
+      [(match_operand:V 1 "register_operand" "0, vr")] UNSPEC_LMUL_EXT))]
+  "TARGET_VECTOR"
+  "#"
+  "&& reload_completed"
+  [(const_int 0)]
+  {
+    rtx subreg = simplify_gen_subreg (<V:MODE>mode, operands[0], <VLMULEXT:MODE>mode, 0);
+    riscv_emit_move (subreg, operands[1]);
+    DONE;
+  })
+
+;; Vector LMUL truncation
+(define_expand "@vlmul_trunc<mode>"
+  [(set (match_operand:VLMULTRUNC 0 "register_operand")
+    (unspec:VLMULTRUNC
+      [(match_operand 1 "vector_any_register_operand")] UNSPEC_LMUL_TRUNC))]
+  "TARGET_VECTOR"
+{
+  rtx subreg = simplify_gen_subreg (<MODE>mode, operands[1], GET_MODE (operands[1]), 0);
+  riscv_emit_move (operands[0], subreg);
+  DONE;
+})
+
+;; insert a vector to a vector group
+(define_expand "@vset<mode>"
+  [(set (match_operand:VSETI 0 "register_operand")
+    (unspec:VSETI
+      [(match_operand:VSETI 1 "register_operand" "0")
+       (match_operand 2 "const_int_operand")
+       (match_operand 3 "vector_any_register_operand")] UNSPEC_SET_VECTOR))]
+  "TARGET_VECTOR"
+{
+  unsigned int nvecs = exact_div (GET_MODE_SIZE (GET_MODE (operands[0])),
+        GET_MODE_SIZE (GET_MODE (operands[3]))).to_constant ();
+  poly_int64 offset = (INTVAL (operands[2]) & (nvecs - 1))
+        * GET_MODE_SIZE (GET_MODE (operands[3]));
+  rtx subreg = simplify_gen_subreg (GET_MODE (operands[3]), operands[1], GET_MODE (operands[1]), offset);
+  riscv_emit_move (subreg, operands[3]);
+  riscv_emit_move (operands[0], operands[1]);
+  DONE;
+})
+
+(define_expand "@vset<mode>"
+  [(set (match_operand:VSETF 0 "register_operand")
+    (unspec:VSETF
+      [(match_operand:VSETF 1 "register_operand" "0")
+       (match_operand 2 "const_int_operand")
+       (match_operand 3 "vector_any_register_operand")] UNSPEC_SET_VECTOR))]
+  "TARGET_VECTOR"
+{
+  unsigned int nvecs = exact_div (GET_MODE_SIZE (GET_MODE (operands[0])),
+        GET_MODE_SIZE (GET_MODE (operands[3]))).to_constant ();
+  poly_int64 offset = (INTVAL (operands[2]) & (nvecs - 1))
+        * GET_MODE_SIZE (GET_MODE (operands[3]));
+  rtx subreg = simplify_gen_subreg (GET_MODE (operands[3]), operands[1], GET_MODE (operands[1]), offset);
+  riscv_emit_move (subreg, operands[3]);
+  riscv_emit_move (operands[0], operands[1]);
+  DONE;
+})
+
+;; get a vector from a vector group
+(define_expand "@vget<mode>"
+  [(set (match_operand:VGETI 0 "register_operand")
+    (unspec:VGETI
+      [(match_operand 1 "vector_any_register_operand")
+       (match_operand 2 "const_int_operand")] UNSPEC_GET_VECTOR))]
+  "TARGET_VECTOR"
+{
+  unsigned int nvecs = exact_div (GET_MODE_SIZE (GET_MODE (operands[1])),
+        GET_MODE_SIZE (GET_MODE (operands[0]))).to_constant ();
+  poly_int64 offset = (INTVAL (operands[2]) & (nvecs - 1))
+        * GET_MODE_SIZE (GET_MODE (operands[0]));
+  rtx subreg = simplify_gen_subreg (GET_MODE (operands[0]), operands[1], GET_MODE (operands[1]), offset);
+  riscv_emit_move (operands[0], subreg);
+  DONE;
+})
+
+(define_expand "@vget<mode>"
+  [(set (match_operand:VGETF 0 "register_operand")
+    (unspec:VGETF
+      [(match_operand 1 "vector_any_register_operand")
+       (match_operand 2 "const_int_operand")] UNSPEC_GET_VECTOR))]
+  "TARGET_VECTOR"
+{
+  unsigned int nvecs = exact_div (GET_MODE_SIZE (GET_MODE (operands[1])),
+        GET_MODE_SIZE (GET_MODE (operands[0]))).to_constant ();
+  poly_int64 offset = (INTVAL (operands[2]) & (nvecs - 1))
+        * GET_MODE_SIZE (GET_MODE (operands[0]));
+  rtx subreg = simplify_gen_subreg (GET_MODE (operands[0]), operands[1], GET_MODE (operands[1]), offset);
+  riscv_emit_move (operands[0], subreg);
+  DONE;
+})
+
 ;; -------------------------------------------------------------------------------
 ;; ---- 7. Vector Loads and Stores
 ;; -------------------------------------------------------------------------------
diff --git a/gcc/testsuite/g++.target/riscv/rvv/misc_func.C b/gcc/testsuite/g++.target/riscv/rvv/misc_func.C
new file mode 100644
index 00000000000..b527bce1cab
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/misc_func.C
@@ -0,0 +1,2597 @@ 
+/* { dg-do compile } */
+/* { dg-skip-if "test vector intrinsic" { *-*-* } { "*" } { "-march=rv*v*" } } */
+
+#include <stddef.h>
+#include <riscv_vector.h>
+
+vuint8mf8_t test_vreinterpret_v_i8mf8_u8mf8(vint8mf8_t src)
+{
+  vuint8mf8_t a = vreinterpret_u8mf8(src);
+  return a;
+}
+
+vuint8mf4_t test_vreinterpret_v_i8mf4_u8mf4(vint8mf4_t src)
+{
+  vuint8mf4_t a = vreinterpret_u8mf4(src);
+  return a;
+}
+
+vuint8mf2_t test_vreinterpret_v_i8mf2_u8mf2(vint8mf2_t src)
+{
+  vuint8mf2_t a = vreinterpret_u8mf2(src);
+  return a;
+}
+
+vuint8m1_t test_vreinterpret_v_i8m1_u8m1(vint8m1_t src)
+{
+  vuint8m1_t a = vreinterpret_u8m1(src);
+  return a;
+}
+
+vuint8m2_t test_vreinterpret_v_i8m2_u8m2(vint8m2_t src)
+{
+  vuint8m2_t a = vreinterpret_u8m2(src);
+  return a;
+}
+
+vuint8m4_t test_vreinterpret_v_i8m4_u8m4(vint8m4_t src)
+{
+  vuint8m4_t a = vreinterpret_u8m4(src);
+  return a;
+}
+
+vuint8m8_t test_vreinterpret_v_i8m8_u8m8(vint8m8_t src)
+{
+  vuint8m8_t a = vreinterpret_u8m8(src);
+  return a;
+}
+
+vint8mf8_t test_vreinterpret_v_u8mf8_i8mf8(vuint8mf8_t src)
+{
+  vint8mf8_t a = vreinterpret_i8mf8(src);
+  return a;
+}
+
+vint8mf4_t test_vreinterpret_v_u8mf4_i8mf4(vuint8mf4_t src)
+{
+  vint8mf4_t a = vreinterpret_i8mf4(src);
+  return a;
+}
+
+vint8mf2_t test_vreinterpret_v_u8mf2_i8mf2(vuint8mf2_t src)
+{
+  vint8mf2_t a = vreinterpret_i8mf2(src);
+  return a;
+}
+
+vint8m1_t test_vreinterpret_v_u8m1_i8m1(vuint8m1_t src)
+{
+  vint8m1_t a = vreinterpret_i8m1(src);
+  return a;
+}
+
+vint8m2_t test_vreinterpret_v_u8m2_i8m2(vuint8m2_t src)
+{
+  vint8m2_t a = vreinterpret_i8m2(src);
+  return a;
+}
+
+vint8m4_t test_vreinterpret_v_u8m4_i8m4(vuint8m4_t src)
+{
+  vint8m4_t a = vreinterpret_i8m4(src);
+  return a;
+}
+
+vint8m8_t test_vreinterpret_v_u8m8_i8m8(vuint8m8_t src)
+{
+  vint8m8_t a = vreinterpret_i8m8(src);
+  return a;
+}
+
+vuint16mf4_t test_vreinterpret_v_i16mf4_u16mf4(vint16mf4_t src)
+{
+  vuint16mf4_t a = vreinterpret_u16mf4(src);
+  return a;
+}
+
+vuint16mf2_t test_vreinterpret_v_i16mf2_u16mf2(vint16mf2_t src)
+{
+  vuint16mf2_t a = vreinterpret_u16mf2(src);
+  return a;
+}
+
+vuint16m1_t test_vreinterpret_v_i16m1_u16m1(vint16m1_t src)
+{
+  vuint16m1_t a = vreinterpret_u16m1(src);
+  return a;
+}
+
+vuint16m2_t test_vreinterpret_v_i16m2_u16m2(vint16m2_t src)
+{
+  vuint16m2_t a = vreinterpret_u16m2(src);
+  return a;
+}
+
+vuint16m4_t test_vreinterpret_v_i16m4_u16m4(vint16m4_t src)
+{
+  vuint16m4_t a = vreinterpret_u16m4(src);
+  return a;
+}
+
+vuint16m8_t test_vreinterpret_v_i16m8_u16m8(vint16m8_t src)
+{
+  vuint16m8_t a = vreinterpret_u16m8(src);
+  return a;
+}
+
+vint16mf4_t test_vreinterpret_v_u16mf4_i16mf4(vuint16mf4_t src)
+{
+  vint16mf4_t a = vreinterpret_i16mf4(src);
+  return a;
+}
+
+vint16mf2_t test_vreinterpret_v_u16mf2_i16mf2(vuint16mf2_t src)
+{
+  vint16mf2_t a = vreinterpret_i16mf2(src);
+  return a;
+}
+
+vint16m1_t test_vreinterpret_v_u16m1_i16m1(vuint16m1_t src)
+{
+  vint16m1_t a = vreinterpret_i16m1(src);
+  return a;
+}
+
+vint16m2_t test_vreinterpret_v_u16m2_i16m2(vuint16m2_t src)
+{
+  vint16m2_t a = vreinterpret_i16m2(src);
+  return a;
+}
+
+vint16m4_t test_vreinterpret_v_u16m4_i16m4(vuint16m4_t src)
+{
+  vint16m4_t a = vreinterpret_i16m4(src);
+  return a;
+}
+
+vint16m8_t test_vreinterpret_v_u16m8_i16m8(vuint16m8_t src)
+{
+  vint16m8_t a = vreinterpret_i16m8(src);
+  return a;
+}
+
+vuint32mf2_t test_vreinterpret_v_i32mf2_u32mf2(vint32mf2_t src)
+{
+  vuint32mf2_t a = vreinterpret_u32mf2(src);
+  return a;
+}
+
+vuint32m1_t test_vreinterpret_v_i32m1_u32m1(vint32m1_t src)
+{
+  vuint32m1_t a = vreinterpret_u32m1(src);
+  return a;
+}
+
+vuint32m2_t test_vreinterpret_v_i32m2_u32m2(vint32m2_t src)
+{
+  vuint32m2_t a = vreinterpret_u32m2(src);
+  return a;
+}
+
+vuint32m4_t test_vreinterpret_v_i32m4_u32m4(vint32m4_t src)
+{
+  vuint32m4_t a = vreinterpret_u32m4(src);
+  return a;
+}
+
+vuint32m8_t test_vreinterpret_v_i32m8_u32m8(vint32m8_t src)
+{
+  vuint32m8_t a = vreinterpret_u32m8(src);
+  return a;
+}
+
+vfloat32mf2_t test_vreinterpret_v_i32mf2_f32mf2(vint32mf2_t src)
+{
+  vfloat32mf2_t a = vreinterpret_f32mf2(src);
+  return a;
+}
+
+vfloat32m1_t test_vreinterpret_v_i32m1_f32m1(vint32m1_t src)
+{
+  vfloat32m1_t a = vreinterpret_f32m1(src);
+  return a;
+}
+
+vfloat32m2_t test_vreinterpret_v_i32m2_f32m2(vint32m2_t src)
+{
+  vfloat32m2_t a = vreinterpret_f32m2(src);
+  return a;
+}
+
+vfloat32m4_t test_vreinterpret_v_i32m4_f32m4(vint32m4_t src)
+{
+  vfloat32m4_t a = vreinterpret_f32m4(src);
+  return a;
+}
+
+vfloat32m8_t test_vreinterpret_v_i32m8_f32m8(vint32m8_t src)
+{
+  vfloat32m8_t a = vreinterpret_f32m8(src);
+  return a;
+}
+
+vint32mf2_t test_vreinterpret_v_u32mf2_i32mf2(vuint32mf2_t src)
+{
+  vint32mf2_t a = vreinterpret_i32mf2(src);
+  return a;
+}
+
+vint32m1_t test_vreinterpret_v_u32m1_i32m1(vuint32m1_t src)
+{
+  vint32m1_t a = vreinterpret_i32m1(src);
+  return a;
+}
+
+vint32m2_t test_vreinterpret_v_u32m2_i32m2(vuint32m2_t src)
+{
+  vint32m2_t a = vreinterpret_i32m2(src);
+  return a;
+}
+
+vint32m4_t test_vreinterpret_v_u32m4_i32m4(vuint32m4_t src)
+{
+  vint32m4_t a = vreinterpret_i32m4(src);
+  return a;
+}
+
+vint32m8_t test_vreinterpret_v_u32m8_i32m8(vuint32m8_t src)
+{
+  vint32m8_t a = vreinterpret_i32m8(src);
+  return a;
+}
+
+vfloat32mf2_t test_vreinterpret_v_u32mf2_f32mf2(vuint32mf2_t src)
+{
+  vfloat32mf2_t a = vreinterpret_f32mf2(src);
+  return a;
+}
+
+vfloat32m1_t test_vreinterpret_v_u32m1_f32m1(vuint32m1_t src)
+{
+  vfloat32m1_t a = vreinterpret_f32m1(src);
+  return a;
+}
+
+vfloat32m2_t test_vreinterpret_v_u32m2_f32m2(vuint32m2_t src)
+{
+  vfloat32m2_t a = vreinterpret_f32m2(src);
+  return a;
+}
+
+vfloat32m4_t test_vreinterpret_v_u32m4_f32m4(vuint32m4_t src)
+{
+  vfloat32m4_t a = vreinterpret_f32m4(src);
+  return a;
+}
+
+vfloat32m8_t test_vreinterpret_v_u32m8_f32m8(vuint32m8_t src)
+{
+  vfloat32m8_t a = vreinterpret_f32m8(src);
+  return a;
+}
+
+vint32mf2_t test_vreinterpret_v_f32mf2_i32mf2(vfloat32mf2_t src)
+{
+  vint32mf2_t a = vreinterpret_i32mf2(src);
+  return a;
+}
+
+vint32m1_t test_vreinterpret_v_f32m1_i32m1(vfloat32m1_t src)
+{
+  vint32m1_t a = vreinterpret_i32m1(src);
+  return a;
+}
+
+vint32m2_t test_vreinterpret_v_f32m2_i32m2(vfloat32m2_t src)
+{
+  vint32m2_t a = vreinterpret_i32m2(src);
+  return a;
+}
+
+vint32m4_t test_vreinterpret_v_f32m4_i32m4(vfloat32m4_t src)
+{
+  vint32m4_t a = vreinterpret_i32m4(src);
+  return a;
+}
+
+vint32m8_t test_vreinterpret_v_f32m8_i32m8(vfloat32m8_t src)
+{
+  vint32m8_t a = vreinterpret_i32m8(src);
+  return a;
+}
+
+vuint32mf2_t test_vreinterpret_v_f32mf2_u32mf2(vfloat32mf2_t src)
+{
+  vuint32mf2_t a = vreinterpret_u32mf2(src);
+  return a;
+}
+
+vuint32m1_t test_vreinterpret_v_f32m1_u32m1(vfloat32m1_t src)
+{
+  vuint32m1_t a = vreinterpret_u32m1(src);
+  return a;
+}
+
+vuint32m2_t test_vreinterpret_v_f32m2_u32m2(vfloat32m2_t src)
+{
+  vuint32m2_t a = vreinterpret_u32m2(src);
+  return a;
+}
+
+vuint32m4_t test_vreinterpret_v_f32m4_u32m4(vfloat32m4_t src)
+{
+  vuint32m4_t a = vreinterpret_u32m4(src);
+  return a;
+}
+
+vuint32m8_t test_vreinterpret_v_f32m8_u32m8(vfloat32m8_t src)
+{
+  vuint32m8_t a = vreinterpret_u32m8(src);
+  return a;
+}
+
+vuint64m1_t test_vreinterpret_v_i64m1_u64m1(vint64m1_t src)
+{
+  vuint64m1_t a = vreinterpret_u64m1(src);
+  return a;
+}
+
+vuint64m2_t test_vreinterpret_v_i64m2_u64m2(vint64m2_t src)
+{
+  vuint64m2_t a = vreinterpret_u64m2(src);
+  return a;
+}
+
+vuint64m4_t test_vreinterpret_v_i64m4_u64m4(vint64m4_t src)
+{
+  vuint64m4_t a = vreinterpret_u64m4(src);
+  return a;
+}
+
+vuint64m8_t test_vreinterpret_v_i64m8_u64m8(vint64m8_t src)
+{
+  vuint64m8_t a = vreinterpret_u64m8(src);
+  return a;
+}
+
+vfloat64m1_t test_vreinterpret_v_i64m1_f64m1(vint64m1_t src)
+{
+  vfloat64m1_t a = vreinterpret_f64m1(src);
+  return a;
+}
+
+vfloat64m2_t test_vreinterpret_v_i64m2_f64m2(vint64m2_t src)
+{
+  vfloat64m2_t a = vreinterpret_f64m2(src);
+  return a;
+}
+
+vfloat64m4_t test_vreinterpret_v_i64m4_f64m4(vint64m4_t src)
+{
+  vfloat64m4_t a = vreinterpret_f64m4(src);
+  return a;
+}
+
+vfloat64m8_t test_vreinterpret_v_i64m8_f64m8(vint64m8_t src)
+{
+  vfloat64m8_t a = vreinterpret_f64m8(src);
+  return a;
+}
+
+vint64m1_t test_vreinterpret_v_u64m1_i64m1(vuint64m1_t src)
+{
+  vint64m1_t a = vreinterpret_i64m1(src);
+  return a;
+}
+
+vint64m2_t test_vreinterpret_v_u64m2_i64m2(vuint64m2_t src)
+{
+  vint64m2_t a = vreinterpret_i64m2(src);
+  return a;
+}
+
+vint64m4_t test_vreinterpret_v_u64m4_i64m4(vuint64m4_t src)
+{
+  vint64m4_t a = vreinterpret_i64m4(src);
+  return a;
+}
+
+vint64m8_t test_vreinterpret_v_u64m8_i64m8(vuint64m8_t src)
+{
+  vint64m8_t a = vreinterpret_i64m8(src);
+  return a;
+}
+
+vfloat64m1_t test_vreinterpret_v_u64m1_f64m1(vuint64m1_t src)
+{
+  vfloat64m1_t a = vreinterpret_f64m1(src);
+  return a;
+}
+
+vfloat64m2_t test_vreinterpret_v_u64m2_f64m2(vuint64m2_t src)
+{
+  vfloat64m2_t a = vreinterpret_f64m2(src);
+  return a;
+}
+
+vfloat64m4_t test_vreinterpret_v_u64m4_f64m4(vuint64m4_t src)
+{
+  vfloat64m4_t a = vreinterpret_f64m4(src);
+  return a;
+}
+
+vfloat64m8_t test_vreinterpret_v_u64m8_f64m8(vuint64m8_t src)
+{
+  vfloat64m8_t a = vreinterpret_f64m8(src);
+  return a;
+}
+
+vint64m1_t test_vreinterpret_v_f64m1_i64m1(vfloat64m1_t src)
+{
+  vint64m1_t a = vreinterpret_i64m1(src);
+  return a;
+}
+
+vint64m2_t test_vreinterpret_v_f64m2_i64m2(vfloat64m2_t src)
+{
+  vint64m2_t a = vreinterpret_i64m2(src);
+  return a;
+}
+
+vint64m4_t test_vreinterpret_v_f64m4_i64m4(vfloat64m4_t src)
+{
+  vint64m4_t a = vreinterpret_i64m4(src);
+  return a;
+}
+
+vint64m8_t test_vreinterpret_v_f64m8_i64m8(vfloat64m8_t src)
+{
+  vint64m8_t a = vreinterpret_i64m8(src);
+  return a;
+}
+
+vuint64m1_t test_vreinterpret_v_f64m1_u64m1(vfloat64m1_t src)
+{
+  vuint64m1_t a = vreinterpret_u64m1(src);
+  return a;
+}
+
+vuint64m2_t test_vreinterpret_v_f64m2_u64m2(vfloat64m2_t src)
+{
+  vuint64m2_t a = vreinterpret_u64m2(src);
+  return a;
+}
+
+vuint64m4_t test_vreinterpret_v_f64m4_u64m4(vfloat64m4_t src)
+{
+  vuint64m4_t a = vreinterpret_u64m4(src);
+  return a;
+}
+
+vuint64m8_t test_vreinterpret_v_f64m8_u64m8(vfloat64m8_t src)
+{
+  vuint64m8_t a = vreinterpret_u64m8(src);
+  return a;
+}
+
+vint16mf4_t test_vreinterpret_v_i8mf4_i16mf4(vint8mf4_t src)
+{
+  vint16mf4_t a = vreinterpret_i16mf4(src);
+  return a;
+}
+
+vint16mf2_t test_vreinterpret_v_i8mf2_i16mf2(vint8mf2_t src)
+{
+  vint16mf2_t a = vreinterpret_i16mf2(src);
+  return a;
+}
+
+vint16m1_t test_vreinterpret_v_i8m1_i16m1(vint8m1_t src)
+{
+  vint16m1_t a = vreinterpret_i16m1(src);
+  return a;
+}
+
+vint16m2_t test_vreinterpret_v_i8m2_i16m2(vint8m2_t src)
+{
+  vint16m2_t a = vreinterpret_i16m2(src);
+  return a;
+}
+
+vint16m4_t test_vreinterpret_v_i8m4_i16m4(vint8m4_t src)
+{
+  vint16m4_t a = vreinterpret_i16m4(src);
+  return a;
+}
+
+vint16m8_t test_vreinterpret_v_i8m8_i16m8(vint8m8_t src)
+{
+  vint16m8_t a = vreinterpret_i16m8(src);
+  return a;
+}
+
+vint32mf2_t test_vreinterpret_v_i8mf2_i32mf2(vint8mf2_t src)
+{
+  vint32mf2_t a = vreinterpret_i32mf2(src);
+  return a;
+}
+
+vint32m1_t test_vreinterpret_v_i8m1_i32m1(vint8m1_t src)
+{
+  vint32m1_t a = vreinterpret_i32m1(src);
+  return a;
+}
+
+vint32m2_t test_vreinterpret_v_i8m2_i32m2(vint8m2_t src)
+{
+  vint32m2_t a = vreinterpret_i32m2(src);
+  return a;
+}
+
+vint32m4_t test_vreinterpret_v_i8m4_i32m4(vint8m4_t src)
+{
+  vint32m4_t a = vreinterpret_i32m4(src);
+  return a;
+}
+
+vint32m8_t test_vreinterpret_v_i8m8_i32m8(vint8m8_t src)
+{
+  vint32m8_t a = vreinterpret_i32m8(src);
+  return a;
+}
+
+vint64m1_t test_vreinterpret_v_i8m1_i64m1(vint8m1_t src)
+{
+  vint64m1_t a = vreinterpret_i64m1(src);
+  return a;
+}
+
+vint64m2_t test_vreinterpret_v_i8m2_i64m2(vint8m2_t src)
+{
+  vint64m2_t a = vreinterpret_i64m2(src);
+  return a;
+}
+
+vint64m4_t test_vreinterpret_v_i8m4_i64m4(vint8m4_t src)
+{
+  vint64m4_t a = vreinterpret_i64m4(src);
+  return a;
+}
+
+vint64m8_t test_vreinterpret_v_i8m8_i64m8(vint8m8_t src)
+{
+  vint64m8_t a = vreinterpret_i64m8(src);
+  return a;
+}
+
+vint8mf4_t test_vreinterpret_v_i16mf4_i8mf4(vint16mf4_t src)
+{
+  vint8mf4_t a = vreinterpret_i8mf4(src);
+  return a;
+}
+
+vint8mf2_t test_vreinterpret_v_i16mf2_i8mf2(vint16mf2_t src)
+{
+  vint8mf2_t a = vreinterpret_i8mf2(src);
+  return a;
+}
+
+vint8m1_t test_vreinterpret_v_i16m1_i8m1(vint16m1_t src)
+{
+  vint8m1_t a = vreinterpret_i8m1(src);
+  return a;
+}
+
+vint8m2_t test_vreinterpret_v_i16m2_i8m2(vint16m2_t src)
+{
+  vint8m2_t a = vreinterpret_i8m2(src);
+  return a;
+}
+
+vint8m4_t test_vreinterpret_v_i16m4_i8m4(vint16m4_t src)
+{
+  vint8m4_t a = vreinterpret_i8m4(src);
+  return a;
+}
+
+vint8m8_t test_vreinterpret_v_i16m8_i8m8(vint16m8_t src)
+{
+  vint8m8_t a = vreinterpret_i8m8(src);
+  return a;
+}
+
+vint32mf2_t test_vreinterpret_v_i16mf2_i32mf2(vint16mf2_t src)
+{
+  vint32mf2_t a = vreinterpret_i32mf2(src);
+  return a;
+}
+
+vint32m1_t test_vreinterpret_v_i16m1_i32m1(vint16m1_t src)
+{
+  vint32m1_t a = vreinterpret_i32m1(src);
+  return a;
+}
+
+vint32m2_t test_vreinterpret_v_i16m2_i32m2(vint16m2_t src)
+{
+  vint32m2_t a = vreinterpret_i32m2(src);
+  return a;
+}
+
+vint32m4_t test_vreinterpret_v_i16m4_i32m4(vint16m4_t src)
+{
+  vint32m4_t a = vreinterpret_i32m4(src);
+  return a;
+}
+
+vint32m8_t test_vreinterpret_v_i16m8_i32m8(vint16m8_t src)
+{
+  vint32m8_t a = vreinterpret_i32m8(src);
+  return a;
+}
+
+vint64m1_t test_vreinterpret_v_i16m1_i64m1(vint16m1_t src)
+{
+  vint64m1_t a = vreinterpret_i64m1(src);
+  return a;
+}
+
+vint64m2_t test_vreinterpret_v_i16m2_i64m2(vint16m2_t src)
+{
+  vint64m2_t a = vreinterpret_i64m2(src);
+  return a;
+}
+
+vint64m4_t test_vreinterpret_v_i16m4_i64m4(vint16m4_t src)
+{
+  vint64m4_t a = vreinterpret_i64m4(src);
+  return a;
+}
+
+vint64m8_t test_vreinterpret_v_i16m8_i64m8(vint16m8_t src)
+{
+  vint64m8_t a = vreinterpret_i64m8(src);
+  return a;
+}
+
+vint8mf2_t test_vreinterpret_v_i32mf2_i8mf2(vint32mf2_t src)
+{
+  vint8mf2_t a = vreinterpret_i8mf2(src);
+  return a;
+}
+
+vint8m1_t test_vreinterpret_v_i32m1_i8m1(vint32m1_t src)
+{
+  vint8m1_t a = vreinterpret_i8m1(src);
+  return a;
+}
+
+vint8m2_t test_vreinterpret_v_i32m2_i8m2(vint32m2_t src)
+{
+  vint8m2_t a = vreinterpret_i8m2(src);
+  return a;
+}
+
+vint8m4_t test_vreinterpret_v_i32m4_i8m4(vint32m4_t src)
+{
+  vint8m4_t a = vreinterpret_i8m4(src);
+  return a;
+}
+
+vint8m8_t test_vreinterpret_v_i32m8_i8m8(vint32m8_t src)
+{
+  vint8m8_t a = vreinterpret_i8m8(src);
+  return a;
+}
+
+vint16mf2_t test_vreinterpret_v_i32mf2_i16mf2(vint32mf2_t src)
+{
+  vint16mf2_t a = vreinterpret_i16mf2(src);
+  return a;
+}
+
+vint16m1_t test_vreinterpret_v_i32m1_i16m1(vint32m1_t src)
+{
+  vint16m1_t a = vreinterpret_i16m1(src);
+  return a;
+}
+
+vint16m2_t test_vreinterpret_v_i32m2_i16m2(vint32m2_t src)
+{
+  vint16m2_t a = vreinterpret_i16m2(src);
+  return a;
+}
+
+vint16m4_t test_vreinterpret_v_i32m4_i16m4(vint32m4_t src)
+{
+  vint16m4_t a = vreinterpret_i16m4(src);
+  return a;
+}
+
+vint16m8_t test_vreinterpret_v_i32m8_i16m8(vint32m8_t src)
+{
+  vint16m8_t a = vreinterpret_i16m8(src);
+  return a;
+}
+
+vint64m1_t test_vreinterpret_v_i32m1_i64m1(vint32m1_t src)
+{
+  vint64m1_t a = vreinterpret_i64m1(src);
+  return a;
+}
+
+vint64m2_t test_vreinterpret_v_i32m2_i64m2(vint32m2_t src)
+{
+  vint64m2_t a = vreinterpret_i64m2(src);
+  return a;
+}
+
+vint64m4_t test_vreinterpret_v_i32m4_i64m4(vint32m4_t src)
+{
+  vint64m4_t a = vreinterpret_i64m4(src);
+  return a;
+}
+
+vint64m8_t test_vreinterpret_v_i32m8_i64m8(vint32m8_t src)
+{
+  vint64m8_t a = vreinterpret_i64m8(src);
+  return a;
+}
+
+vint8m1_t test_vreinterpret_v_i64m1_i8m1(vint64m1_t src)
+{
+  vint8m1_t a = vreinterpret_i8m1(src);
+  return a;
+}
+
+vint8m2_t test_vreinterpret_v_i64m2_i8m2(vint64m2_t src)
+{
+  vint8m2_t a = vreinterpret_i8m2(src);
+  return a;
+}
+
+vint8m4_t test_vreinterpret_v_i64m4_i8m4(vint64m4_t src)
+{
+  vint8m4_t a = vreinterpret_i8m4(src);
+  return a;
+}
+
+vint8m8_t test_vreinterpret_v_i64m8_i8m8(vint64m8_t src)
+{
+  vint8m8_t a = vreinterpret_i8m8(src);
+  return a;
+}
+
+vint16m1_t test_vreinterpret_v_i64m1_i16m1(vint64m1_t src)
+{
+  vint16m1_t a = vreinterpret_i16m1(src);
+  return a;
+}
+
+vint16m2_t test_vreinterpret_v_i64m2_i16m2(vint64m2_t src)
+{
+  vint16m2_t a = vreinterpret_i16m2(src);
+  return a;
+}
+
+vint16m4_t test_vreinterpret_v_i64m4_i16m4(vint64m4_t src)
+{
+  vint16m4_t a = vreinterpret_i16m4(src);
+  return a;
+}
+
+vint16m8_t test_vreinterpret_v_i64m8_i16m8(vint64m8_t src)
+{
+  vint16m8_t a = vreinterpret_i16m8(src);
+  return a;
+}
+
+vint32m1_t test_vreinterpret_v_i64m1_i32m1(vint64m1_t src)
+{
+  vint32m1_t a = vreinterpret_i32m1(src);
+  return a;
+}
+
+vint32m2_t test_vreinterpret_v_i64m2_i32m2(vint64m2_t src)
+{
+  vint32m2_t a = vreinterpret_i32m2(src);
+  return a;
+}
+
+vint32m4_t test_vreinterpret_v_i64m4_i32m4(vint64m4_t src)
+{
+  vint32m4_t a = vreinterpret_i32m4(src);
+  return a;
+}
+
+vint32m8_t test_vreinterpret_v_i64m8_i32m8(vint64m8_t src)
+{
+  vint32m8_t a = vreinterpret_i32m8(src);
+  return a;
+}
+
+vuint16mf4_t test_vreinterpret_v_u8mf4_u16mf4(vuint8mf4_t src)
+{
+  vuint16mf4_t a = vreinterpret_u16mf4(src);
+  return a;
+}
+
+vuint16mf2_t test_vreinterpret_v_u8mf2_u16mf2(vuint8mf2_t src)
+{
+  vuint16mf2_t a = vreinterpret_u16mf2(src);
+  return a;
+}
+
+vuint16m1_t test_vreinterpret_v_u8m1_u16m1(vuint8m1_t src)
+{
+  vuint16m1_t a = vreinterpret_u16m1(src);
+  return a;
+}
+
+vuint16m2_t test_vreinterpret_v_u8m2_u16m2(vuint8m2_t src)
+{
+  vuint16m2_t a = vreinterpret_u16m2(src);
+  return a;
+}
+
+vuint16m4_t test_vreinterpret_v_u8m4_u16m4(vuint8m4_t src)
+{
+  vuint16m4_t a = vreinterpret_u16m4(src);
+  return a;
+}
+
+vuint16m8_t test_vreinterpret_v_u8m8_u16m8(vuint8m8_t src)
+{
+  vuint16m8_t a = vreinterpret_u16m8(src);
+  return a;
+}
+
+vuint32mf2_t test_vreinterpret_v_u8mf2_u32mf2(vuint8mf2_t src)
+{
+  vuint32mf2_t a = vreinterpret_u32mf2(src);
+  return a;
+}
+
+vuint32m1_t test_vreinterpret_v_u8m1_u32m1(vuint8m1_t src)
+{
+  vuint32m1_t a = vreinterpret_u32m1(src);
+  return a;
+}
+
+vuint32m2_t test_vreinterpret_v_u8m2_u32m2(vuint8m2_t src)
+{
+  vuint32m2_t a = vreinterpret_u32m2(src);
+  return a;
+}
+
+vuint32m4_t test_vreinterpret_v_u8m4_u32m4(vuint8m4_t src)
+{
+  vuint32m4_t a = vreinterpret_u32m4(src);
+  return a;
+}
+
+vuint32m8_t test_vreinterpret_v_u8m8_u32m8(vuint8m8_t src)
+{
+  vuint32m8_t a = vreinterpret_u32m8(src);
+  return a;
+}
+
+vuint64m1_t test_vreinterpret_v_u8m1_u64m1(vuint8m1_t src)
+{
+  vuint64m1_t a = vreinterpret_u64m1(src);
+  return a;
+}
+
+vuint64m2_t test_vreinterpret_v_u8m2_u64m2(vuint8m2_t src)
+{
+  vuint64m2_t a = vreinterpret_u64m2(src);
+  return a;
+}
+
+vuint64m4_t test_vreinterpret_v_u8m4_u64m4(vuint8m4_t src)
+{
+  vuint64m4_t a = vreinterpret_u64m4(src);
+  return a;
+}
+
+vuint64m8_t test_vreinterpret_v_u8m8_u64m8(vuint8m8_t src)
+{
+  vuint64m8_t a = vreinterpret_u64m8(src);
+  return a;
+}
+
+vuint8mf4_t test_vreinterpret_v_u16mf4_u8mf4(vuint16mf4_t src)
+{
+  vuint8mf4_t a = vreinterpret_u8mf4(src);
+  return a;
+}
+
+vuint8mf2_t test_vreinterpret_v_u16mf2_u8mf2(vuint16mf2_t src)
+{
+  vuint8mf2_t a = vreinterpret_u8mf2(src);
+  return a;
+}
+
+vuint8m1_t test_vreinterpret_v_u16m1_u8m1(vuint16m1_t src)
+{
+  vuint8m1_t a = vreinterpret_u8m1(src);
+  return a;
+}
+
+vuint8m2_t test_vreinterpret_v_u16m2_u8m2(vuint16m2_t src)
+{
+  vuint8m2_t a = vreinterpret_u8m2(src);
+  return a;
+}
+
+vuint8m4_t test_vreinterpret_v_u16m4_u8m4(vuint16m4_t src)
+{
+  vuint8m4_t a = vreinterpret_u8m4(src);
+  return a;
+}
+
+vuint8m8_t test_vreinterpret_v_u16m8_u8m8(vuint16m8_t src)
+{
+  vuint8m8_t a = vreinterpret_u8m8(src);
+  return a;
+}
+
+vuint32mf2_t test_vreinterpret_v_u16mf2_u32mf2(vuint16mf2_t src)
+{
+  vuint32mf2_t a = vreinterpret_u32mf2(src);
+  return a;
+}
+
+vuint32m1_t test_vreinterpret_v_u16m1_u32m1(vuint16m1_t src)
+{
+  vuint32m1_t a = vreinterpret_u32m1(src);
+  return a;
+}
+
+vuint32m2_t test_vreinterpret_v_u16m2_u32m2(vuint16m2_t src)
+{
+  vuint32m2_t a = vreinterpret_u32m2(src);
+  return a;
+}
+
+vuint32m4_t test_vreinterpret_v_u16m4_u32m4(vuint16m4_t src)
+{
+  vuint32m4_t a = vreinterpret_u32m4(src);
+  return a;
+}
+
+vuint32m8_t test_vreinterpret_v_u16m8_u32m8(vuint16m8_t src)
+{
+  vuint32m8_t a = vreinterpret_u32m8(src);
+  return a;
+}
+
+vuint64m1_t test_vreinterpret_v_u16m1_u64m1(vuint16m1_t src)
+{
+  vuint64m1_t a = vreinterpret_u64m1(src);
+  return a;
+}
+
+vuint64m2_t test_vreinterpret_v_u16m2_u64m2(vuint16m2_t src)
+{
+  vuint64m2_t a = vreinterpret_u64m2(src);
+  return a;
+}
+
+vuint64m4_t test_vreinterpret_v_u16m4_u64m4(vuint16m4_t src)
+{
+  vuint64m4_t a = vreinterpret_u64m4(src);
+  return a;
+}
+
+vuint64m8_t test_vreinterpret_v_u16m8_u64m8(vuint16m8_t src)
+{
+  vuint64m8_t a = vreinterpret_u64m8(src);
+  return a;
+}
+
+vuint8mf2_t test_vreinterpret_v_u32mf2_u8mf2(vuint32mf2_t src)
+{
+  vuint8mf2_t a = vreinterpret_u8mf2(src);
+  return a;
+}
+
+vuint8m1_t test_vreinterpret_v_u32m1_u8m1(vuint32m1_t src)
+{
+  vuint8m1_t a = vreinterpret_u8m1(src);
+  return a;
+}
+
+vuint8m2_t test_vreinterpret_v_u32m2_u8m2(vuint32m2_t src)
+{
+  vuint8m2_t a = vreinterpret_u8m2(src);
+  return a;
+}
+
+vuint8m4_t test_vreinterpret_v_u32m4_u8m4(vuint32m4_t src)
+{
+  vuint8m4_t a = vreinterpret_u8m4(src);
+  return a;
+}
+
+vuint8m8_t test_vreinterpret_v_u32m8_u8m8(vuint32m8_t src)
+{
+  vuint8m8_t a = vreinterpret_u8m8(src);
+  return a;
+}
+
+vuint16mf2_t test_vreinterpret_v_u32mf2_u16mf2(vuint32mf2_t src)
+{
+  vuint16mf2_t a = vreinterpret_u16mf2(src);
+  return a;
+}
+
+vuint16m1_t test_vreinterpret_v_u32m1_u16m1(vuint32m1_t src)
+{
+  vuint16m1_t a = vreinterpret_u16m1(src);
+  return a;
+}
+
+vuint16m2_t test_vreinterpret_v_u32m2_u16m2(vuint32m2_t src)
+{
+  vuint16m2_t a = vreinterpret_u16m2(src);
+  return a;
+}
+
+vuint16m4_t test_vreinterpret_v_u32m4_u16m4(vuint32m4_t src)
+{
+  vuint16m4_t a = vreinterpret_u16m4(src);
+  return a;
+}
+
+vuint16m8_t test_vreinterpret_v_u32m8_u16m8(vuint32m8_t src)
+{
+  vuint16m8_t a = vreinterpret_u16m8(src);
+  return a;
+}
+
+vuint64m1_t test_vreinterpret_v_u32m1_u64m1(vuint32m1_t src)
+{
+  vuint64m1_t a = vreinterpret_u64m1(src);
+  return a;
+}
+
+vuint64m2_t test_vreinterpret_v_u32m2_u64m2(vuint32m2_t src)
+{
+  vuint64m2_t a = vreinterpret_u64m2(src);
+  return a;
+}
+
+vuint64m4_t test_vreinterpret_v_u32m4_u64m4(vuint32m4_t src)
+{
+  vuint64m4_t a = vreinterpret_u64m4(src);
+  return a;
+}
+
+vuint64m8_t test_vreinterpret_v_u32m8_u64m8(vuint32m8_t src)
+{
+  vuint64m8_t a = vreinterpret_u64m8(src);
+  return a;
+}
+
+vuint8m1_t test_vreinterpret_v_u64m1_u8m1(vuint64m1_t src)
+{
+  vuint8m1_t a = vreinterpret_u8m1(src);
+  return a;
+}
+
+vuint8m2_t test_vreinterpret_v_u64m2_u8m2(vuint64m2_t src)
+{
+  vuint8m2_t a = vreinterpret_u8m2(src);
+  return a;
+}
+
+vuint8m4_t test_vreinterpret_v_u64m4_u8m4(vuint64m4_t src)
+{
+  vuint8m4_t a = vreinterpret_u8m4(src);
+  return a;
+}
+
+vuint8m8_t test_vreinterpret_v_u64m8_u8m8(vuint64m8_t src)
+{
+  vuint8m8_t a = vreinterpret_u8m8(src);
+  return a;
+}
+
+vuint16m1_t test_vreinterpret_v_u64m1_u16m1(vuint64m1_t src)
+{
+  vuint16m1_t a = vreinterpret_u16m1(src);
+  return a;
+}
+
+vuint16m2_t test_vreinterpret_v_u64m2_u16m2(vuint64m2_t src)
+{
+  vuint16m2_t a = vreinterpret_u16m2(src);
+  return a;
+}
+
+vuint16m4_t test_vreinterpret_v_u64m4_u16m4(vuint64m4_t src)
+{
+  vuint16m4_t a = vreinterpret_u16m4(src);
+  return a;
+}
+
+vuint16m8_t test_vreinterpret_v_u64m8_u16m8(vuint64m8_t src)
+{
+  vuint16m8_t a = vreinterpret_u16m8(src);
+  return a;
+}
+
+vuint32m1_t test_vreinterpret_v_u64m1_u32m1(vuint64m1_t src)
+{
+  vuint32m1_t a = vreinterpret_u32m1(src);
+  return a;
+}
+
+vuint32m2_t test_vreinterpret_v_u64m2_u32m2(vuint64m2_t src)
+{
+  vuint32m2_t a = vreinterpret_u32m2(src);
+  return a;
+}
+
+vuint32m4_t test_vreinterpret_v_u64m4_u32m4(vuint64m4_t src)
+{
+  vuint32m4_t a = vreinterpret_u32m4(src);
+  return a;
+}
+
+vuint32m8_t test_vreinterpret_v_u64m8_u32m8(vuint64m8_t src)
+{
+  vuint32m8_t a = vreinterpret_u32m8(src);
+  return a;
+}
+
+vint8mf4_t test_vlmul_ext_v_i8mf8_i8mf4(vint8mf8_t op1)
+{
+  vint8mf4_t a = vlmul_ext_i8mf4(op1);
+  return a;
+}
+
+vint8mf2_t test_vlmul_ext_v_i8mf8_i8mf2(vint8mf8_t op1)
+{
+  vint8mf2_t a = vlmul_ext_i8mf2(op1);
+  return a;
+}
+
+vint8m1_t test_vlmul_ext_v_i8mf8_i8m1(vint8mf8_t op1)
+{
+  vint8m1_t a = vlmul_ext_i8m1(op1);
+  return a;
+}
+
+vint8m2_t test_vlmul_ext_v_i8mf8_i8m2(vint8mf8_t op1)
+{
+  vint8m2_t a = vlmul_ext_i8m2(op1);
+  return a;
+}
+
+vint8m4_t test_vlmul_ext_v_i8mf8_i8m4(vint8mf8_t op1)
+{
+  vint8m4_t a = vlmul_ext_i8m4(op1);
+  return a;
+}
+
+vint8m8_t test_vlmul_ext_v_i8mf8_i8m8(vint8mf8_t op1)
+{
+  vint8m8_t a = vlmul_ext_i8m8(op1);
+  return a;
+}
+
+vint8mf2_t test_vlmul_ext_v_i8mf4_i8mf2(vint8mf4_t op1)
+{
+  vint8mf2_t a = vlmul_ext_i8mf2(op1);
+  return a;
+}
+
+vint8m1_t test_vlmul_ext_v_i8mf4_i8m1(vint8mf4_t op1)
+{
+  vint8m1_t a = vlmul_ext_i8m1(op1);
+  return a;
+}
+
+vint8m2_t test_vlmul_ext_v_i8mf4_i8m2(vint8mf4_t op1)
+{
+  vint8m2_t a = vlmul_ext_i8m2(op1);
+  return a;
+}
+
+vint8m4_t test_vlmul_ext_v_i8mf4_i8m4(vint8mf4_t op1)
+{
+  vint8m4_t a = vlmul_ext_i8m4(op1);
+  return a;
+}
+
+vint8m8_t test_vlmul_ext_v_i8mf4_i8m8(vint8mf4_t op1)
+{
+  vint8m8_t a = vlmul_ext_i8m8(op1);
+  return a;
+}
+
+vint8m1_t test_vlmul_ext_v_i8mf2_i8m1(vint8mf2_t op1)
+{
+  vint8m1_t a = vlmul_ext_i8m1(op1);
+  return a;
+}
+
+vint8m2_t test_vlmul_ext_v_i8mf2_i8m2(vint8mf2_t op1)
+{
+  vint8m2_t a = vlmul_ext_i8m2(op1);
+  return a;
+}
+
+vint8m4_t test_vlmul_ext_v_i8mf2_i8m4(vint8mf2_t op1)
+{
+  vint8m4_t a = vlmul_ext_i8m4(op1);
+  return a;
+}
+
+vint8m8_t test_vlmul_ext_v_i8mf2_i8m8(vint8mf2_t op1)
+{
+  vint8m8_t a = vlmul_ext_i8m8(op1);
+  return a;
+}
+
+vint8m2_t test_vlmul_ext_v_i8m1_i8m2(vint8m1_t op1)
+{
+  vint8m2_t a = vlmul_ext_i8m2(op1);
+  return a;
+}
+
+vint8m4_t test_vlmul_ext_v_i8m1_i8m4(vint8m1_t op1)
+{
+  vint8m4_t a = vlmul_ext_i8m4(op1);
+  return a;
+}
+
+vint8m8_t test_vlmul_ext_v_i8m1_i8m8(vint8m1_t op1)
+{
+  vint8m8_t a = vlmul_ext_i8m8(op1);
+  return a;
+}
+
+vint8m4_t test_vlmul_ext_v_i8m2_i8m4(vint8m2_t op1)
+{
+  vint8m4_t a = vlmul_ext_i8m4(op1);
+  return a;
+}
+
+vint8m8_t test_vlmul_ext_v_i8m2_i8m8(vint8m2_t op1)
+{
+  vint8m8_t a = vlmul_ext_i8m8(op1);
+  return a;
+}
+
+vint8m8_t test_vlmul_ext_v_i8m4_i8m8(vint8m4_t op1)
+{
+  vint8m8_t a = vlmul_ext_i8m8(op1);
+  return a;
+}
+
+vint16mf2_t test_vlmul_ext_v_i16mf4_i16mf2(vint16mf4_t op1)
+{
+  vint16mf2_t a = vlmul_ext_i16mf2(op1);
+  return a;
+}
+
+vint16m1_t test_vlmul_ext_v_i16mf4_i16m1(vint16mf4_t op1)
+{
+  vint16m1_t a = vlmul_ext_i16m1(op1);
+  return a;
+}
+
+vint16m2_t test_vlmul_ext_v_i16mf4_i16m2(vint16mf4_t op1)
+{
+  vint16m2_t a = vlmul_ext_i16m2(op1);
+  return a;
+}
+
+vint16m4_t test_vlmul_ext_v_i16mf4_i16m4(vint16mf4_t op1)
+{
+  vint16m4_t a = vlmul_ext_i16m4(op1);
+  return a;
+}
+
+vint16m8_t test_vlmul_ext_v_i16mf4_i16m8(vint16mf4_t op1)
+{
+  vint16m8_t a = vlmul_ext_i16m8(op1);
+  return a;
+}
+
+vint16m1_t test_vlmul_ext_v_i16mf2_i16m1(vint16mf2_t op1)
+{
+  vint16m1_t a = vlmul_ext_i16m1(op1);
+  return a;
+}
+
+vint16m2_t test_vlmul_ext_v_i16mf2_i16m2(vint16mf2_t op1)
+{
+  vint16m2_t a = vlmul_ext_i16m2(op1);
+  return a;
+}
+
+vint16m4_t test_vlmul_ext_v_i16mf2_i16m4(vint16mf2_t op1)
+{
+  vint16m4_t a = vlmul_ext_i16m4(op1);
+  return a;
+}
+
+vint16m8_t test_vlmul_ext_v_i16mf2_i16m8(vint16mf2_t op1)
+{
+  vint16m8_t a = vlmul_ext_i16m8(op1);
+  return a;
+}
+
+vint16m2_t test_vlmul_ext_v_i16m1_i16m2(vint16m1_t op1)
+{
+  vint16m2_t a = vlmul_ext_i16m2(op1);
+  return a;
+}
+
+vint16m4_t test_vlmul_ext_v_i16m1_i16m4(vint16m1_t op1)
+{
+  vint16m4_t a = vlmul_ext_i16m4(op1);
+  return a;
+}
+
+vint16m8_t test_vlmul_ext_v_i16m1_i16m8(vint16m1_t op1)
+{
+  vint16m8_t a = vlmul_ext_i16m8(op1);
+  return a;
+}
+
+vint16m4_t test_vlmul_ext_v_i16m2_i16m4(vint16m2_t op1)
+{
+  vint16m4_t a = vlmul_ext_i16m4(op1);
+  return a;
+}
+
+vint16m8_t test_vlmul_ext_v_i16m2_i16m8(vint16m2_t op1)
+{
+  vint16m8_t a = vlmul_ext_i16m8(op1);
+  return a;
+}
+
+vint16m8_t test_vlmul_ext_v_i16m4_i16m8(vint16m4_t op1)
+{
+  vint16m8_t a = vlmul_ext_i16m8(op1);
+  return a;
+}
+
+vint32m1_t test_vlmul_ext_v_i32mf2_i32m1(vint32mf2_t op1)
+{
+  vint32m1_t a = vlmul_ext_i32m1(op1);
+  return a;
+}
+
+vint32m2_t test_vlmul_ext_v_i32mf2_i32m2(vint32mf2_t op1)
+{
+  vint32m2_t a = vlmul_ext_i32m2(op1);
+  return a;
+}
+
+vint32m4_t test_vlmul_ext_v_i32mf2_i32m4(vint32mf2_t op1)
+{
+  vint32m4_t a = vlmul_ext_i32m4(op1);
+  return a;
+}
+
+vint32m8_t test_vlmul_ext_v_i32mf2_i32m8(vint32mf2_t op1)
+{
+  vint32m8_t a = vlmul_ext_i32m8(op1);
+  return a;
+}
+
+vint32m2_t test_vlmul_ext_v_i32m1_i32m2(vint32m1_t op1)
+{
+  vint32m2_t a = vlmul_ext_i32m2(op1);
+  return a;
+}
+
+vint32m4_t test_vlmul_ext_v_i32m1_i32m4(vint32m1_t op1)
+{
+  vint32m4_t a = vlmul_ext_i32m4(op1);
+  return a;
+}
+
+vint32m8_t test_vlmul_ext_v_i32m1_i32m8(vint32m1_t op1)
+{
+  vint32m8_t a = vlmul_ext_i32m8(op1);
+  return a;
+}
+
+vint32m4_t test_vlmul_ext_v_i32m2_i32m4(vint32m2_t op1)
+{
+  vint32m4_t a = vlmul_ext_i32m4(op1);
+  return a;
+}
+
+vint32m8_t test_vlmul_ext_v_i32m2_i32m8(vint32m2_t op1)
+{
+  vint32m8_t a = vlmul_ext_i32m8(op1);
+  return a;
+}
+
+vint32m8_t test_vlmul_ext_v_i32m4_i32m8(vint32m4_t op1)
+{
+  vint32m8_t a = vlmul_ext_i32m8(op1);
+  return a;
+}
+
+vint64m2_t test_vlmul_ext_v_i64m1_i64m2(vint64m1_t op1)
+{
+  vint64m2_t a = vlmul_ext_i64m2(op1);
+  return a;
+}
+
+vint64m4_t test_vlmul_ext_v_i64m1_i64m4(vint64m1_t op1)
+{
+  vint64m4_t a = vlmul_ext_i64m4(op1);
+  return a;
+}
+
+vint64m8_t test_vlmul_ext_v_i64m1_i64m8(vint64m1_t op1)
+{
+  vint64m8_t a = vlmul_ext_i64m8(op1);
+  return a;
+}
+
+vint64m4_t test_vlmul_ext_v_i64m2_i64m4(vint64m2_t op1)
+{
+  vint64m4_t a = vlmul_ext_i64m4(op1);
+  return a;
+}
+
+vint64m8_t test_vlmul_ext_v_i64m2_i64m8(vint64m2_t op1)
+{
+  vint64m8_t a = vlmul_ext_i64m8(op1);
+  return a;
+}
+
+vint64m8_t test_vlmul_ext_v_i64m4_i64m8(vint64m4_t op1)
+{
+  vint64m8_t a = vlmul_ext_i64m8(op1);
+  return a;
+}
+
+vuint8mf4_t test_vlmul_ext_v_u8mf8_u8mf4(vuint8mf8_t op1)
+{
+  vuint8mf4_t a = vlmul_ext_u8mf4(op1);
+  return a;
+}
+
+vuint8mf2_t test_vlmul_ext_v_u8mf8_u8mf2(vuint8mf8_t op1)
+{
+  vuint8mf2_t a = vlmul_ext_u8mf2(op1);
+  return a;
+}
+
+vuint8m1_t test_vlmul_ext_v_u8mf8_u8m1(vuint8mf8_t op1)
+{
+  vuint8m1_t a = vlmul_ext_u8m1(op1);
+  return a;
+}
+
+vuint8m2_t test_vlmul_ext_v_u8mf8_u8m2(vuint8mf8_t op1)
+{
+  vuint8m2_t a = vlmul_ext_u8m2(op1);
+  return a;
+}
+
+vuint8m4_t test_vlmul_ext_v_u8mf8_u8m4(vuint8mf8_t op1)
+{
+  vuint8m4_t a = vlmul_ext_u8m4(op1);
+  return a;
+}
+
+vuint8m8_t test_vlmul_ext_v_u8mf8_u8m8(vuint8mf8_t op1)
+{
+  vuint8m8_t a = vlmul_ext_u8m8(op1);
+  return a;
+}
+
+vuint8mf2_t test_vlmul_ext_v_u8mf4_u8mf2(vuint8mf4_t op1)
+{
+  vuint8mf2_t a = vlmul_ext_u8mf2(op1);
+  return a;
+}
+
+vuint8m1_t test_vlmul_ext_v_u8mf4_u8m1(vuint8mf4_t op1)
+{
+  vuint8m1_t a = vlmul_ext_u8m1(op1);
+  return a;
+}
+
+vuint8m2_t test_vlmul_ext_v_u8mf4_u8m2(vuint8mf4_t op1)
+{
+  vuint8m2_t a = vlmul_ext_u8m2(op1);
+  return a;
+}
+
+vuint8m4_t test_vlmul_ext_v_u8mf4_u8m4(vuint8mf4_t op1)
+{
+  vuint8m4_t a = vlmul_ext_u8m4(op1);
+  return a;
+}
+
+vuint8m8_t test_vlmul_ext_v_u8mf4_u8m8(vuint8mf4_t op1)
+{
+  vuint8m8_t a = vlmul_ext_u8m8(op1);
+  return a;
+}
+
+vuint8m1_t test_vlmul_ext_v_u8mf2_u8m1(vuint8mf2_t op1)
+{
+  vuint8m1_t a = vlmul_ext_u8m1(op1);
+  return a;
+}
+
+vuint8m2_t test_vlmul_ext_v_u8mf2_u8m2(vuint8mf2_t op1)
+{
+  vuint8m2_t a = vlmul_ext_u8m2(op1);
+  return a;
+}
+
+vuint8m4_t test_vlmul_ext_v_u8mf2_u8m4(vuint8mf2_t op1)
+{
+  vuint8m4_t a = vlmul_ext_u8m4(op1);
+  return a;
+}
+
+vuint8m8_t test_vlmul_ext_v_u8mf2_u8m8(vuint8mf2_t op1)
+{
+  vuint8m8_t a = vlmul_ext_u8m8(op1);
+  return a;
+}
+
+vuint8m2_t test_vlmul_ext_v_u8m1_u8m2(vuint8m1_t op1)
+{
+  vuint8m2_t a = vlmul_ext_u8m2(op1);
+  return a;
+}
+
+vuint8m4_t test_vlmul_ext_v_u8m1_u8m4(vuint8m1_t op1)
+{
+  vuint8m4_t a = vlmul_ext_u8m4(op1);
+  return a;
+}
+
+vuint8m8_t test_vlmul_ext_v_u8m1_u8m8(vuint8m1_t op1)
+{
+  vuint8m8_t a = vlmul_ext_u8m8(op1);
+  return a;
+}
+
+vuint8m4_t test_vlmul_ext_v_u8m2_u8m4(vuint8m2_t op1)
+{
+  vuint8m4_t a = vlmul_ext_u8m4(op1);
+  return a;
+}
+
+vuint8m8_t test_vlmul_ext_v_u8m2_u8m8(vuint8m2_t op1)
+{
+  vuint8m8_t a = vlmul_ext_u8m8(op1);
+  return a;
+}
+
+vuint8m8_t test_vlmul_ext_v_u8m4_u8m8(vuint8m4_t op1)
+{
+  vuint8m8_t a = vlmul_ext_u8m8(op1);
+  return a;
+}
+
+vuint16mf2_t test_vlmul_ext_v_u16mf4_u16mf2(vuint16mf4_t op1)
+{
+  vuint16mf2_t a = vlmul_ext_u16mf2(op1);
+  return a;
+}
+
+vuint16m1_t test_vlmul_ext_v_u16mf4_u16m1(vuint16mf4_t op1)
+{
+  vuint16m1_t a = vlmul_ext_u16m1(op1);
+  return a;
+}
+
+vuint16m2_t test_vlmul_ext_v_u16mf4_u16m2(vuint16mf4_t op1)
+{
+  vuint16m2_t a = vlmul_ext_u16m2(op1);
+  return a;
+}
+
+vuint16m4_t test_vlmul_ext_v_u16mf4_u16m4(vuint16mf4_t op1)
+{
+  vuint16m4_t a = vlmul_ext_u16m4(op1);
+  return a;
+}
+
+vuint16m8_t test_vlmul_ext_v_u16mf4_u16m8(vuint16mf4_t op1)
+{
+  vuint16m8_t a = vlmul_ext_u16m8(op1);
+  return a;
+}
+
+vuint16m1_t test_vlmul_ext_v_u16mf2_u16m1(vuint16mf2_t op1)
+{
+  vuint16m1_t a = vlmul_ext_u16m1(op1);
+  return a;
+}
+
+vuint16m2_t test_vlmul_ext_v_u16mf2_u16m2(vuint16mf2_t op1)
+{
+  vuint16m2_t a = vlmul_ext_u16m2(op1);
+  return a;
+}
+
+vuint16m4_t test_vlmul_ext_v_u16mf2_u16m4(vuint16mf2_t op1)
+{
+  vuint16m4_t a = vlmul_ext_u16m4(op1);
+  return a;
+}
+
+vuint16m8_t test_vlmul_ext_v_u16mf2_u16m8(vuint16mf2_t op1)
+{
+  vuint16m8_t a = vlmul_ext_u16m8(op1);
+  return a;
+}
+
+vuint16m2_t test_vlmul_ext_v_u16m1_u16m2(vuint16m1_t op1)
+{
+  vuint16m2_t a = vlmul_ext_u16m2(op1);
+  return a;
+}
+
+vuint16m4_t test_vlmul_ext_v_u16m1_u16m4(vuint16m1_t op1)
+{
+  vuint16m4_t a = vlmul_ext_u16m4(op1);
+  return a;
+}
+
+vuint16m8_t test_vlmul_ext_v_u16m1_u16m8(vuint16m1_t op1)
+{
+  vuint16m8_t a = vlmul_ext_u16m8(op1);
+  return a;
+}
+
+vuint16m4_t test_vlmul_ext_v_u16m2_u16m4(vuint16m2_t op1)
+{
+  vuint16m4_t a = vlmul_ext_u16m4(op1);
+  return a;
+}
+
+vuint16m8_t test_vlmul_ext_v_u16m2_u16m8(vuint16m2_t op1)
+{
+  vuint16m8_t a = vlmul_ext_u16m8(op1);
+  return a;
+}
+
+vuint16m8_t test_vlmul_ext_v_u16m4_u16m8(vuint16m4_t op1)
+{
+  vuint16m8_t a = vlmul_ext_u16m8(op1);
+  return a;
+}
+
+vuint32m1_t test_vlmul_ext_v_u32mf2_u32m1(vuint32mf2_t op1)
+{
+  vuint32m1_t a = vlmul_ext_u32m1(op1);
+  return a;
+}
+
+vuint32m2_t test_vlmul_ext_v_u32mf2_u32m2(vuint32mf2_t op1)
+{
+  vuint32m2_t a = vlmul_ext_u32m2(op1);
+  return a;
+}
+
+vuint32m4_t test_vlmul_ext_v_u32mf2_u32m4(vuint32mf2_t op1)
+{
+  vuint32m4_t a = vlmul_ext_u32m4(op1);
+  return a;
+}
+
+vuint32m8_t test_vlmul_ext_v_u32mf2_u32m8(vuint32mf2_t op1)
+{
+  vuint32m8_t a = vlmul_ext_u32m8(op1);
+  return a;
+}
+
+vuint32m2_t test_vlmul_ext_v_u32m1_u32m2(vuint32m1_t op1)
+{
+  vuint32m2_t a = vlmul_ext_u32m2(op1);
+  return a;
+}
+
+vuint32m4_t test_vlmul_ext_v_u32m1_u32m4(vuint32m1_t op1)
+{
+  vuint32m4_t a = vlmul_ext_u32m4(op1);
+  return a;
+}
+
+vuint32m8_t test_vlmul_ext_v_u32m1_u32m8(vuint32m1_t op1)
+{
+  vuint32m8_t a = vlmul_ext_u32m8(op1);
+  return a;
+}
+
+vuint32m4_t test_vlmul_ext_v_u32m2_u32m4(vuint32m2_t op1)
+{
+  vuint32m4_t a = vlmul_ext_u32m4(op1);
+  return a;
+}
+
+vuint32m8_t test_vlmul_ext_v_u32m2_u32m8(vuint32m2_t op1)
+{
+  vuint32m8_t a = vlmul_ext_u32m8(op1);
+  return a;
+}
+
+vuint32m8_t test_vlmul_ext_v_u32m4_u32m8(vuint32m4_t op1)
+{
+  vuint32m8_t a = vlmul_ext_u32m8(op1);
+  return a;
+}
+
+vuint64m2_t test_vlmul_ext_v_u64m1_u64m2(vuint64m1_t op1)
+{
+  vuint64m2_t a = vlmul_ext_u64m2(op1);
+  return a;
+}
+
+vuint64m4_t test_vlmul_ext_v_u64m1_u64m4(vuint64m1_t op1)
+{
+  vuint64m4_t a = vlmul_ext_u64m4(op1);
+  return a;
+}
+
+vuint64m8_t test_vlmul_ext_v_u64m1_u64m8(vuint64m1_t op1)
+{
+  vuint64m8_t a = vlmul_ext_u64m8(op1);
+  return a;
+}
+
+vuint64m4_t test_vlmul_ext_v_u64m2_u64m4(vuint64m2_t op1)
+{
+  vuint64m4_t a = vlmul_ext_u64m4(op1);
+  return a;
+}
+
+vuint64m8_t test_vlmul_ext_v_u64m2_u64m8(vuint64m2_t op1)
+{
+  vuint64m8_t a = vlmul_ext_u64m8(op1);
+  return a;
+}
+
+vuint64m8_t test_vlmul_ext_v_u64m4_u64m8(vuint64m4_t op1)
+{
+  vuint64m8_t a = vlmul_ext_u64m8(op1);
+  return a;
+}
+
+vfloat32m1_t test_vlmul_ext_v_f32mf2_f32m1(vfloat32mf2_t op1)
+{
+  vfloat32m1_t a = vlmul_ext_f32m1(op1);
+  return a;
+}
+
+vfloat32m2_t test_vlmul_ext_v_f32mf2_f32m2(vfloat32mf2_t op1)
+{
+  vfloat32m2_t a = vlmul_ext_f32m2(op1);
+  return a;
+}
+
+vfloat32m4_t test_vlmul_ext_v_f32mf2_f32m4(vfloat32mf2_t op1)
+{
+  vfloat32m4_t a = vlmul_ext_f32m4(op1);
+  return a;
+}
+
+vfloat32m8_t test_vlmul_ext_v_f32mf2_f32m8(vfloat32mf2_t op1)
+{
+  vfloat32m8_t a = vlmul_ext_f32m8(op1);
+  return a;
+}
+
+vfloat32m2_t test_vlmul_ext_v_f32m1_f32m2(vfloat32m1_t op1)
+{
+  vfloat32m2_t a = vlmul_ext_f32m2(op1);
+  return a;
+}
+
+vfloat32m4_t test_vlmul_ext_v_f32m1_f32m4(vfloat32m1_t op1)
+{
+  vfloat32m4_t a = vlmul_ext_f32m4(op1);
+  return a;
+}
+
+vfloat32m8_t test_vlmul_ext_v_f32m1_f32m8(vfloat32m1_t op1)
+{
+  vfloat32m8_t a = vlmul_ext_f32m8(op1);
+  return a;
+}
+
+vfloat32m4_t test_vlmul_ext_v_f32m2_f32m4(vfloat32m2_t op1)
+{
+  vfloat32m4_t a = vlmul_ext_f32m4(op1);
+  return a;
+}
+
+vfloat32m8_t test_vlmul_ext_v_f32m2_f32m8(vfloat32m2_t op1)
+{
+  vfloat32m8_t a = vlmul_ext_f32m8(op1);
+  return a;
+}
+
+vfloat32m8_t test_vlmul_ext_v_f32m4_f32m8(vfloat32m4_t op1)
+{
+  vfloat32m8_t a = vlmul_ext_f32m8(op1);
+  return a;
+}
+
+vfloat64m2_t test_vlmul_ext_v_f64m1_f64m2(vfloat64m1_t op1)
+{
+  vfloat64m2_t a = vlmul_ext_f64m2(op1);
+  return a;
+}
+
+vfloat64m4_t test_vlmul_ext_v_f64m1_f64m4(vfloat64m1_t op1)
+{
+  vfloat64m4_t a = vlmul_ext_f64m4(op1);
+  return a;
+}
+
+vfloat64m8_t test_vlmul_ext_v_f64m1_f64m8(vfloat64m1_t op1)
+{
+  vfloat64m8_t a = vlmul_ext_f64m8(op1);
+  return a;
+}
+
+vfloat64m4_t test_vlmul_ext_v_f64m2_f64m4(vfloat64m2_t op1)
+{
+  vfloat64m4_t a = vlmul_ext_f64m4(op1);
+  return a;
+}
+
+vfloat64m8_t test_vlmul_ext_v_f64m2_f64m8(vfloat64m2_t op1)
+{
+  vfloat64m8_t a = vlmul_ext_f64m8(op1);
+  return a;
+}
+
+vfloat64m8_t test_vlmul_ext_v_f64m4_f64m8(vfloat64m4_t op1)
+{
+  vfloat64m8_t a = vlmul_ext_f64m8(op1);
+  return a;
+}
+
+vint8mf8_t test_vlmul_trunc_v_i8mf4_i8mf8(vint8mf4_t op1)
+{
+  vint8mf8_t a = vlmul_trunc_i8mf8(op1);
+  return a;
+}
+
+vint8mf8_t test_vlmul_trunc_v_i8mf2_i8mf8(vint8mf2_t op1)
+{
+  vint8mf8_t a = vlmul_trunc_i8mf8(op1);
+  return a;
+}
+
+vint8mf4_t test_vlmul_trunc_v_i8mf2_i8mf4(vint8mf2_t op1)
+{
+  vint8mf4_t a = vlmul_trunc_i8mf4(op1);
+  return a;
+}
+
+vint8mf8_t test_vlmul_trunc_v_i8m1_i8mf8(vint8m1_t op1)
+{
+  vint8mf8_t a = vlmul_trunc_i8mf8(op1);
+  return a;
+}
+
+vint8mf4_t test_vlmul_trunc_v_i8m1_i8mf4(vint8m1_t op1)
+{
+  vint8mf4_t a = vlmul_trunc_i8mf4(op1);
+  return a;
+}
+
+vint8mf2_t test_vlmul_trunc_v_i8m1_i8mf2(vint8m1_t op1)
+{
+  vint8mf2_t a = vlmul_trunc_i8mf2(op1);
+  return a;
+}
+
+vint8mf8_t test_vlmul_trunc_v_i8m2_i8mf8(vint8m2_t op1)
+{
+  vint8mf8_t a = vlmul_trunc_i8mf8(op1);
+  return a;
+}
+
+vint8mf4_t test_vlmul_trunc_v_i8m2_i8mf4(vint8m2_t op1)
+{
+  vint8mf4_t a = vlmul_trunc_i8mf4(op1);
+  return a;
+}
+
+vint8mf2_t test_vlmul_trunc_v_i8m2_i8mf2(vint8m2_t op1)
+{
+  vint8mf2_t a = vlmul_trunc_i8mf2(op1);
+  return a;
+}
+
+vint8m1_t test_vlmul_trunc_v_i8m2_i8m1(vint8m2_t op1)
+{
+  vint8m1_t a = vlmul_trunc_i8m1(op1);
+  return a;
+}
+
+vint8mf8_t test_vlmul_trunc_v_i8m4_i8mf8(vint8m4_t op1)
+{
+  vint8mf8_t a = vlmul_trunc_i8mf8(op1);
+  return a;
+}
+
+vint8mf4_t test_vlmul_trunc_v_i8m4_i8mf4(vint8m4_t op1)
+{
+  vint8mf4_t a = vlmul_trunc_i8mf4(op1);
+  return a;
+}
+
+vint8mf2_t test_vlmul_trunc_v_i8m4_i8mf2(vint8m4_t op1)
+{
+  vint8mf2_t a = vlmul_trunc_i8mf2(op1);
+  return a;
+}
+
+vint8m1_t test_vlmul_trunc_v_i8m4_i8m1(vint8m4_t op1)
+{
+  vint8m1_t a = vlmul_trunc_i8m1(op1);
+  return a;
+}
+
+vint8m2_t test_vlmul_trunc_v_i8m4_i8m2(vint8m4_t op1)
+{
+  vint8m2_t a = vlmul_trunc_i8m2(op1);
+  return a;
+}
+
+vint8mf8_t test_vlmul_trunc_v_i8m8_i8mf8(vint8m8_t op1)
+{
+  vint8mf8_t a = vlmul_trunc_i8mf8(op1);
+  return a;
+}
+
+vint8mf4_t test_vlmul_trunc_v_i8m8_i8mf4(vint8m8_t op1)
+{
+  vint8mf4_t a = vlmul_trunc_i8mf4(op1);
+  return a;
+}
+
+vint8mf2_t test_vlmul_trunc_v_i8m8_i8mf2(vint8m8_t op1)
+{
+  vint8mf2_t a = vlmul_trunc_i8mf2(op1);
+  return a;
+}
+
+vint8m1_t test_vlmul_trunc_v_i8m8_i8m1(vint8m8_t op1)
+{
+  vint8m1_t a = vlmul_trunc_i8m1(op1);
+  return a;
+}
+
+vint8m2_t test_vlmul_trunc_v_i8m8_i8m2(vint8m8_t op1)
+{
+  vint8m2_t a = vlmul_trunc_i8m2(op1);
+  return a;
+}
+
+vint8m4_t test_vlmul_trunc_v_i8m8_i8m4(vint8m8_t op1)
+{
+  vint8m4_t a = vlmul_trunc_i8m4(op1);
+  return a;
+}
+
+vint16mf4_t test_vlmul_trunc_v_i16mf2_i16mf4(vint16mf2_t op1)
+{
+  vint16mf4_t a = vlmul_trunc_i16mf4(op1);
+  return a;
+}
+
+vint16mf4_t test_vlmul_trunc_v_i16m1_i16mf4(vint16m1_t op1)
+{
+  vint16mf4_t a = vlmul_trunc_i16mf4(op1);
+  return a;
+}
+
+vint16mf2_t test_vlmul_trunc_v_i16m1_i16mf2(vint16m1_t op1)
+{
+  vint16mf2_t a = vlmul_trunc_i16mf2(op1);
+  return a;
+}
+
+vint16mf4_t test_vlmul_trunc_v_i16m2_i16mf4(vint16m2_t op1)
+{
+  vint16mf4_t a = vlmul_trunc_i16mf4(op1);
+  return a;
+}
+
+vint16mf2_t test_vlmul_trunc_v_i16m2_i16mf2(vint16m2_t op1)
+{
+  vint16mf2_t a = vlmul_trunc_i16mf2(op1);
+  return a;
+}
+
+vint16m1_t test_vlmul_trunc_v_i16m2_i16m1(vint16m2_t op1)
+{
+  vint16m1_t a = vlmul_trunc_i16m1(op1);
+  return a;
+}
+
+vint16mf4_t test_vlmul_trunc_v_i16m4_i16mf4(vint16m4_t op1)
+{
+  vint16mf4_t a = vlmul_trunc_i16mf4(op1);
+  return a;
+}
+
+vint16mf2_t test_vlmul_trunc_v_i16m4_i16mf2(vint16m4_t op1)
+{
+  vint16mf2_t a = vlmul_trunc_i16mf2(op1);
+  return a;
+}
+
+vint16m1_t test_vlmul_trunc_v_i16m4_i16m1(vint16m4_t op1)
+{
+  vint16m1_t a = vlmul_trunc_i16m1(op1);
+  return a;
+}
+
+vint16m2_t test_vlmul_trunc_v_i16m4_i16m2(vint16m4_t op1)
+{
+  vint16m2_t a = vlmul_trunc_i16m2(op1);
+  return a;
+}
+
+vint16mf4_t test_vlmul_trunc_v_i16m8_i16mf4(vint16m8_t op1)
+{
+  vint16mf4_t a = vlmul_trunc_i16mf4(op1);
+  return a;
+}
+
+vint16mf2_t test_vlmul_trunc_v_i16m8_i16mf2(vint16m8_t op1)
+{
+  vint16mf2_t a = vlmul_trunc_i16mf2(op1);
+  return a;
+}
+
+vint16m1_t test_vlmul_trunc_v_i16m8_i16m1(vint16m8_t op1)
+{
+  vint16m1_t a = vlmul_trunc_i16m1(op1);
+  return a;
+}
+
+vint16m2_t test_vlmul_trunc_v_i16m8_i16m2(vint16m8_t op1)
+{
+  vint16m2_t a = vlmul_trunc_i16m2(op1);
+  return a;
+}
+
+vint16m4_t test_vlmul_trunc_v_i16m8_i16m4(vint16m8_t op1)
+{
+  vint16m4_t a = vlmul_trunc_i16m4(op1);
+  return a;
+}
+
+vint32mf2_t test_vlmul_trunc_v_i32m1_i32mf2(vint32m1_t op1)
+{
+  vint32mf2_t a = vlmul_trunc_i32mf2(op1);
+  return a;
+}
+
+vint32mf2_t test_vlmul_trunc_v_i32m2_i32mf2(vint32m2_t op1)
+{
+  vint32mf2_t a = vlmul_trunc_i32mf2(op1);
+  return a;
+}
+
+vint32m1_t test_vlmul_trunc_v_i32m2_i32m1(vint32m2_t op1)
+{
+  vint32m1_t a = vlmul_trunc_i32m1(op1);
+  return a;
+}
+
+vint32mf2_t test_vlmul_trunc_v_i32m4_i32mf2(vint32m4_t op1)
+{
+  vint32mf2_t a = vlmul_trunc_i32mf2(op1);
+  return a;
+}
+
+vint32m1_t test_vlmul_trunc_v_i32m4_i32m1(vint32m4_t op1)
+{
+  vint32m1_t a = vlmul_trunc_i32m1(op1);
+  return a;
+}
+
+vint32m2_t test_vlmul_trunc_v_i32m4_i32m2(vint32m4_t op1)
+{
+  vint32m2_t a = vlmul_trunc_i32m2(op1);
+  return a;
+}
+
+vint32mf2_t test_vlmul_trunc_v_i32m8_i32mf2(vint32m8_t op1)
+{
+  vint32mf2_t a = vlmul_trunc_i32mf2(op1);
+  return a;
+}
+
+vint32m1_t test_vlmul_trunc_v_i32m8_i32m1(vint32m8_t op1)
+{
+  vint32m1_t a = vlmul_trunc_i32m1(op1);
+  return a;
+}
+
+vint32m2_t test_vlmul_trunc_v_i32m8_i32m2(vint32m8_t op1)
+{
+  vint32m2_t a = vlmul_trunc_i32m2(op1);
+  return a;
+}
+
+vint32m4_t test_vlmul_trunc_v_i32m8_i32m4(vint32m8_t op1)
+{
+  vint32m4_t a = vlmul_trunc_i32m4(op1);
+  return a;
+}
+
+vint64m1_t test_vlmul_trunc_v_i64m2_i64m1(vint64m2_t op1)
+{
+  vint64m1_t a = vlmul_trunc_i64m1(op1);
+  return a;
+}
+
+vint64m1_t test_vlmul_trunc_v_i64m4_i64m1(vint64m4_t op1)
+{
+  vint64m1_t a = vlmul_trunc_i64m1(op1);
+  return a;
+}
+
+vint64m2_t test_vlmul_trunc_v_i64m4_i64m2(vint64m4_t op1)
+{
+  vint64m2_t a = vlmul_trunc_i64m2(op1);
+  return a;
+}
+
+vint64m1_t test_vlmul_trunc_v_i64m8_i64m1(vint64m8_t op1)
+{
+  vint64m1_t a = vlmul_trunc_i64m1(op1);
+  return a;
+}
+
+vint64m2_t test_vlmul_trunc_v_i64m8_i64m2(vint64m8_t op1)
+{
+  vint64m2_t a = vlmul_trunc_i64m2(op1);
+  return a;
+}
+
+vint64m4_t test_vlmul_trunc_v_i64m8_i64m4(vint64m8_t op1)
+{
+  vint64m4_t a = vlmul_trunc_i64m4(op1);
+  return a;
+}
+
+vuint8mf8_t test_vlmul_trunc_v_u8mf4_u8mf8(vuint8mf4_t op1)
+{
+  vuint8mf8_t a = vlmul_trunc_u8mf8(op1);
+  return a;
+}
+
+vuint8mf8_t test_vlmul_trunc_v_u8mf2_u8mf8(vuint8mf2_t op1)
+{
+  vuint8mf8_t a = vlmul_trunc_u8mf8(op1);
+  return a;
+}
+
+vuint8mf4_t test_vlmul_trunc_v_u8mf2_u8mf4(vuint8mf2_t op1)
+{
+  vuint8mf4_t a = vlmul_trunc_u8mf4(op1);
+  return a;
+}
+
+vuint8mf8_t test_vlmul_trunc_v_u8m1_u8mf8(vuint8m1_t op1)
+{
+  vuint8mf8_t a = vlmul_trunc_u8mf8(op1);
+  return a;
+}
+
+vuint8mf4_t test_vlmul_trunc_v_u8m1_u8mf4(vuint8m1_t op1)
+{
+  vuint8mf4_t a = vlmul_trunc_u8mf4(op1);
+  return a;
+}
+
+vuint8mf2_t test_vlmul_trunc_v_u8m1_u8mf2(vuint8m1_t op1)
+{
+  vuint8mf2_t a = vlmul_trunc_u8mf2(op1);
+  return a;
+}
+
+vuint8mf8_t test_vlmul_trunc_v_u8m2_u8mf8(vuint8m2_t op1)
+{
+  vuint8mf8_t a = vlmul_trunc_u8mf8(op1);
+  return a;
+}
+
+vuint8mf4_t test_vlmul_trunc_v_u8m2_u8mf4(vuint8m2_t op1)
+{
+  vuint8mf4_t a = vlmul_trunc_u8mf4(op1);
+  return a;
+}
+
+vuint8mf2_t test_vlmul_trunc_v_u8m2_u8mf2(vuint8m2_t op1)
+{
+  vuint8mf2_t a = vlmul_trunc_u8mf2(op1);
+  return a;
+}
+
+vuint8m1_t test_vlmul_trunc_v_u8m2_u8m1(vuint8m2_t op1)
+{
+  vuint8m1_t a = vlmul_trunc_u8m1(op1);
+  return a;
+}
+
+vuint8mf8_t test_vlmul_trunc_v_u8m4_u8mf8(vuint8m4_t op1)
+{
+  vuint8mf8_t a = vlmul_trunc_u8mf8(op1);
+  return a;
+}
+
+vuint8mf4_t test_vlmul_trunc_v_u8m4_u8mf4(vuint8m4_t op1)
+{
+  vuint8mf4_t a = vlmul_trunc_u8mf4(op1);
+  return a;
+}
+
+vuint8mf2_t test_vlmul_trunc_v_u8m4_u8mf2(vuint8m4_t op1)
+{
+  vuint8mf2_t a = vlmul_trunc_u8mf2(op1);
+  return a;
+}
+
+vuint8m1_t test_vlmul_trunc_v_u8m4_u8m1(vuint8m4_t op1)
+{
+  vuint8m1_t a = vlmul_trunc_u8m1(op1);
+  return a;
+}
+
+vuint8m2_t test_vlmul_trunc_v_u8m4_u8m2(vuint8m4_t op1)
+{
+  vuint8m2_t a = vlmul_trunc_u8m2(op1);
+  return a;
+}
+
+vuint8mf8_t test_vlmul_trunc_v_u8m8_u8mf8(vuint8m8_t op1)
+{
+  vuint8mf8_t a = vlmul_trunc_u8mf8(op1);
+  return a;
+}
+
+vuint8mf4_t test_vlmul_trunc_v_u8m8_u8mf4(vuint8m8_t op1)
+{
+  vuint8mf4_t a = vlmul_trunc_u8mf4(op1);
+  return a;
+}
+
+vuint8mf2_t test_vlmul_trunc_v_u8m8_u8mf2(vuint8m8_t op1)
+{
+  vuint8mf2_t a = vlmul_trunc_u8mf2(op1);
+  return a;
+}
+
+vuint8m1_t test_vlmul_trunc_v_u8m8_u8m1(vuint8m8_t op1)
+{
+  vuint8m1_t a = vlmul_trunc_u8m1(op1);
+  return a;
+}
+
+vuint8m2_t test_vlmul_trunc_v_u8m8_u8m2(vuint8m8_t op1)
+{
+  vuint8m2_t a = vlmul_trunc_u8m2(op1);
+  return a;
+}
+
+vuint8m4_t test_vlmul_trunc_v_u8m8_u8m4(vuint8m8_t op1)
+{
+  vuint8m4_t a = vlmul_trunc_u8m4(op1);
+  return a;
+}
+
+vuint16mf4_t test_vlmul_trunc_v_u16mf2_u16mf4(vuint16mf2_t op1)
+{
+  vuint16mf4_t a = vlmul_trunc_u16mf4(op1);
+  return a;
+}
+
+vuint16mf4_t test_vlmul_trunc_v_u16m1_u16mf4(vuint16m1_t op1)
+{
+  vuint16mf4_t a = vlmul_trunc_u16mf4(op1);
+  return a;
+}
+
+vuint16mf2_t test_vlmul_trunc_v_u16m1_u16mf2(vuint16m1_t op1)
+{
+  vuint16mf2_t a = vlmul_trunc_u16mf2(op1);
+  return a;
+}
+
+vuint16mf4_t test_vlmul_trunc_v_u16m2_u16mf4(vuint16m2_t op1)
+{
+  vuint16mf4_t a = vlmul_trunc_u16mf4(op1);
+  return a;
+}
+
+vuint16mf2_t test_vlmul_trunc_v_u16m2_u16mf2(vuint16m2_t op1)
+{
+  vuint16mf2_t a = vlmul_trunc_u16mf2(op1);
+  return a;
+}
+
+vuint16m1_t test_vlmul_trunc_v_u16m2_u16m1(vuint16m2_t op1)
+{
+  vuint16m1_t a = vlmul_trunc_u16m1(op1);
+  return a;
+}
+
+vuint16mf4_t test_vlmul_trunc_v_u16m4_u16mf4(vuint16m4_t op1)
+{
+  vuint16mf4_t a = vlmul_trunc_u16mf4(op1);
+  return a;
+}
+
+vuint16mf2_t test_vlmul_trunc_v_u16m4_u16mf2(vuint16m4_t op1)
+{
+  vuint16mf2_t a = vlmul_trunc_u16mf2(op1);
+  return a;
+}
+
+vuint16m1_t test_vlmul_trunc_v_u16m4_u16m1(vuint16m4_t op1)
+{
+  vuint16m1_t a = vlmul_trunc_u16m1(op1);
+  return a;
+}
+
+vuint16m2_t test_vlmul_trunc_v_u16m4_u16m2(vuint16m4_t op1)
+{
+  vuint16m2_t a = vlmul_trunc_u16m2(op1);
+  return a;
+}
+
+vuint16mf4_t test_vlmul_trunc_v_u16m8_u16mf4(vuint16m8_t op1)
+{
+  vuint16mf4_t a = vlmul_trunc_u16mf4(op1);
+  return a;
+}
+
+vuint16mf2_t test_vlmul_trunc_v_u16m8_u16mf2(vuint16m8_t op1)
+{
+  vuint16mf2_t a = vlmul_trunc_u16mf2(op1);
+  return a;
+}
+
+vuint16m1_t test_vlmul_trunc_v_u16m8_u16m1(vuint16m8_t op1)
+{
+  vuint16m1_t a = vlmul_trunc_u16m1(op1);
+  return a;
+}
+
+vuint16m2_t test_vlmul_trunc_v_u16m8_u16m2(vuint16m8_t op1)
+{
+  vuint16m2_t a = vlmul_trunc_u16m2(op1);
+  return a;
+}
+
+vuint16m4_t test_vlmul_trunc_v_u16m8_u16m4(vuint16m8_t op1)
+{
+  vuint16m4_t a = vlmul_trunc_u16m4(op1);
+  return a;
+}
+
+vuint32mf2_t test_vlmul_trunc_v_u32m1_u32mf2(vuint32m1_t op1)
+{
+  vuint32mf2_t a = vlmul_trunc_u32mf2(op1);
+  return a;
+}
+
+vuint32mf2_t test_vlmul_trunc_v_u32m2_u32mf2(vuint32m2_t op1)
+{
+  vuint32mf2_t a = vlmul_trunc_u32mf2(op1);
+  return a;
+}
+
+vuint32m1_t test_vlmul_trunc_v_u32m2_u32m1(vuint32m2_t op1)
+{
+  vuint32m1_t a = vlmul_trunc_u32m1(op1);
+  return a;
+}
+
+vuint32mf2_t test_vlmul_trunc_v_u32m4_u32mf2(vuint32m4_t op1)
+{
+  vuint32mf2_t a = vlmul_trunc_u32mf2(op1);
+  return a;
+}
+
+vuint32m1_t test_vlmul_trunc_v_u32m4_u32m1(vuint32m4_t op1)
+{
+  vuint32m1_t a = vlmul_trunc_u32m1(op1);
+  return a;
+}
+
+vuint32m2_t test_vlmul_trunc_v_u32m4_u32m2(vuint32m4_t op1)
+{
+  vuint32m2_t a = vlmul_trunc_u32m2(op1);
+  return a;
+}
+
+vuint32mf2_t test_vlmul_trunc_v_u32m8_u32mf2(vuint32m8_t op1)
+{
+  vuint32mf2_t a = vlmul_trunc_u32mf2(op1);
+  return a;
+}
+
+vuint32m1_t test_vlmul_trunc_v_u32m8_u32m1(vuint32m8_t op1)
+{
+  vuint32m1_t a = vlmul_trunc_u32m1(op1);
+  return a;
+}
+
+vuint32m2_t test_vlmul_trunc_v_u32m8_u32m2(vuint32m8_t op1)
+{
+  vuint32m2_t a = vlmul_trunc_u32m2(op1);
+  return a;
+}
+
+vuint32m4_t test_vlmul_trunc_v_u32m8_u32m4(vuint32m8_t op1)
+{
+  vuint32m4_t a = vlmul_trunc_u32m4(op1);
+  return a;
+}
+
+vuint64m1_t test_vlmul_trunc_v_u64m2_u64m1(vuint64m2_t op1)
+{
+  vuint64m1_t a = vlmul_trunc_u64m1(op1);
+  return a;
+}
+
+vuint64m1_t test_vlmul_trunc_v_u64m4_u64m1(vuint64m4_t op1)
+{
+  vuint64m1_t a = vlmul_trunc_u64m1(op1);
+  return a;
+}
+
+vuint64m2_t test_vlmul_trunc_v_u64m4_u64m2(vuint64m4_t op1)
+{
+  vuint64m2_t a = vlmul_trunc_u64m2(op1);
+  return a;
+}
+
+vuint64m1_t test_vlmul_trunc_v_u64m8_u64m1(vuint64m8_t op1)
+{
+  vuint64m1_t a = vlmul_trunc_u64m1(op1);
+  return a;
+}
+
+vuint64m2_t test_vlmul_trunc_v_u64m8_u64m2(vuint64m8_t op1)
+{
+  vuint64m2_t a = vlmul_trunc_u64m2(op1);
+  return a;
+}
+
+vuint64m4_t test_vlmul_trunc_v_u64m8_u64m4(vuint64m8_t op1)
+{
+  vuint64m4_t a = vlmul_trunc_u64m4(op1);
+  return a;
+}
+
+vfloat32mf2_t test_vlmul_trunc_v_f32m1_f32mf2(vfloat32m1_t op1)
+{
+  vfloat32mf2_t a = vlmul_trunc_f32mf2(op1);
+  return a;
+}
+
+vfloat32mf2_t test_vlmul_trunc_v_f32m2_f32mf2(vfloat32m2_t op1)
+{
+  vfloat32mf2_t a = vlmul_trunc_f32mf2(op1);
+  return a;
+}
+
+vfloat32m1_t test_vlmul_trunc_v_f32m2_f32m1(vfloat32m2_t op1)
+{
+  vfloat32m1_t a = vlmul_trunc_f32m1(op1);
+  return a;
+}
+
+vfloat32mf2_t test_vlmul_trunc_v_f32m4_f32mf2(vfloat32m4_t op1)
+{
+  vfloat32mf2_t a = vlmul_trunc_f32mf2(op1);
+  return a;
+}
+
+vfloat32m1_t test_vlmul_trunc_v_f32m4_f32m1(vfloat32m4_t op1)
+{
+  vfloat32m1_t a = vlmul_trunc_f32m1(op1);
+  return a;
+}
+
+vfloat32m2_t test_vlmul_trunc_v_f32m4_f32m2(vfloat32m4_t op1)
+{
+  vfloat32m2_t a = vlmul_trunc_f32m2(op1);
+  return a;
+}
+
+vfloat32mf2_t test_vlmul_trunc_v_f32m8_f32mf2(vfloat32m8_t op1)
+{
+  vfloat32mf2_t a = vlmul_trunc_f32mf2(op1);
+  return a;
+}
+
+vfloat32m1_t test_vlmul_trunc_v_f32m8_f32m1(vfloat32m8_t op1)
+{
+  vfloat32m1_t a = vlmul_trunc_f32m1(op1);
+  return a;
+}
+
+vfloat32m2_t test_vlmul_trunc_v_f32m8_f32m2(vfloat32m8_t op1)
+{
+  vfloat32m2_t a = vlmul_trunc_f32m2(op1);
+  return a;
+}
+
+vfloat32m4_t test_vlmul_trunc_v_f32m8_f32m4(vfloat32m8_t op1)
+{
+  vfloat32m4_t a = vlmul_trunc_f32m4(op1);
+  return a;
+}
+
+vfloat64m1_t test_vlmul_trunc_v_f64m2_f64m1(vfloat64m2_t op1)
+{
+  vfloat64m1_t a = vlmul_trunc_f64m1(op1);
+  return a;
+}
+
+vfloat64m1_t test_vlmul_trunc_v_f64m4_f64m1(vfloat64m4_t op1)
+{
+  vfloat64m1_t a = vlmul_trunc_f64m1(op1);
+  return a;
+}
+
+vfloat64m2_t test_vlmul_trunc_v_f64m4_f64m2(vfloat64m4_t op1)
+{
+  vfloat64m2_t a = vlmul_trunc_f64m2(op1);
+  return a;
+}
+
+vfloat64m1_t test_vlmul_trunc_v_f64m8_f64m1(vfloat64m8_t op1)
+{
+  vfloat64m1_t a = vlmul_trunc_f64m1(op1);
+  return a;
+}
+
+vfloat64m2_t test_vlmul_trunc_v_f64m8_f64m2(vfloat64m8_t op1)
+{
+  vfloat64m2_t a = vlmul_trunc_f64m2(op1);
+  return a;
+}
+
+vfloat64m4_t test_vlmul_trunc_v_f64m8_f64m4(vfloat64m8_t op1)
+{
+  vfloat64m4_t a = vlmul_trunc_f64m4(op1);
+  return a;
+}
\ No newline at end of file
diff --git a/gcc/testsuite/g++.target/riscv/rvv/rvv-intrinsic.exp b/gcc/testsuite/g++.target/riscv/rvv/rvv-intrinsic.exp
new file mode 100644
index 00000000000..c8db25f0fbd
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/rvv-intrinsic.exp
@@ -0,0 +1,39 @@ 
+# Copyright (C) 2022-2022 Free Software Foundation, Inc.
+
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with GCC; see the file COPYING3.  If not see
+# <http://www.gnu.org/licenses/>.
+
+# GCC testsuite that uses the `dg.exp' driver.
+
+# Test the front-end for C++.
+# We don't need to test back-end code-gen in RV32 system for C++
+# Because it is already tested in C.
+# Exit immediately if this isn't a RISC-V target.
+if ![istarget riscv64*-*-*] then {
+  return
+}
+
+# Load support procs.
+load_lib g++-dg.exp
+
+# Initialize `dg'.
+dg-init
+
+# Main loop.
+set CFLAGS "-march=rv64gcv_zfh -O3"
+dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.C]] \
+	"" $CFLAGS
+
+# All done.
+dg-finish
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/intrinsic/misc_func.c b/gcc/testsuite/gcc.target/riscv/rvv/intrinsic/misc_func.c
new file mode 100644
index 00000000000..387da4205f9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/intrinsic/misc_func.c
@@ -0,0 +1,2921 @@ 
+
+/* { dg-do compile } */
+/* { dg-skip-if "test vector intrinsic" { *-*-* } { "*" } { "-march=rv*v*" } } */
+
+#include <stddef.h>
+#include <riscv_vector.h>
+
+
+/* Reinterpret between different type under the same SEW and LMUL */
+
+vuint8mf8_t test_vreinterpret_v_i8mf8_u8mf8(vint8mf8_t src)
+{
+  vuint8mf8_t a = vreinterpret_v_i8mf8_u8mf8(src);
+  return a;
+}
+
+vuint8mf4_t test_vreinterpret_v_i8mf4_u8mf4(vint8mf4_t src)
+{
+  vuint8mf4_t a = vreinterpret_v_i8mf4_u8mf4(src);
+  return a;
+}
+
+vuint8mf2_t test_vreinterpret_v_i8mf2_u8mf2(vint8mf2_t src)
+{
+  vuint8mf2_t a = vreinterpret_v_i8mf2_u8mf2(src);
+  return a;
+}
+
+vuint8m1_t test_vreinterpret_v_i8m1_u8m1(vint8m1_t src)
+{
+  vuint8m1_t a = vreinterpret_v_i8m1_u8m1(src);
+  return a;
+}
+
+vuint8m2_t test_vreinterpret_v_i8m2_u8m2(vint8m2_t src)
+{
+  vuint8m2_t a = vreinterpret_v_i8m2_u8m2(src);
+  return a;
+}
+
+vuint8m4_t test_vreinterpret_v_i8m4_u8m4(vint8m4_t src)
+{
+  vuint8m4_t a = vreinterpret_v_i8m4_u8m4(src);
+  return a;
+}
+
+vuint8m8_t test_vreinterpret_v_i8m8_u8m8(vint8m8_t src)
+{
+  vuint8m8_t a = vreinterpret_v_i8m8_u8m8(src);
+  return a;
+}
+
+vint8mf8_t test_vreinterpret_v_u8mf8_i8mf8(vuint8mf8_t src)
+{
+  vint8mf8_t a = vreinterpret_v_u8mf8_i8mf8(src);
+  return a;
+}
+
+vint8mf4_t test_vreinterpret_v_u8mf4_i8mf4(vuint8mf4_t src)
+{
+  vint8mf4_t a = vreinterpret_v_u8mf4_i8mf4(src);
+  return a;
+}
+
+vint8mf2_t test_vreinterpret_v_u8mf2_i8mf2(vuint8mf2_t src)
+{
+  vint8mf2_t a = vreinterpret_v_u8mf2_i8mf2(src);
+  return a;
+}
+
+vint8m1_t test_vreinterpret_v_u8m1_i8m1(vuint8m1_t src)
+{
+  vint8m1_t a = vreinterpret_v_u8m1_i8m1(src);
+  return a;
+}
+
+vint8m2_t test_vreinterpret_v_u8m2_i8m2(vuint8m2_t src)
+{
+  vint8m2_t a = vreinterpret_v_u8m2_i8m2(src);
+  return a;
+}
+
+vint8m4_t test_vreinterpret_v_u8m4_i8m4(vuint8m4_t src)
+{
+  vint8m4_t a = vreinterpret_v_u8m4_i8m4(src);
+  return a;
+}
+
+vint8m8_t test_vreinterpret_v_u8m8_i8m8(vuint8m8_t src)
+{
+  vint8m8_t a = vreinterpret_v_u8m8_i8m8(src);
+  return a;
+}
+
+vuint16mf4_t test_vreinterpret_v_i16mf4_u16mf4(vint16mf4_t src)
+{
+  vuint16mf4_t a = vreinterpret_v_i16mf4_u16mf4(src);
+  return a;
+}
+
+vuint16mf2_t test_vreinterpret_v_i16mf2_u16mf2(vint16mf2_t src)
+{
+  vuint16mf2_t a = vreinterpret_v_i16mf2_u16mf2(src);
+  return a;
+}
+
+vuint16m1_t test_vreinterpret_v_i16m1_u16m1(vint16m1_t src)
+{
+  vuint16m1_t a = vreinterpret_v_i16m1_u16m1(src);
+  return a;
+}
+
+vuint16m2_t test_vreinterpret_v_i16m2_u16m2(vint16m2_t src)
+{
+  vuint16m2_t a = vreinterpret_v_i16m2_u16m2(src);
+  return a;
+}
+
+vuint16m4_t test_vreinterpret_v_i16m4_u16m4(vint16m4_t src)
+{
+  vuint16m4_t a = vreinterpret_v_i16m4_u16m4(src);
+  return a;
+}
+
+vuint16m8_t test_vreinterpret_v_i16m8_u16m8(vint16m8_t src)
+{
+  vuint16m8_t a = vreinterpret_v_i16m8_u16m8(src);
+  return a;
+}
+
+vint16mf4_t test_vreinterpret_v_u16mf4_i16mf4(vuint16mf4_t src)
+{
+  vint16mf4_t a = vreinterpret_v_u16mf4_i16mf4(src);
+  return a;
+}
+
+vint16mf2_t test_vreinterpret_v_u16mf2_i16mf2(vuint16mf2_t src)
+{
+  vint16mf2_t a = vreinterpret_v_u16mf2_i16mf2(src);
+  return a;
+}
+
+vint16m1_t test_vreinterpret_v_u16m1_i16m1(vuint16m1_t src)
+{
+  vint16m1_t a = vreinterpret_v_u16m1_i16m1(src);
+  return a;
+}
+
+vint16m2_t test_vreinterpret_v_u16m2_i16m2(vuint16m2_t src)
+{
+  vint16m2_t a = vreinterpret_v_u16m2_i16m2(src);
+  return a;
+}
+
+vint16m4_t test_vreinterpret_v_u16m4_i16m4(vuint16m4_t src)
+{
+  vint16m4_t a = vreinterpret_v_u16m4_i16m4(src);
+  return a;
+}
+
+vint16m8_t test_vreinterpret_v_u16m8_i16m8(vuint16m8_t src)
+{
+  vint16m8_t a = vreinterpret_v_u16m8_i16m8(src);
+  return a;
+}
+
+vuint32mf2_t test_vreinterpret_v_i32mf2_u32mf2(vint32mf2_t src)
+{
+  vuint32mf2_t a = vreinterpret_v_i32mf2_u32mf2(src);
+  return a;
+}
+
+vuint32m1_t test_vreinterpret_v_i32m1_u32m1(vint32m1_t src)
+{
+  vuint32m1_t a = vreinterpret_v_i32m1_u32m1(src);
+  return a;
+}
+
+vuint32m2_t test_vreinterpret_v_i32m2_u32m2(vint32m2_t src)
+{
+  vuint32m2_t a = vreinterpret_v_i32m2_u32m2(src);
+  return a;
+}
+
+vuint32m4_t test_vreinterpret_v_i32m4_u32m4(vint32m4_t src)
+{
+  vuint32m4_t a = vreinterpret_v_i32m4_u32m4(src);
+  return a;
+}
+
+vuint32m8_t test_vreinterpret_v_i32m8_u32m8(vint32m8_t src)
+{
+  vuint32m8_t a = vreinterpret_v_i32m8_u32m8(src);
+  return a;
+}
+
+vfloat32mf2_t test_vreinterpret_v_i32mf2_f32mf2(vint32mf2_t src)
+{
+  vfloat32mf2_t a = vreinterpret_v_i32mf2_f32mf2(src);
+  return a;
+}
+
+vfloat32m1_t test_vreinterpret_v_i32m1_f32m1(vint32m1_t src)
+{
+  vfloat32m1_t a = vreinterpret_v_i32m1_f32m1(src);
+  return a;
+}
+
+vfloat32m2_t test_vreinterpret_v_i32m2_f32m2(vint32m2_t src)
+{
+  vfloat32m2_t a = vreinterpret_v_i32m2_f32m2(src);
+  return a;
+}
+
+vfloat32m4_t test_vreinterpret_v_i32m4_f32m4(vint32m4_t src)
+{
+  vfloat32m4_t a = vreinterpret_v_i32m4_f32m4(src);
+  return a;
+}
+
+vfloat32m8_t test_vreinterpret_v_i32m8_f32m8(vint32m8_t src)
+{
+  vfloat32m8_t a = vreinterpret_v_i32m8_f32m8(src);
+  return a;
+}
+
+vint32mf2_t test_vreinterpret_v_u32mf2_i32mf2(vuint32mf2_t src)
+{
+  vint32mf2_t a = vreinterpret_v_u32mf2_i32mf2(src);
+  return a;
+}
+
+vint32m1_t test_vreinterpret_v_u32m1_i32m1(vuint32m1_t src)
+{
+  vint32m1_t a = vreinterpret_v_u32m1_i32m1(src);
+  return a;
+}
+
+vint32m2_t test_vreinterpret_v_u32m2_i32m2(vuint32m2_t src)
+{
+  vint32m2_t a = vreinterpret_v_u32m2_i32m2(src);
+  return a;
+}
+
+vint32m4_t test_vreinterpret_v_u32m4_i32m4(vuint32m4_t src)
+{
+  vint32m4_t a = vreinterpret_v_u32m4_i32m4(src);
+  return a;
+}
+
+vint32m8_t test_vreinterpret_v_u32m8_i32m8(vuint32m8_t src)
+{
+  vint32m8_t a = vreinterpret_v_u32m8_i32m8(src);
+  return a;
+}
+
+vfloat32mf2_t test_vreinterpret_v_u32mf2_f32mf2(vuint32mf2_t src)
+{
+  vfloat32mf2_t a = vreinterpret_v_u32mf2_f32mf2(src);
+  return a;
+}
+
+vfloat32m1_t test_vreinterpret_v_u32m1_f32m1(vuint32m1_t src)
+{
+  vfloat32m1_t a = vreinterpret_v_u32m1_f32m1(src);
+  return a;
+}
+
+vfloat32m2_t test_vreinterpret_v_u32m2_f32m2(vuint32m2_t src)
+{
+  vfloat32m2_t a = vreinterpret_v_u32m2_f32m2(src);
+  return a;
+}
+
+vfloat32m4_t test_vreinterpret_v_u32m4_f32m4(vuint32m4_t src)
+{
+  vfloat32m4_t a = vreinterpret_v_u32m4_f32m4(src);
+  return a;
+}
+
+vfloat32m8_t test_vreinterpret_v_u32m8_f32m8(vuint32m8_t src)
+{
+  vfloat32m8_t a = vreinterpret_v_u32m8_f32m8(src);
+  return a;
+}
+
+vint32mf2_t test_vreinterpret_v_f32mf2_i32mf2(vfloat32mf2_t src)
+{
+  vint32mf2_t a = vreinterpret_v_f32mf2_i32mf2(src);
+  return a;
+}
+
+vint32m1_t test_vreinterpret_v_f32m1_i32m1(vfloat32m1_t src)
+{
+  vint32m1_t a = vreinterpret_v_f32m1_i32m1(src);
+  return a;
+}
+
+vint32m2_t test_vreinterpret_v_f32m2_i32m2(vfloat32m2_t src)
+{
+  vint32m2_t a = vreinterpret_v_f32m2_i32m2(src);
+  return a;
+}
+
+vint32m4_t test_vreinterpret_v_f32m4_i32m4(vfloat32m4_t src)
+{
+  vint32m4_t a = vreinterpret_v_f32m4_i32m4(src);
+  return a;
+}
+
+vint32m8_t test_vreinterpret_v_f32m8_i32m8(vfloat32m8_t src)
+{
+  vint32m8_t a = vreinterpret_v_f32m8_i32m8(src);
+  return a;
+}
+
+vuint32mf2_t test_vreinterpret_v_f32mf2_u32mf2(vfloat32mf2_t src)
+{
+  vuint32mf2_t a = vreinterpret_v_f32mf2_u32mf2(src);
+  return a;
+}
+
+vuint32m1_t test_vreinterpret_v_f32m1_u32m1(vfloat32m1_t src)
+{
+  vuint32m1_t a = vreinterpret_v_f32m1_u32m1(src);
+  return a;
+}
+
+vuint32m2_t test_vreinterpret_v_f32m2_u32m2(vfloat32m2_t src)
+{
+  vuint32m2_t a = vreinterpret_v_f32m2_u32m2(src);
+  return a;
+}
+
+vuint32m4_t test_vreinterpret_v_f32m4_u32m4(vfloat32m4_t src)
+{
+  vuint32m4_t a = vreinterpret_v_f32m4_u32m4(src);
+  return a;
+}
+
+vuint32m8_t test_vreinterpret_v_f32m8_u32m8(vfloat32m8_t src)
+{
+  vuint32m8_t a = vreinterpret_v_f32m8_u32m8(src);
+  return a;
+}
+
+vuint64m1_t test_vreinterpret_v_i64m1_u64m1(vint64m1_t src)
+{
+  vuint64m1_t a = vreinterpret_v_i64m1_u64m1(src);
+  return a;
+}
+
+vuint64m2_t test_vreinterpret_v_i64m2_u64m2(vint64m2_t src)
+{
+  vuint64m2_t a = vreinterpret_v_i64m2_u64m2(src);
+  return a;
+}
+
+vuint64m4_t test_vreinterpret_v_i64m4_u64m4(vint64m4_t src)
+{
+  vuint64m4_t a = vreinterpret_v_i64m4_u64m4(src);
+  return a;
+}
+
+vuint64m8_t test_vreinterpret_v_i64m8_u64m8(vint64m8_t src)
+{
+  vuint64m8_t a = vreinterpret_v_i64m8_u64m8(src);
+  return a;
+}
+
+vfloat64m1_t test_vreinterpret_v_i64m1_f64m1(vint64m1_t src)
+{
+  vfloat64m1_t a = vreinterpret_v_i64m1_f64m1(src);
+  return a;
+}
+
+vfloat64m2_t test_vreinterpret_v_i64m2_f64m2(vint64m2_t src)
+{
+  vfloat64m2_t a = vreinterpret_v_i64m2_f64m2(src);
+  return a;
+}
+
+vfloat64m4_t test_vreinterpret_v_i64m4_f64m4(vint64m4_t src)
+{
+  vfloat64m4_t a = vreinterpret_v_i64m4_f64m4(src);
+  return a;
+}
+
+vfloat64m8_t test_vreinterpret_v_i64m8_f64m8(vint64m8_t src)
+{
+  vfloat64m8_t a = vreinterpret_v_i64m8_f64m8(src);
+  return a;
+}
+
+vint64m1_t test_vreinterpret_v_u64m1_i64m1(vuint64m1_t src)
+{
+  vint64m1_t a = vreinterpret_v_u64m1_i64m1(src);
+  return a;
+}
+
+vint64m2_t test_vreinterpret_v_u64m2_i64m2(vuint64m2_t src)
+{
+  vint64m2_t a = vreinterpret_v_u64m2_i64m2(src);
+  return a;
+}
+
+vint64m4_t test_vreinterpret_v_u64m4_i64m4(vuint64m4_t src)
+{
+  vint64m4_t a = vreinterpret_v_u64m4_i64m4(src);
+  return a;
+}
+
+vint64m8_t test_vreinterpret_v_u64m8_i64m8(vuint64m8_t src)
+{
+  vint64m8_t a = vreinterpret_v_u64m8_i64m8(src);
+  return a;
+}
+
+vfloat64m1_t test_vreinterpret_v_u64m1_f64m1(vuint64m1_t src)
+{
+  vfloat64m1_t a = vreinterpret_v_u64m1_f64m1(src);
+  return a;
+}
+
+vfloat64m2_t test_vreinterpret_v_u64m2_f64m2(vuint64m2_t src)
+{
+  vfloat64m2_t a = vreinterpret_v_u64m2_f64m2(src);
+  return a;
+}
+
+vfloat64m4_t test_vreinterpret_v_u64m4_f64m4(vuint64m4_t src)
+{
+  vfloat64m4_t a = vreinterpret_v_u64m4_f64m4(src);
+  return a;
+}
+
+vfloat64m8_t test_vreinterpret_v_u64m8_f64m8(vuint64m8_t src)
+{
+  vfloat64m8_t a = vreinterpret_v_u64m8_f64m8(src);
+  return a;
+}
+
+vint64m1_t test_vreinterpret_v_f64m1_i64m1(vfloat64m1_t src)
+{
+  vint64m1_t a = vreinterpret_v_f64m1_i64m1(src);
+  return a;
+}
+
+vint64m2_t test_vreinterpret_v_f64m2_i64m2(vfloat64m2_t src)
+{
+  vint64m2_t a = vreinterpret_v_f64m2_i64m2(src);
+  return a;
+}
+
+vint64m4_t test_vreinterpret_v_f64m4_i64m4(vfloat64m4_t src)
+{
+  vint64m4_t a = vreinterpret_v_f64m4_i64m4(src);
+  return a;
+}
+
+vint64m8_t test_vreinterpret_v_f64m8_i64m8(vfloat64m8_t src)
+{
+  vint64m8_t a = vreinterpret_v_f64m8_i64m8(src);
+  return a;
+}
+
+vuint64m1_t test_vreinterpret_v_f64m1_u64m1(vfloat64m1_t src)
+{
+  vuint64m1_t a = vreinterpret_v_f64m1_u64m1(src);
+  return a;
+}
+
+vuint64m2_t test_vreinterpret_v_f64m2_u64m2(vfloat64m2_t src)
+{
+  vuint64m2_t a = vreinterpret_v_f64m2_u64m2(src);
+  return a;
+}
+
+vuint64m4_t test_vreinterpret_v_f64m4_u64m4(vfloat64m4_t src)
+{
+  vuint64m4_t a = vreinterpret_v_f64m4_u64m4(src);
+  return a;
+}
+
+vuint64m8_t test_vreinterpret_v_f64m8_u64m8(vfloat64m8_t src)
+{
+  vuint64m8_t a = vreinterpret_v_f64m8_u64m8(src);
+  return a;
+}
+
+/* Reinterpret between different SEW under the same LMUL */
+
+vint16mf4_t test_vreinterpret_v_i8mf4_i16mf4(vint8mf4_t src)
+{
+  vint16mf4_t a = vreinterpret_v_i8mf4_i16mf4(src);
+  return a;
+}
+
+vint16mf2_t test_vreinterpret_v_i8mf2_i16mf2(vint8mf2_t src)
+{
+  vint16mf2_t a = vreinterpret_v_i8mf2_i16mf2(src);
+  return a;
+}
+
+vint16m1_t test_vreinterpret_v_i8m1_i16m1(vint8m1_t src)
+{
+  vint16m1_t a = vreinterpret_v_i8m1_i16m1(src);
+  return a;
+}
+
+vint16m2_t test_vreinterpret_v_i8m2_i16m2(vint8m2_t src)
+{
+  vint16m2_t a = vreinterpret_v_i8m2_i16m2(src);
+  return a;
+}
+
+vint16m4_t test_vreinterpret_v_i8m4_i16m4(vint8m4_t src)
+{
+  vint16m4_t a = vreinterpret_v_i8m4_i16m4(src);
+  return a;
+}
+
+vint16m8_t test_vreinterpret_v_i8m8_i16m8(vint8m8_t src)
+{
+  vint16m8_t a = vreinterpret_v_i8m8_i16m8(src);
+  return a;
+}
+
+vint32mf2_t test_vreinterpret_v_i8mf2_i32mf2(vint8mf2_t src)
+{
+  vint32mf2_t a = vreinterpret_v_i8mf2_i32mf2(src);
+  return a;
+}
+
+vint32m1_t test_vreinterpret_v_i8m1_i32m1(vint8m1_t src)
+{
+  vint32m1_t a = vreinterpret_v_i8m1_i32m1(src);
+  return a;
+}
+
+vint32m2_t test_vreinterpret_v_i8m2_i32m2(vint8m2_t src)
+{
+  vint32m2_t a = vreinterpret_v_i8m2_i32m2(src);
+  return a;
+}
+
+vint32m4_t test_vreinterpret_v_i8m4_i32m4(vint8m4_t src)
+{
+  vint32m4_t a = vreinterpret_v_i8m4_i32m4(src);
+  return a;
+}
+
+vint32m8_t test_vreinterpret_v_i8m8_i32m8(vint8m8_t src)
+{
+  vint32m8_t a = vreinterpret_v_i8m8_i32m8(src);
+  return a;
+}
+
+vint64m1_t test_vreinterpret_v_i8m1_i64m1(vint8m1_t src)
+{
+  vint64m1_t a = vreinterpret_v_i8m1_i64m1(src);
+  return a;
+}
+
+vint64m2_t test_vreinterpret_v_i8m2_i64m2(vint8m2_t src)
+{
+  vint64m2_t a = vreinterpret_v_i8m2_i64m2(src);
+  return a;
+}
+
+vint64m4_t test_vreinterpret_v_i8m4_i64m4(vint8m4_t src)
+{
+  vint64m4_t a = vreinterpret_v_i8m4_i64m4(src);
+  return a;
+}
+
+vint64m8_t test_vreinterpret_v_i8m8_i64m8(vint8m8_t src)
+{
+  vint64m8_t a = vreinterpret_v_i8m8_i64m8(src);
+  return a;
+}
+
+vint8mf4_t test_vreinterpret_v_i16mf4_i8mf4(vint16mf4_t src)
+{
+  vint8mf4_t a = vreinterpret_v_i16mf4_i8mf4(src);
+  return a;
+}
+
+vint8mf2_t test_vreinterpret_v_i16mf2_i8mf2(vint16mf2_t src)
+{
+  vint8mf2_t a = vreinterpret_v_i16mf2_i8mf2(src);
+  return a;
+}
+
+vint8m1_t test_vreinterpret_v_i16m1_i8m1(vint16m1_t src)
+{
+  vint8m1_t a = vreinterpret_v_i16m1_i8m1(src);
+  return a;
+}
+
+vint8m2_t test_vreinterpret_v_i16m2_i8m2(vint16m2_t src)
+{
+  vint8m2_t a = vreinterpret_v_i16m2_i8m2(src);
+  return a;
+}
+
+vint8m4_t test_vreinterpret_v_i16m4_i8m4(vint16m4_t src)
+{
+  vint8m4_t a = vreinterpret_v_i16m4_i8m4(src);
+  return a;
+}
+
+vint8m8_t test_vreinterpret_v_i16m8_i8m8(vint16m8_t src)
+{
+  vint8m8_t a = vreinterpret_v_i16m8_i8m8(src);
+  return a;
+}
+
+vint32mf2_t test_vreinterpret_v_i16mf2_i32mf2(vint16mf2_t src)
+{
+  vint32mf2_t a = vreinterpret_v_i16mf2_i32mf2(src);
+  return a;
+}
+
+vint32m1_t test_vreinterpret_v_i16m1_i32m1(vint16m1_t src)
+{
+  vint32m1_t a = vreinterpret_v_i16m1_i32m1(src);
+  return a;
+}
+
+vint32m2_t test_vreinterpret_v_i16m2_i32m2(vint16m2_t src)
+{
+  vint32m2_t a = vreinterpret_v_i16m2_i32m2(src);
+  return a;
+}
+
+vint32m4_t test_vreinterpret_v_i16m4_i32m4(vint16m4_t src)
+{
+  vint32m4_t a = vreinterpret_v_i16m4_i32m4(src);
+  return a;
+}
+
+vint32m8_t test_vreinterpret_v_i16m8_i32m8(vint16m8_t src)
+{
+  vint32m8_t a = vreinterpret_v_i16m8_i32m8(src);
+  return a;
+}
+
+vint64m1_t test_vreinterpret_v_i16m1_i64m1(vint16m1_t src)
+{
+  vint64m1_t a = vreinterpret_v_i16m1_i64m1(src);
+  return a;
+}
+
+vint64m2_t test_vreinterpret_v_i16m2_i64m2(vint16m2_t src)
+{
+  vint64m2_t a = vreinterpret_v_i16m2_i64m2(src);
+  return a;
+}
+
+vint64m4_t test_vreinterpret_v_i16m4_i64m4(vint16m4_t src)
+{
+  vint64m4_t a = vreinterpret_v_i16m4_i64m4(src);
+  return a;
+}
+
+vint64m8_t test_vreinterpret_v_i16m8_i64m8(vint16m8_t src)
+{
+  vint64m8_t a = vreinterpret_v_i16m8_i64m8(src);
+  return a;
+}
+
+vint8mf2_t test_vreinterpret_v_i32mf2_i8mf2(vint32mf2_t src)
+{
+  vint8mf2_t a = vreinterpret_v_i32mf2_i8mf2(src);
+  return a;
+}
+
+vint8m1_t test_vreinterpret_v_i32m1_i8m1(vint32m1_t src)
+{
+  vint8m1_t a = vreinterpret_v_i32m1_i8m1(src);
+  return a;
+}
+
+vint8m2_t test_vreinterpret_v_i32m2_i8m2(vint32m2_t src)
+{
+  vint8m2_t a = vreinterpret_v_i32m2_i8m2(src);
+  return a;
+}
+
+vint8m4_t test_vreinterpret_v_i32m4_i8m4(vint32m4_t src)
+{
+  vint8m4_t a = vreinterpret_v_i32m4_i8m4(src);
+  return a;
+}
+
+vint8m8_t test_vreinterpret_v_i32m8_i8m8(vint32m8_t src)
+{
+  vint8m8_t a = vreinterpret_v_i32m8_i8m8(src);
+  return a;
+}
+
+vint16mf2_t test_vreinterpret_v_i32mf2_i16mf2(vint32mf2_t src)
+{
+  vint16mf2_t a = vreinterpret_v_i32mf2_i16mf2(src);
+  return a;
+}
+
+vint16m1_t test_vreinterpret_v_i32m1_i16m1(vint32m1_t src)
+{
+  vint16m1_t a = vreinterpret_v_i32m1_i16m1(src);
+  return a;
+}
+
+vint16m2_t test_vreinterpret_v_i32m2_i16m2(vint32m2_t src)
+{
+  vint16m2_t a = vreinterpret_v_i32m2_i16m2(src);
+  return a;
+}
+
+vint16m4_t test_vreinterpret_v_i32m4_i16m4(vint32m4_t src)
+{
+  vint16m4_t a = vreinterpret_v_i32m4_i16m4(src);
+  return a;
+}
+
+vint16m8_t test_vreinterpret_v_i32m8_i16m8(vint32m8_t src)
+{
+  vint16m8_t a = vreinterpret_v_i32m8_i16m8(src);
+  return a;
+}
+
+vint64m1_t test_vreinterpret_v_i32m1_i64m1(vint32m1_t src)
+{
+  vint64m1_t a = vreinterpret_v_i32m1_i64m1(src);
+  return a;
+}
+
+vint64m2_t test_vreinterpret_v_i32m2_i64m2(vint32m2_t src)
+{
+  vint64m2_t a = vreinterpret_v_i32m2_i64m2(src);
+  return a;
+}
+
+vint64m4_t test_vreinterpret_v_i32m4_i64m4(vint32m4_t src)
+{
+  vint64m4_t a = vreinterpret_v_i32m4_i64m4(src);
+  return a;
+}
+
+vint64m8_t test_vreinterpret_v_i32m8_i64m8(vint32m8_t src)
+{
+  vint64m8_t a = vreinterpret_v_i32m8_i64m8(src);
+  return a;
+}
+
+vint8m1_t test_vreinterpret_v_i64m1_i8m1(vint64m1_t src)
+{
+  vint8m1_t a = vreinterpret_v_i64m1_i8m1(src);
+  return a;
+}
+
+vint8m2_t test_vreinterpret_v_i64m2_i8m2(vint64m2_t src)
+{
+  vint8m2_t a = vreinterpret_v_i64m2_i8m2(src);
+  return a;
+}
+
+vint8m4_t test_vreinterpret_v_i64m4_i8m4(vint64m4_t src)
+{
+  vint8m4_t a = vreinterpret_v_i64m4_i8m4(src);
+  return a;
+}
+
+vint8m8_t test_vreinterpret_v_i64m8_i8m8(vint64m8_t src)
+{
+  vint8m8_t a = vreinterpret_v_i64m8_i8m8(src);
+  return a;
+}
+
+vint16m1_t test_vreinterpret_v_i64m1_i16m1(vint64m1_t src)
+{
+  vint16m1_t a = vreinterpret_v_i64m1_i16m1(src);
+  return a;
+}
+
+vint16m2_t test_vreinterpret_v_i64m2_i16m2(vint64m2_t src)
+{
+  vint16m2_t a = vreinterpret_v_i64m2_i16m2(src);
+  return a;
+}
+
+vint16m4_t test_vreinterpret_v_i64m4_i16m4(vint64m4_t src)
+{
+  vint16m4_t a = vreinterpret_v_i64m4_i16m4(src);
+  return a;
+}
+
+vint16m8_t test_vreinterpret_v_i64m8_i16m8(vint64m8_t src)
+{
+  vint16m8_t a = vreinterpret_v_i64m8_i16m8(src);
+  return a;
+}
+
+vint32m1_t test_vreinterpret_v_i64m1_i32m1(vint64m1_t src)
+{
+  vint32m1_t a = vreinterpret_v_i64m1_i32m1(src);
+  return a;
+}
+
+vint32m2_t test_vreinterpret_v_i64m2_i32m2(vint64m2_t src)
+{
+  vint32m2_t a = vreinterpret_v_i64m2_i32m2(src);
+  return a;
+}
+
+vint32m4_t test_vreinterpret_v_i64m4_i32m4(vint64m4_t src)
+{
+  vint32m4_t a = vreinterpret_v_i64m4_i32m4(src);
+  return a;
+}
+
+vint32m8_t test_vreinterpret_v_i64m8_i32m8(vint64m8_t src)
+{
+  vint32m8_t a = vreinterpret_v_i64m8_i32m8(src);
+  return a;
+}
+
+vuint16mf4_t test_vreinterpret_v_u8mf4_u16mf4(vuint8mf4_t src)
+{
+  vuint16mf4_t a = vreinterpret_v_u8mf4_u16mf4(src);
+  return a;
+}
+
+vuint16mf2_t test_vreinterpret_v_u8mf2_u16mf2(vuint8mf2_t src)
+{
+  vuint16mf2_t a = vreinterpret_v_u8mf2_u16mf2(src);
+  return a;
+}
+
+vuint16m1_t test_vreinterpret_v_u8m1_u16m1(vuint8m1_t src)
+{
+  vuint16m1_t a = vreinterpret_v_u8m1_u16m1(src);
+  return a;
+}
+
+vuint16m2_t test_vreinterpret_v_u8m2_u16m2(vuint8m2_t src)
+{
+  vuint16m2_t a = vreinterpret_v_u8m2_u16m2(src);
+  return a;
+}
+
+vuint16m4_t test_vreinterpret_v_u8m4_u16m4(vuint8m4_t src)
+{
+  vuint16m4_t a = vreinterpret_v_u8m4_u16m4(src);
+  return a;
+}
+
+vuint16m8_t test_vreinterpret_v_u8m8_u16m8(vuint8m8_t src)
+{
+  vuint16m8_t a = vreinterpret_v_u8m8_u16m8(src);
+  return a;
+}
+
+vuint32mf2_t test_vreinterpret_v_u8mf2_u32mf2(vuint8mf2_t src)
+{
+  vuint32mf2_t a = vreinterpret_v_u8mf2_u32mf2(src);
+  return a;
+}
+
+vuint32m1_t test_vreinterpret_v_u8m1_u32m1(vuint8m1_t src)
+{
+  vuint32m1_t a = vreinterpret_v_u8m1_u32m1(src);
+  return a;
+}
+
+vuint32m2_t test_vreinterpret_v_u8m2_u32m2(vuint8m2_t src)
+{
+  vuint32m2_t a = vreinterpret_v_u8m2_u32m2(src);
+  return a;
+}
+
+vuint32m4_t test_vreinterpret_v_u8m4_u32m4(vuint8m4_t src)
+{
+  vuint32m4_t a = vreinterpret_v_u8m4_u32m4(src);
+  return a;
+}
+
+vuint32m8_t test_vreinterpret_v_u8m8_u32m8(vuint8m8_t src)
+{
+  vuint32m8_t a = vreinterpret_v_u8m8_u32m8(src);
+  return a;
+}
+
+vuint64m1_t test_vreinterpret_v_u8m1_u64m1(vuint8m1_t src)
+{
+  vuint64m1_t a = vreinterpret_v_u8m1_u64m1(src);
+  return a;
+}
+
+vuint64m2_t test_vreinterpret_v_u8m2_u64m2(vuint8m2_t src)
+{
+  vuint64m2_t a = vreinterpret_v_u8m2_u64m2(src);
+  return a;
+}
+
+vuint64m4_t test_vreinterpret_v_u8m4_u64m4(vuint8m4_t src)
+{
+  vuint64m4_t a = vreinterpret_v_u8m4_u64m4(src);
+  return a;
+}
+
+vuint64m8_t test_vreinterpret_v_u8m8_u64m8(vuint8m8_t src)
+{
+  vuint64m8_t a = vreinterpret_v_u8m8_u64m8(src);
+  return a;
+}
+
+vuint8mf4_t test_vreinterpret_v_u16mf4_u8mf4(vuint16mf4_t src)
+{
+  vuint8mf4_t a = vreinterpret_v_u16mf4_u8mf4(src);
+  return a;
+}
+
+vuint8mf2_t test_vreinterpret_v_u16mf2_u8mf2(vuint16mf2_t src)
+{
+  vuint8mf2_t a = vreinterpret_v_u16mf2_u8mf2(src);
+  return a;
+}
+
+vuint8m1_t test_vreinterpret_v_u16m1_u8m1(vuint16m1_t src)
+{
+  vuint8m1_t a = vreinterpret_v_u16m1_u8m1(src);
+  return a;
+}
+
+vuint8m2_t test_vreinterpret_v_u16m2_u8m2(vuint16m2_t src)
+{
+  vuint8m2_t a = vreinterpret_v_u16m2_u8m2(src);
+  return a;
+}
+
+vuint8m4_t test_vreinterpret_v_u16m4_u8m4(vuint16m4_t src)
+{
+  vuint8m4_t a = vreinterpret_v_u16m4_u8m4(src);
+  return a;
+}
+
+vuint8m8_t test_vreinterpret_v_u16m8_u8m8(vuint16m8_t src)
+{
+  vuint8m8_t a = vreinterpret_v_u16m8_u8m8(src);
+  return a;
+}
+
+vuint32mf2_t test_vreinterpret_v_u16mf2_u32mf2(vuint16mf2_t src)
+{
+  vuint32mf2_t a = vreinterpret_v_u16mf2_u32mf2(src);
+  return a;
+}
+
+vuint32m1_t test_vreinterpret_v_u16m1_u32m1(vuint16m1_t src)
+{
+  vuint32m1_t a = vreinterpret_v_u16m1_u32m1(src);
+  return a;
+}
+
+vuint32m2_t test_vreinterpret_v_u16m2_u32m2(vuint16m2_t src)
+{
+  vuint32m2_t a = vreinterpret_v_u16m2_u32m2(src);
+  return a;
+}
+
+vuint32m4_t test_vreinterpret_v_u16m4_u32m4(vuint16m4_t src)
+{
+  vuint32m4_t a = vreinterpret_v_u16m4_u32m4(src);
+  return a;
+}
+
+vuint32m8_t test_vreinterpret_v_u16m8_u32m8(vuint16m8_t src)
+{
+  vuint32m8_t a = vreinterpret_v_u16m8_u32m8(src);
+  return a;
+}
+
+vuint64m1_t test_vreinterpret_v_u16m1_u64m1(vuint16m1_t src)
+{
+  vuint64m1_t a = vreinterpret_v_u16m1_u64m1(src);
+  return a;
+}
+
+vuint64m2_t test_vreinterpret_v_u16m2_u64m2(vuint16m2_t src)
+{
+  vuint64m2_t a = vreinterpret_v_u16m2_u64m2(src);
+  return a;
+}
+
+vuint64m4_t test_vreinterpret_v_u16m4_u64m4(vuint16m4_t src)
+{
+  vuint64m4_t a = vreinterpret_v_u16m4_u64m4(src);
+  return a;
+}
+
+vuint64m8_t test_vreinterpret_v_u16m8_u64m8(vuint16m8_t src)
+{
+  vuint64m8_t a = vreinterpret_v_u16m8_u64m8(src);
+  return a;
+}
+
+vuint8mf2_t test_vreinterpret_v_u32mf2_u8mf2(vuint32mf2_t src)
+{
+  vuint8mf2_t a = vreinterpret_v_u32mf2_u8mf2(src);
+  return a;
+}
+
+vuint8m1_t test_vreinterpret_v_u32m1_u8m1(vuint32m1_t src)
+{
+  vuint8m1_t a = vreinterpret_v_u32m1_u8m1(src);
+  return a;
+}
+
+vuint8m2_t test_vreinterpret_v_u32m2_u8m2(vuint32m2_t src)
+{
+  vuint8m2_t a = vreinterpret_v_u32m2_u8m2(src);
+  return a;
+}
+
+vuint8m4_t test_vreinterpret_v_u32m4_u8m4(vuint32m4_t src)
+{
+  vuint8m4_t a = vreinterpret_v_u32m4_u8m4(src);
+  return a;
+}
+
+vuint8m8_t test_vreinterpret_v_u32m8_u8m8(vuint32m8_t src)
+{
+  vuint8m8_t a = vreinterpret_v_u32m8_u8m8(src);
+  return a;
+}
+
+vuint16mf2_t test_vreinterpret_v_u32mf2_u16mf2(vuint32mf2_t src)
+{
+  vuint16mf2_t a = vreinterpret_v_u32mf2_u16mf2(src);
+  return a;
+}
+
+vuint16m1_t test_vreinterpret_v_u32m1_u16m1(vuint32m1_t src)
+{
+  vuint16m1_t a = vreinterpret_v_u32m1_u16m1(src);
+  return a;
+}
+
+vuint16m2_t test_vreinterpret_v_u32m2_u16m2(vuint32m2_t src)
+{
+  vuint16m2_t a = vreinterpret_v_u32m2_u16m2(src);
+  return a;
+}
+
+vuint16m4_t test_vreinterpret_v_u32m4_u16m4(vuint32m4_t src)
+{
+  vuint16m4_t a = vreinterpret_v_u32m4_u16m4(src);
+  return a;
+}
+
+vuint16m8_t test_vreinterpret_v_u32m8_u16m8(vuint32m8_t src)
+{
+  vuint16m8_t a = vreinterpret_v_u32m8_u16m8(src);
+  return a;
+}
+
+vuint64m1_t test_vreinterpret_v_u32m1_u64m1(vuint32m1_t src)
+{
+  vuint64m1_t a = vreinterpret_v_u32m1_u64m1(src);
+  return a;
+}
+
+vuint64m2_t test_vreinterpret_v_u32m2_u64m2(vuint32m2_t src)
+{
+  vuint64m2_t a = vreinterpret_v_u32m2_u64m2(src);
+  return a;
+}
+
+vuint64m4_t test_vreinterpret_v_u32m4_u64m4(vuint32m4_t src)
+{
+  vuint64m4_t a = vreinterpret_v_u32m4_u64m4(src);
+  return a;
+}
+
+vuint64m8_t test_vreinterpret_v_u32m8_u64m8(vuint32m8_t src)
+{
+  vuint64m8_t a = vreinterpret_v_u32m8_u64m8(src);
+  return a;
+}
+
+vuint8m1_t test_vreinterpret_v_u64m1_u8m1(vuint64m1_t src)
+{
+  vuint8m1_t a = vreinterpret_v_u64m1_u8m1(src);
+  return a;
+}
+
+vuint8m2_t test_vreinterpret_v_u64m2_u8m2(vuint64m2_t src)
+{
+  vuint8m2_t a = vreinterpret_v_u64m2_u8m2(src);
+  return a;
+}
+
+vuint8m4_t test_vreinterpret_v_u64m4_u8m4(vuint64m4_t src)
+{
+  vuint8m4_t a = vreinterpret_v_u64m4_u8m4(src);
+  return a;
+}
+
+vuint8m8_t test_vreinterpret_v_u64m8_u8m8(vuint64m8_t src)
+{
+  vuint8m8_t a = vreinterpret_v_u64m8_u8m8(src);
+  return a;
+}
+
+vuint16m1_t test_vreinterpret_v_u64m1_u16m1(vuint64m1_t src)
+{
+  vuint16m1_t a = vreinterpret_v_u64m1_u16m1(src);
+  return a;
+}
+
+vuint16m2_t test_vreinterpret_v_u64m2_u16m2(vuint64m2_t src)
+{
+  vuint16m2_t a = vreinterpret_v_u64m2_u16m2(src);
+  return a;
+}
+
+vuint16m4_t test_vreinterpret_v_u64m4_u16m4(vuint64m4_t src)
+{
+  vuint16m4_t a = vreinterpret_v_u64m4_u16m4(src);
+  return a;
+}
+
+vuint16m8_t test_vreinterpret_v_u64m8_u16m8(vuint64m8_t src)
+{
+  vuint16m8_t a = vreinterpret_v_u64m8_u16m8(src);
+  return a;
+}
+
+vuint32m1_t test_vreinterpret_v_u64m1_u32m1(vuint64m1_t src)
+{
+  vuint32m1_t a = vreinterpret_v_u64m1_u32m1(src);
+  return a;
+}
+
+vuint32m2_t test_vreinterpret_v_u64m2_u32m2(vuint64m2_t src)
+{
+  vuint32m2_t a = vreinterpret_v_u64m2_u32m2(src);
+  return a;
+}
+
+vuint32m4_t test_vreinterpret_v_u64m4_u32m4(vuint64m4_t src)
+{
+  vuint32m4_t a = vreinterpret_v_u64m4_u32m4(src);
+  return a;
+}
+
+vuint32m8_t test_vreinterpret_v_u64m8_u32m8(vuint64m8_t src)
+{
+  vuint32m8_t a = vreinterpret_v_u64m8_u32m8(src);
+  return a;
+}
+
+vint8mf4_t test_vlmul_ext_v_i8mf8_i8mf4(vint8mf8_t op1)
+{
+  vint8mf4_t a = vlmul_ext_v_i8mf8_i8mf4(op1);
+  return a;
+}
+
+vint8mf2_t test_vlmul_ext_v_i8mf8_i8mf2(vint8mf8_t op1)
+{
+  vint8mf2_t a = vlmul_ext_v_i8mf8_i8mf2(op1);
+  return a;
+}
+
+vint8m1_t test_vlmul_ext_v_i8mf8_i8m1(vint8mf8_t op1)
+{
+  vint8m1_t a = vlmul_ext_v_i8mf8_i8m1(op1);
+  return a;
+}
+
+vint8m2_t test_vlmul_ext_v_i8mf8_i8m2(vint8mf8_t op1)
+{
+  vint8m2_t a = vlmul_ext_v_i8mf8_i8m2(op1);
+  return a;
+}
+
+vint8m4_t test_vlmul_ext_v_i8mf8_i8m4(vint8mf8_t op1)
+{
+  vint8m4_t a = vlmul_ext_v_i8mf8_i8m4(op1);
+  return a;
+}
+
+vint8m8_t test_vlmul_ext_v_i8mf8_i8m8(vint8mf8_t op1)
+{
+  vint8m8_t a = vlmul_ext_v_i8mf8_i8m8(op1);
+  return a;
+}
+
+vint8mf2_t test_vlmul_ext_v_i8mf4_i8mf2(vint8mf4_t op1)
+{
+  vint8mf2_t a = vlmul_ext_v_i8mf4_i8mf2(op1);
+  return a;
+}
+
+vint8m1_t test_vlmul_ext_v_i8mf4_i8m1(vint8mf4_t op1)
+{
+  vint8m1_t a = vlmul_ext_v_i8mf4_i8m1(op1);
+  return a;
+}
+
+vint8m2_t test_vlmul_ext_v_i8mf4_i8m2(vint8mf4_t op1)
+{
+  vint8m2_t a = vlmul_ext_v_i8mf4_i8m2(op1);
+  return a;
+}
+
+vint8m4_t test_vlmul_ext_v_i8mf4_i8m4(vint8mf4_t op1)
+{
+  vint8m4_t a = vlmul_ext_v_i8mf4_i8m4(op1);
+  return a;
+}
+
+vint8m8_t test_vlmul_ext_v_i8mf4_i8m8(vint8mf4_t op1)
+{
+  vint8m8_t a = vlmul_ext_v_i8mf4_i8m8(op1);
+  return a;
+}
+
+vint8m1_t test_vlmul_ext_v_i8mf2_i8m1(vint8mf2_t op1)
+{
+  vint8m1_t a = vlmul_ext_v_i8mf2_i8m1(op1);
+  return a;
+}
+
+vint8m2_t test_vlmul_ext_v_i8mf2_i8m2(vint8mf2_t op1)
+{
+  vint8m2_t a = vlmul_ext_v_i8mf2_i8m2(op1);
+  return a;
+}
+
+vint8m4_t test_vlmul_ext_v_i8mf2_i8m4(vint8mf2_t op1)
+{
+  vint8m4_t a = vlmul_ext_v_i8mf2_i8m4(op1);
+  return a;
+}
+
+vint8m8_t test_vlmul_ext_v_i8mf2_i8m8(vint8mf2_t op1)
+{
+  vint8m8_t a = vlmul_ext_v_i8mf2_i8m8(op1);
+  return a;
+}
+
+vint8m2_t test_vlmul_ext_v_i8m1_i8m2(vint8m1_t op1)
+{
+  vint8m2_t a = vlmul_ext_v_i8m1_i8m2(op1);
+  return a;
+}
+
+vint8m4_t test_vlmul_ext_v_i8m1_i8m4(vint8m1_t op1)
+{
+  vint8m4_t a = vlmul_ext_v_i8m1_i8m4(op1);
+  return a;
+}
+
+vint8m8_t test_vlmul_ext_v_i8m1_i8m8(vint8m1_t op1)
+{
+  vint8m8_t a = vlmul_ext_v_i8m1_i8m8(op1);
+  return a;
+}
+
+vint8m4_t test_vlmul_ext_v_i8m2_i8m4(vint8m2_t op1)
+{
+  vint8m4_t a = vlmul_ext_v_i8m2_i8m4(op1);
+  return a;
+}
+
+vint8m8_t test_vlmul_ext_v_i8m2_i8m8(vint8m2_t op1)
+{
+  vint8m8_t a = vlmul_ext_v_i8m2_i8m8(op1);
+  return a;
+}
+
+vint8m8_t test_vlmul_ext_v_i8m4_i8m8(vint8m4_t op1)
+{
+  vint8m8_t a = vlmul_ext_v_i8m4_i8m8(op1);
+  return a;
+}
+
+vint16mf2_t test_vlmul_ext_v_i16mf4_i16mf2(vint16mf4_t op1)
+{
+  vint16mf2_t a = vlmul_ext_v_i16mf4_i16mf2(op1);
+  return a;
+}
+
+vint16m1_t test_vlmul_ext_v_i16mf4_i16m1(vint16mf4_t op1)
+{
+  vint16m1_t a = vlmul_ext_v_i16mf4_i16m1(op1);
+  return a;
+}
+
+vint16m2_t test_vlmul_ext_v_i16mf4_i16m2(vint16mf4_t op1)
+{
+  vint16m2_t a = vlmul_ext_v_i16mf4_i16m2(op1);
+  return a;
+}
+
+vint16m4_t test_vlmul_ext_v_i16mf4_i16m4(vint16mf4_t op1)
+{
+  vint16m4_t a = vlmul_ext_v_i16mf4_i16m4(op1);
+  return a;
+}
+
+vint16m8_t test_vlmul_ext_v_i16mf4_i16m8(vint16mf4_t op1)
+{
+  vint16m8_t a = vlmul_ext_v_i16mf4_i16m8(op1);
+  return a;
+}
+
+vint16m1_t test_vlmul_ext_v_i16mf2_i16m1(vint16mf2_t op1)
+{
+  vint16m1_t a = vlmul_ext_v_i16mf2_i16m1(op1);
+  return a;
+}
+
+vint16m2_t test_vlmul_ext_v_i16mf2_i16m2(vint16mf2_t op1)
+{
+  vint16m2_t a = vlmul_ext_v_i16mf2_i16m2(op1);
+  return a;
+}
+
+vint16m4_t test_vlmul_ext_v_i16mf2_i16m4(vint16mf2_t op1)
+{
+  vint16m4_t a = vlmul_ext_v_i16mf2_i16m4(op1);
+  return a;
+}
+
+vint16m8_t test_vlmul_ext_v_i16mf2_i16m8(vint16mf2_t op1)
+{
+  vint16m8_t a = vlmul_ext_v_i16mf2_i16m8(op1);
+  return a;
+}
+
+vint16m2_t test_vlmul_ext_v_i16m1_i16m2(vint16m1_t op1)
+{
+  vint16m2_t a = vlmul_ext_v_i16m1_i16m2(op1);
+  return a;
+}
+
+vint16m4_t test_vlmul_ext_v_i16m1_i16m4(vint16m1_t op1)
+{
+  vint16m4_t a = vlmul_ext_v_i16m1_i16m4(op1);
+  return a;
+}
+
+vint16m8_t test_vlmul_ext_v_i16m1_i16m8(vint16m1_t op1)
+{
+  vint16m8_t a = vlmul_ext_v_i16m1_i16m8(op1);
+  return a;
+}
+
+vint16m4_t test_vlmul_ext_v_i16m2_i16m4(vint16m2_t op1)
+{
+  vint16m4_t a = vlmul_ext_v_i16m2_i16m4(op1);
+  return a;
+}
+
+vint16m8_t test_vlmul_ext_v_i16m2_i16m8(vint16m2_t op1)
+{
+  vint16m8_t a = vlmul_ext_v_i16m2_i16m8(op1);
+  return a;
+}
+
+vint16m8_t test_vlmul_ext_v_i16m4_i16m8(vint16m4_t op1)
+{
+  vint16m8_t a = vlmul_ext_v_i16m4_i16m8(op1);
+  return a;
+}
+
+vint32m1_t test_vlmul_ext_v_i32mf2_i32m1(vint32mf2_t op1)
+{
+  vint32m1_t a = vlmul_ext_v_i32mf2_i32m1(op1);
+  return a;
+}
+
+vint32m2_t test_vlmul_ext_v_i32mf2_i32m2(vint32mf2_t op1)
+{
+  vint32m2_t a = vlmul_ext_v_i32mf2_i32m2(op1);
+  return a;
+}
+
+vint32m4_t test_vlmul_ext_v_i32mf2_i32m4(vint32mf2_t op1)
+{
+  vint32m4_t a = vlmul_ext_v_i32mf2_i32m4(op1);
+  return a;
+}
+
+vint32m8_t test_vlmul_ext_v_i32mf2_i32m8(vint32mf2_t op1)
+{
+  vint32m8_t a = vlmul_ext_v_i32mf2_i32m8(op1);
+  return a;
+}
+
+vint32m2_t test_vlmul_ext_v_i32m1_i32m2(vint32m1_t op1)
+{
+  vint32m2_t a = vlmul_ext_v_i32m1_i32m2(op1);
+  return a;
+}
+
+vint32m4_t test_vlmul_ext_v_i32m1_i32m4(vint32m1_t op1)
+{
+  vint32m4_t a = vlmul_ext_v_i32m1_i32m4(op1);
+  return a;
+}
+
+vint32m8_t test_vlmul_ext_v_i32m1_i32m8(vint32m1_t op1)
+{
+  vint32m8_t a = vlmul_ext_v_i32m1_i32m8(op1);
+  return a;
+}
+
+vint32m4_t test_vlmul_ext_v_i32m2_i32m4(vint32m2_t op1)
+{
+  vint32m4_t a = vlmul_ext_v_i32m2_i32m4(op1);
+  return a;
+}
+
+vint32m8_t test_vlmul_ext_v_i32m2_i32m8(vint32m2_t op1)
+{
+  vint32m8_t a = vlmul_ext_v_i32m2_i32m8(op1);
+  return a;
+}
+
+vint32m8_t test_vlmul_ext_v_i32m4_i32m8(vint32m4_t op1)
+{
+  vint32m8_t a = vlmul_ext_v_i32m4_i32m8(op1);
+  return a;
+}
+
+vint64m2_t test_vlmul_ext_v_i64m1_i64m2(vint64m1_t op1)
+{
+  vint64m2_t a = vlmul_ext_v_i64m1_i64m2(op1);
+  return a;
+}
+
+vint64m4_t test_vlmul_ext_v_i64m1_i64m4(vint64m1_t op1)
+{
+  vint64m4_t a = vlmul_ext_v_i64m1_i64m4(op1);
+  return a;
+}
+
+vint64m8_t test_vlmul_ext_v_i64m1_i64m8(vint64m1_t op1)
+{
+  vint64m8_t a = vlmul_ext_v_i64m1_i64m8(op1);
+  return a;
+}
+
+vint64m4_t test_vlmul_ext_v_i64m2_i64m4(vint64m2_t op1)
+{
+  vint64m4_t a = vlmul_ext_v_i64m2_i64m4(op1);
+  return a;
+}
+
+vint64m8_t test_vlmul_ext_v_i64m2_i64m8(vint64m2_t op1)
+{
+  vint64m8_t a = vlmul_ext_v_i64m2_i64m8(op1);
+  return a;
+}
+
+vint64m8_t test_vlmul_ext_v_i64m4_i64m8(vint64m4_t op1)
+{
+  vint64m8_t a = vlmul_ext_v_i64m4_i64m8(op1);
+  return a;
+}
+
+vuint8mf4_t test_vlmul_ext_v_u8mf8_u8mf4(vuint8mf8_t op1)
+{
+  vuint8mf4_t a = vlmul_ext_v_u8mf8_u8mf4(op1);
+  return a;
+}
+
+vuint8mf2_t test_vlmul_ext_v_u8mf8_u8mf2(vuint8mf8_t op1)
+{
+  vuint8mf2_t a = vlmul_ext_v_u8mf8_u8mf2(op1);
+  return a;
+}
+
+vuint8m1_t test_vlmul_ext_v_u8mf8_u8m1(vuint8mf8_t op1)
+{
+  vuint8m1_t a = vlmul_ext_v_u8mf8_u8m1(op1);
+  return a;
+}
+
+vuint8m2_t test_vlmul_ext_v_u8mf8_u8m2(vuint8mf8_t op1)
+{
+  vuint8m2_t a = vlmul_ext_v_u8mf8_u8m2(op1);
+  return a;
+}
+
+vuint8m4_t test_vlmul_ext_v_u8mf8_u8m4(vuint8mf8_t op1)
+{
+  vuint8m4_t a = vlmul_ext_v_u8mf8_u8m4(op1);
+  return a;
+}
+
+vuint8m8_t test_vlmul_ext_v_u8mf8_u8m8(vuint8mf8_t op1)
+{
+  vuint8m8_t a = vlmul_ext_v_u8mf8_u8m8(op1);
+  return a;
+}
+
+vuint8mf2_t test_vlmul_ext_v_u8mf4_u8mf2(vuint8mf4_t op1)
+{
+  vuint8mf2_t a = vlmul_ext_v_u8mf4_u8mf2(op1);
+  return a;
+}
+
+vuint8m1_t test_vlmul_ext_v_u8mf4_u8m1(vuint8mf4_t op1)
+{
+  vuint8m1_t a = vlmul_ext_v_u8mf4_u8m1(op1);
+  return a;
+}
+
+vuint8m2_t test_vlmul_ext_v_u8mf4_u8m2(vuint8mf4_t op1)
+{
+  vuint8m2_t a = vlmul_ext_v_u8mf4_u8m2(op1);
+  return a;
+}
+
+vuint8m4_t test_vlmul_ext_v_u8mf4_u8m4(vuint8mf4_t op1)
+{
+  vuint8m4_t a = vlmul_ext_v_u8mf4_u8m4(op1);
+  return a;
+}
+
+vuint8m8_t test_vlmul_ext_v_u8mf4_u8m8(vuint8mf4_t op1)
+{
+  vuint8m8_t a = vlmul_ext_v_u8mf4_u8m8(op1);
+  return a;
+}
+
+vuint8m1_t test_vlmul_ext_v_u8mf2_u8m1(vuint8mf2_t op1)
+{
+  vuint8m1_t a = vlmul_ext_v_u8mf2_u8m1(op1);
+  return a;
+}
+
+vuint8m2_t test_vlmul_ext_v_u8mf2_u8m2(vuint8mf2_t op1)
+{
+  vuint8m2_t a = vlmul_ext_v_u8mf2_u8m2(op1);
+  return a;
+}
+
+vuint8m4_t test_vlmul_ext_v_u8mf2_u8m4(vuint8mf2_t op1)
+{
+  vuint8m4_t a = vlmul_ext_v_u8mf2_u8m4(op1);
+  return a;
+}
+
+vuint8m8_t test_vlmul_ext_v_u8mf2_u8m8(vuint8mf2_t op1)
+{
+  vuint8m8_t a = vlmul_ext_v_u8mf2_u8m8(op1);
+  return a;
+}
+
+vuint8m2_t test_vlmul_ext_v_u8m1_u8m2(vuint8m1_t op1)
+{
+  vuint8m2_t a = vlmul_ext_v_u8m1_u8m2(op1);
+  return a;
+}
+
+vuint8m4_t test_vlmul_ext_v_u8m1_u8m4(vuint8m1_t op1)
+{
+  vuint8m4_t a = vlmul_ext_v_u8m1_u8m4(op1);
+  return a;
+}
+
+vuint8m8_t test_vlmul_ext_v_u8m1_u8m8(vuint8m1_t op1)
+{
+  vuint8m8_t a = vlmul_ext_v_u8m1_u8m8(op1);
+  return a;
+}
+
+vuint8m4_t test_vlmul_ext_v_u8m2_u8m4(vuint8m2_t op1)
+{
+  vuint8m4_t a = vlmul_ext_v_u8m2_u8m4(op1);
+  return a;
+}
+
+vuint8m8_t test_vlmul_ext_v_u8m2_u8m8(vuint8m2_t op1)
+{
+  vuint8m8_t a = vlmul_ext_v_u8m2_u8m8(op1);
+  return a;
+}
+
+vuint8m8_t test_vlmul_ext_v_u8m4_u8m8(vuint8m4_t op1)
+{
+  vuint8m8_t a = vlmul_ext_v_u8m4_u8m8(op1);
+  return a;
+}
+
+vuint16mf2_t test_vlmul_ext_v_u16mf4_u16mf2(vuint16mf4_t op1)
+{
+  vuint16mf2_t a = vlmul_ext_v_u16mf4_u16mf2(op1);
+  return a;
+}
+
+vuint16m1_t test_vlmul_ext_v_u16mf4_u16m1(vuint16mf4_t op1)
+{
+  vuint16m1_t a = vlmul_ext_v_u16mf4_u16m1(op1);
+  return a;
+}
+
+vuint16m2_t test_vlmul_ext_v_u16mf4_u16m2(vuint16mf4_t op1)
+{
+  vuint16m2_t a = vlmul_ext_v_u16mf4_u16m2(op1);
+  return a;
+}
+
+vuint16m4_t test_vlmul_ext_v_u16mf4_u16m4(vuint16mf4_t op1)
+{
+  vuint16m4_t a = vlmul_ext_v_u16mf4_u16m4(op1);
+  return a;
+}
+
+vuint16m8_t test_vlmul_ext_v_u16mf4_u16m8(vuint16mf4_t op1)
+{
+  vuint16m8_t a = vlmul_ext_v_u16mf4_u16m8(op1);
+  return a;
+}
+
+vuint16m1_t test_vlmul_ext_v_u16mf2_u16m1(vuint16mf2_t op1)
+{
+  vuint16m1_t a = vlmul_ext_v_u16mf2_u16m1(op1);
+  return a;
+}
+
+vuint16m2_t test_vlmul_ext_v_u16mf2_u16m2(vuint16mf2_t op1)
+{
+  vuint16m2_t a = vlmul_ext_v_u16mf2_u16m2(op1);
+  return a;
+}
+
+vuint16m4_t test_vlmul_ext_v_u16mf2_u16m4(vuint16mf2_t op1)
+{
+  vuint16m4_t a = vlmul_ext_v_u16mf2_u16m4(op1);
+  return a;
+}
+
+vuint16m8_t test_vlmul_ext_v_u16mf2_u16m8(vuint16mf2_t op1)
+{
+  vuint16m8_t a = vlmul_ext_v_u16mf2_u16m8(op1);
+  return a;
+}
+
+vuint16m2_t test_vlmul_ext_v_u16m1_u16m2(vuint16m1_t op1)
+{
+  vuint16m2_t a = vlmul_ext_v_u16m1_u16m2(op1);
+  return a;
+}
+
+vuint16m4_t test_vlmul_ext_v_u16m1_u16m4(vuint16m1_t op1)
+{
+  vuint16m4_t a = vlmul_ext_v_u16m1_u16m4(op1);
+  return a;
+}
+
+vuint16m8_t test_vlmul_ext_v_u16m1_u16m8(vuint16m1_t op1)
+{
+  vuint16m8_t a = vlmul_ext_v_u16m1_u16m8(op1);
+  return a;
+}
+
+vuint16m4_t test_vlmul_ext_v_u16m2_u16m4(vuint16m2_t op1)
+{
+  vuint16m4_t a = vlmul_ext_v_u16m2_u16m4(op1);
+  return a;
+}
+
+vuint16m8_t test_vlmul_ext_v_u16m2_u16m8(vuint16m2_t op1)
+{
+  vuint16m8_t a = vlmul_ext_v_u16m2_u16m8(op1);
+  return a;
+}
+
+vuint16m8_t test_vlmul_ext_v_u16m4_u16m8(vuint16m4_t op1)
+{
+  vuint16m8_t a = vlmul_ext_v_u16m4_u16m8(op1);
+  return a;
+}
+
+vuint32m1_t test_vlmul_ext_v_u32mf2_u32m1(vuint32mf2_t op1)
+{
+  vuint32m1_t a = vlmul_ext_v_u32mf2_u32m1(op1);
+  return a;
+}
+
+vuint32m2_t test_vlmul_ext_v_u32mf2_u32m2(vuint32mf2_t op1)
+{
+  vuint32m2_t a = vlmul_ext_v_u32mf2_u32m2(op1);
+  return a;
+}
+
+vuint32m4_t test_vlmul_ext_v_u32mf2_u32m4(vuint32mf2_t op1)
+{
+  vuint32m4_t a = vlmul_ext_v_u32mf2_u32m4(op1);
+  return a;
+}
+
+vuint32m8_t test_vlmul_ext_v_u32mf2_u32m8(vuint32mf2_t op1)
+{
+  vuint32m8_t a = vlmul_ext_v_u32mf2_u32m8(op1);
+  return a;
+}
+
+vuint32m2_t test_vlmul_ext_v_u32m1_u32m2(vuint32m1_t op1)
+{
+  vuint32m2_t a = vlmul_ext_v_u32m1_u32m2(op1);
+  return a;
+}
+
+vuint32m4_t test_vlmul_ext_v_u32m1_u32m4(vuint32m1_t op1)
+{
+  vuint32m4_t a = vlmul_ext_v_u32m1_u32m4(op1);
+  return a;
+}
+
+vuint32m8_t test_vlmul_ext_v_u32m1_u32m8(vuint32m1_t op1)
+{
+  vuint32m8_t a = vlmul_ext_v_u32m1_u32m8(op1);
+  return a;
+}
+
+vuint32m4_t test_vlmul_ext_v_u32m2_u32m4(vuint32m2_t op1)
+{
+  vuint32m4_t a = vlmul_ext_v_u32m2_u32m4(op1);
+  return a;
+}
+
+vuint32m8_t test_vlmul_ext_v_u32m2_u32m8(vuint32m2_t op1)
+{
+  vuint32m8_t a = vlmul_ext_v_u32m2_u32m8(op1);
+  return a;
+}
+
+vuint32m8_t test_vlmul_ext_v_u32m4_u32m8(vuint32m4_t op1)
+{
+  vuint32m8_t a = vlmul_ext_v_u32m4_u32m8(op1);
+  return a;
+}
+
+vuint64m2_t test_vlmul_ext_v_u64m1_u64m2(vuint64m1_t op1)
+{
+  vuint64m2_t a = vlmul_ext_v_u64m1_u64m2(op1);
+  return a;
+}
+
+vuint64m4_t test_vlmul_ext_v_u64m1_u64m4(vuint64m1_t op1)
+{
+  vuint64m4_t a = vlmul_ext_v_u64m1_u64m4(op1);
+  return a;
+}
+
+vuint64m8_t test_vlmul_ext_v_u64m1_u64m8(vuint64m1_t op1)
+{
+  vuint64m8_t a = vlmul_ext_v_u64m1_u64m8(op1);
+  return a;
+}
+
+vuint64m4_t test_vlmul_ext_v_u64m2_u64m4(vuint64m2_t op1)
+{
+  vuint64m4_t a = vlmul_ext_v_u64m2_u64m4(op1);
+  return a;
+}
+
+vuint64m8_t test_vlmul_ext_v_u64m2_u64m8(vuint64m2_t op1)
+{
+  vuint64m8_t a = vlmul_ext_v_u64m2_u64m8(op1);
+  return a;
+}
+
+vuint64m8_t test_vlmul_ext_v_u64m4_u64m8(vuint64m4_t op1)
+{
+  vuint64m8_t a = vlmul_ext_v_u64m4_u64m8(op1);
+  return a;
+}
+
+vfloat32m1_t test_vlmul_ext_v_f32mf2_f32m1(vfloat32mf2_t op1)
+{
+  vfloat32m1_t a = vlmul_ext_v_f32mf2_f32m1(op1);
+  return a;
+}
+
+vfloat32m2_t test_vlmul_ext_v_f32mf2_f32m2(vfloat32mf2_t op1)
+{
+  vfloat32m2_t a = vlmul_ext_v_f32mf2_f32m2(op1);
+  return a;
+}
+
+vfloat32m4_t test_vlmul_ext_v_f32mf2_f32m4(vfloat32mf2_t op1)
+{
+  vfloat32m4_t a = vlmul_ext_v_f32mf2_f32m4(op1);
+  return a;
+}
+
+vfloat32m8_t test_vlmul_ext_v_f32mf2_f32m8(vfloat32mf2_t op1)
+{
+  vfloat32m8_t a = vlmul_ext_v_f32mf2_f32m8(op1);
+  return a;
+}
+
+vfloat32m2_t test_vlmul_ext_v_f32m1_f32m2(vfloat32m1_t op1)
+{
+  vfloat32m2_t a = vlmul_ext_v_f32m1_f32m2(op1);
+  return a;
+}
+
+vfloat32m4_t test_vlmul_ext_v_f32m1_f32m4(vfloat32m1_t op1)
+{
+  vfloat32m4_t a = vlmul_ext_v_f32m1_f32m4(op1);
+  return a;
+}
+
+vfloat32m8_t test_vlmul_ext_v_f32m1_f32m8(vfloat32m1_t op1)
+{
+  vfloat32m8_t a = vlmul_ext_v_f32m1_f32m8(op1);
+  return a;
+}
+
+vfloat32m4_t test_vlmul_ext_v_f32m2_f32m4(vfloat32m2_t op1)
+{
+  vfloat32m4_t a = vlmul_ext_v_f32m2_f32m4(op1);
+  return a;
+}
+
+vfloat32m8_t test_vlmul_ext_v_f32m2_f32m8(vfloat32m2_t op1)
+{
+  vfloat32m8_t a = vlmul_ext_v_f32m2_f32m8(op1);
+  return a;
+}
+
+vfloat32m8_t test_vlmul_ext_v_f32m4_f32m8(vfloat32m4_t op1)
+{
+  vfloat32m8_t a = vlmul_ext_v_f32m4_f32m8(op1);
+  return a;
+}
+
+vfloat64m2_t test_vlmul_ext_v_f64m1_f64m2(vfloat64m1_t op1)
+{
+  vfloat64m2_t a = vlmul_ext_v_f64m1_f64m2(op1);
+  return a;
+}
+
+vfloat64m4_t test_vlmul_ext_v_f64m1_f64m4(vfloat64m1_t op1)
+{
+  vfloat64m4_t a = vlmul_ext_v_f64m1_f64m4(op1);
+  return a;
+}
+
+vfloat64m8_t test_vlmul_ext_v_f64m1_f64m8(vfloat64m1_t op1)
+{
+  vfloat64m8_t a = vlmul_ext_v_f64m1_f64m8(op1);
+  return a;
+}
+
+vfloat64m4_t test_vlmul_ext_v_f64m2_f64m4(vfloat64m2_t op1)
+{
+  vfloat64m4_t a = vlmul_ext_v_f64m2_f64m4(op1);
+  return a;
+}
+
+vfloat64m8_t test_vlmul_ext_v_f64m2_f64m8(vfloat64m2_t op1)
+{
+  vfloat64m8_t a = vlmul_ext_v_f64m2_f64m8(op1);
+  return a;
+}
+
+vfloat64m8_t test_vlmul_ext_v_f64m4_f64m8(vfloat64m4_t op1)
+{
+  vfloat64m8_t a = vlmul_ext_v_f64m4_f64m8(op1);
+  return a;
+}
+
+vint8mf8_t test_vlmul_trunc_v_i8mf4_i8mf8(vint8mf4_t op1)
+{
+  vint8mf8_t a = vlmul_trunc_v_i8mf4_i8mf8(op1);
+  return a;
+}
+
+vint8mf8_t test_vlmul_trunc_v_i8mf2_i8mf8(vint8mf2_t op1)
+{
+  vint8mf8_t a = vlmul_trunc_v_i8mf2_i8mf8(op1);
+  return a;
+}
+
+vint8mf4_t test_vlmul_trunc_v_i8mf2_i8mf4(vint8mf2_t op1)
+{
+  vint8mf4_t a = vlmul_trunc_v_i8mf2_i8mf4(op1);
+  return a;
+}
+
+vint8mf8_t test_vlmul_trunc_v_i8m1_i8mf8(vint8m1_t op1)
+{
+  vint8mf8_t a = vlmul_trunc_v_i8m1_i8mf8(op1);
+  return a;
+}
+
+vint8mf4_t test_vlmul_trunc_v_i8m1_i8mf4(vint8m1_t op1)
+{
+  vint8mf4_t a = vlmul_trunc_v_i8m1_i8mf4(op1);
+  return a;
+}
+
+vint8mf2_t test_vlmul_trunc_v_i8m1_i8mf2(vint8m1_t op1)
+{
+  vint8mf2_t a = vlmul_trunc_v_i8m1_i8mf2(op1);
+  return a;
+}
+
+vint8mf8_t test_vlmul_trunc_v_i8m2_i8mf8(vint8m2_t op1)
+{
+  vint8mf8_t a = vlmul_trunc_v_i8m2_i8mf8(op1);
+  return a;
+}
+
+vint8mf4_t test_vlmul_trunc_v_i8m2_i8mf4(vint8m2_t op1)
+{
+  vint8mf4_t a = vlmul_trunc_v_i8m2_i8mf4(op1);
+  return a;
+}
+
+vint8mf2_t test_vlmul_trunc_v_i8m2_i8mf2(vint8m2_t op1)
+{
+  vint8mf2_t a = vlmul_trunc_v_i8m2_i8mf2(op1);
+  return a;
+}
+
+vint8m1_t test_vlmul_trunc_v_i8m2_i8m1(vint8m2_t op1)
+{
+  vint8m1_t a = vlmul_trunc_v_i8m2_i8m1(op1);
+  return a;
+}
+
+vint8mf8_t test_vlmul_trunc_v_i8m4_i8mf8(vint8m4_t op1)
+{
+  vint8mf8_t a = vlmul_trunc_v_i8m4_i8mf8(op1);
+  return a;
+}
+
+vint8mf4_t test_vlmul_trunc_v_i8m4_i8mf4(vint8m4_t op1)
+{
+  vint8mf4_t a = vlmul_trunc_v_i8m4_i8mf4(op1);
+  return a;
+}
+
+vint8mf2_t test_vlmul_trunc_v_i8m4_i8mf2(vint8m4_t op1)
+{
+  vint8mf2_t a = vlmul_trunc_v_i8m4_i8mf2(op1);
+  return a;
+}
+
+vint8m1_t test_vlmul_trunc_v_i8m4_i8m1(vint8m4_t op1)
+{
+  vint8m1_t a = vlmul_trunc_v_i8m4_i8m1(op1);
+  return a;
+}
+
+vint8m2_t test_vlmul_trunc_v_i8m4_i8m2(vint8m4_t op1)
+{
+  vint8m2_t a = vlmul_trunc_v_i8m4_i8m2(op1);
+  return a;
+}
+
+vint8mf8_t test_vlmul_trunc_v_i8m8_i8mf8(vint8m8_t op1)
+{
+  vint8mf8_t a = vlmul_trunc_v_i8m8_i8mf8(op1);
+  return a;
+}
+
+vint8mf4_t test_vlmul_trunc_v_i8m8_i8mf4(vint8m8_t op1)
+{
+  vint8mf4_t a = vlmul_trunc_v_i8m8_i8mf4(op1);
+  return a;
+}
+
+vint8mf2_t test_vlmul_trunc_v_i8m8_i8mf2(vint8m8_t op1)
+{
+  vint8mf2_t a = vlmul_trunc_v_i8m8_i8mf2(op1);
+  return a;
+}
+
+vint8m1_t test_vlmul_trunc_v_i8m8_i8m1(vint8m8_t op1)
+{
+  vint8m1_t a = vlmul_trunc_v_i8m8_i8m1(op1);
+  return a;
+}
+
+vint8m2_t test_vlmul_trunc_v_i8m8_i8m2(vint8m8_t op1)
+{
+  vint8m2_t a = vlmul_trunc_v_i8m8_i8m2(op1);
+  return a;
+}
+
+vint8m4_t test_vlmul_trunc_v_i8m8_i8m4(vint8m8_t op1)
+{
+  vint8m4_t a = vlmul_trunc_v_i8m8_i8m4(op1);
+  return a;
+}
+
+vint16mf4_t test_vlmul_trunc_v_i16mf2_i16mf4(vint16mf2_t op1)
+{
+  vint16mf4_t a = vlmul_trunc_v_i16mf2_i16mf4(op1);
+  return a;
+}
+
+vint16mf4_t test_vlmul_trunc_v_i16m1_i16mf4(vint16m1_t op1)
+{
+  vint16mf4_t a = vlmul_trunc_v_i16m1_i16mf4(op1);
+  return a;
+}
+
+vint16mf2_t test_vlmul_trunc_v_i16m1_i16mf2(vint16m1_t op1)
+{
+  vint16mf2_t a = vlmul_trunc_v_i16m1_i16mf2(op1);
+  return a;
+}
+
+vint16mf4_t test_vlmul_trunc_v_i16m2_i16mf4(vint16m2_t op1)
+{
+  vint16mf4_t a = vlmul_trunc_v_i16m2_i16mf4(op1);
+  return a;
+}
+
+vint16mf2_t test_vlmul_trunc_v_i16m2_i16mf2(vint16m2_t op1)
+{
+  vint16mf2_t a = vlmul_trunc_v_i16m2_i16mf2(op1);
+  return a;
+}
+
+vint16m1_t test_vlmul_trunc_v_i16m2_i16m1(vint16m2_t op1)
+{
+  vint16m1_t a = vlmul_trunc_v_i16m2_i16m1(op1);
+  return a;
+}
+
+vint16mf4_t test_vlmul_trunc_v_i16m4_i16mf4(vint16m4_t op1)
+{
+  vint16mf4_t a = vlmul_trunc_v_i16m4_i16mf4(op1);
+  return a;
+}
+
+vint16mf2_t test_vlmul_trunc_v_i16m4_i16mf2(vint16m4_t op1)
+{
+  vint16mf2_t a = vlmul_trunc_v_i16m4_i16mf2(op1);
+  return a;
+}
+
+vint16m1_t test_vlmul_trunc_v_i16m4_i16m1(vint16m4_t op1)
+{
+  vint16m1_t a = vlmul_trunc_v_i16m4_i16m1(op1);
+  return a;
+}
+
+vint16m2_t test_vlmul_trunc_v_i16m4_i16m2(vint16m4_t op1)
+{
+  vint16m2_t a = vlmul_trunc_v_i16m4_i16m2(op1);
+  return a;
+}
+
+vint16mf4_t test_vlmul_trunc_v_i16m8_i16mf4(vint16m8_t op1)
+{
+  vint16mf4_t a = vlmul_trunc_v_i16m8_i16mf4(op1);
+  return a;
+}
+
+vint16mf2_t test_vlmul_trunc_v_i16m8_i16mf2(vint16m8_t op1)
+{
+  vint16mf2_t a = vlmul_trunc_v_i16m8_i16mf2(op1);
+  return a;
+}
+
+vint16m1_t test_vlmul_trunc_v_i16m8_i16m1(vint16m8_t op1)
+{
+  vint16m1_t a = vlmul_trunc_v_i16m8_i16m1(op1);
+  return a;
+}
+
+vint16m2_t test_vlmul_trunc_v_i16m8_i16m2(vint16m8_t op1)
+{
+  vint16m2_t a = vlmul_trunc_v_i16m8_i16m2(op1);
+  return a;
+}
+
+vint16m4_t test_vlmul_trunc_v_i16m8_i16m4(vint16m8_t op1)
+{
+  vint16m4_t a = vlmul_trunc_v_i16m8_i16m4(op1);
+  return a;
+}
+
+vint32mf2_t test_vlmul_trunc_v_i32m1_i32mf2(vint32m1_t op1)
+{
+  vint32mf2_t a = vlmul_trunc_v_i32m1_i32mf2(op1);
+  return a;
+}
+
+vint32mf2_t test_vlmul_trunc_v_i32m2_i32mf2(vint32m2_t op1)
+{
+  vint32mf2_t a = vlmul_trunc_v_i32m2_i32mf2(op1);
+  return a;
+}
+
+vint32m1_t test_vlmul_trunc_v_i32m2_i32m1(vint32m2_t op1)
+{
+  vint32m1_t a = vlmul_trunc_v_i32m2_i32m1(op1);
+  return a;
+}
+
+vint32mf2_t test_vlmul_trunc_v_i32m4_i32mf2(vint32m4_t op1)
+{
+  vint32mf2_t a = vlmul_trunc_v_i32m4_i32mf2(op1);
+  return a;
+}
+
+vint32m1_t test_vlmul_trunc_v_i32m4_i32m1(vint32m4_t op1)
+{
+  vint32m1_t a = vlmul_trunc_v_i32m4_i32m1(op1);
+  return a;
+}
+
+vint32m2_t test_vlmul_trunc_v_i32m4_i32m2(vint32m4_t op1)
+{
+  vint32m2_t a = vlmul_trunc_v_i32m4_i32m2(op1);
+  return a;
+}
+
+vint32mf2_t test_vlmul_trunc_v_i32m8_i32mf2(vint32m8_t op1)
+{
+  vint32mf2_t a = vlmul_trunc_v_i32m8_i32mf2(op1);
+  return a;
+}
+
+vint32m1_t test_vlmul_trunc_v_i32m8_i32m1(vint32m8_t op1)
+{
+  vint32m1_t a = vlmul_trunc_v_i32m8_i32m1(op1);
+  return a;
+}
+
+vint32m2_t test_vlmul_trunc_v_i32m8_i32m2(vint32m8_t op1)
+{
+  vint32m2_t a = vlmul_trunc_v_i32m8_i32m2(op1);
+  return a;
+}
+
+vint32m4_t test_vlmul_trunc_v_i32m8_i32m4(vint32m8_t op1)
+{
+  vint32m4_t a = vlmul_trunc_v_i32m8_i32m4(op1);
+  return a;
+}
+
+vint64m1_t test_vlmul_trunc_v_i64m2_i64m1(vint64m2_t op1)
+{
+  vint64m1_t a = vlmul_trunc_v_i64m2_i64m1(op1);
+  return a;
+}
+
+vint64m1_t test_vlmul_trunc_v_i64m4_i64m1(vint64m4_t op1)
+{
+  vint64m1_t a = vlmul_trunc_v_i64m4_i64m1(op1);
+  return a;
+}
+
+vint64m2_t test_vlmul_trunc_v_i64m4_i64m2(vint64m4_t op1)
+{
+  vint64m2_t a = vlmul_trunc_v_i64m4_i64m2(op1);
+  return a;
+}
+
+vint64m1_t test_vlmul_trunc_v_i64m8_i64m1(vint64m8_t op1)
+{
+  vint64m1_t a = vlmul_trunc_v_i64m8_i64m1(op1);
+  return a;
+}
+
+vint64m2_t test_vlmul_trunc_v_i64m8_i64m2(vint64m8_t op1)
+{
+  vint64m2_t a = vlmul_trunc_v_i64m8_i64m2(op1);
+  return a;
+}
+
+vint64m4_t test_vlmul_trunc_v_i64m8_i64m4(vint64m8_t op1)
+{
+  vint64m4_t a = vlmul_trunc_v_i64m8_i64m4(op1);
+  return a;
+}
+
+vuint8mf8_t test_vlmul_trunc_v_u8mf4_u8mf8(vuint8mf4_t op1)
+{
+  vuint8mf8_t a = vlmul_trunc_v_u8mf4_u8mf8(op1);
+  return a;
+}
+
+vuint8mf8_t test_vlmul_trunc_v_u8mf2_u8mf8(vuint8mf2_t op1)
+{
+  vuint8mf8_t a = vlmul_trunc_v_u8mf2_u8mf8(op1);
+  return a;
+}
+
+vuint8mf4_t test_vlmul_trunc_v_u8mf2_u8mf4(vuint8mf2_t op1)
+{
+  vuint8mf4_t a = vlmul_trunc_v_u8mf2_u8mf4(op1);
+  return a;
+}
+
+vuint8mf8_t test_vlmul_trunc_v_u8m1_u8mf8(vuint8m1_t op1)
+{
+  vuint8mf8_t a = vlmul_trunc_v_u8m1_u8mf8(op1);
+  return a;
+}
+
+vuint8mf4_t test_vlmul_trunc_v_u8m1_u8mf4(vuint8m1_t op1)
+{
+  vuint8mf4_t a = vlmul_trunc_v_u8m1_u8mf4(op1);
+  return a;
+}
+
+vuint8mf2_t test_vlmul_trunc_v_u8m1_u8mf2(vuint8m1_t op1)
+{
+  vuint8mf2_t a = vlmul_trunc_v_u8m1_u8mf2(op1);
+  return a;
+}
+
+vuint8mf8_t test_vlmul_trunc_v_u8m2_u8mf8(vuint8m2_t op1)
+{
+  vuint8mf8_t a = vlmul_trunc_v_u8m2_u8mf8(op1);
+  return a;
+}
+
+vuint8mf4_t test_vlmul_trunc_v_u8m2_u8mf4(vuint8m2_t op1)
+{
+  vuint8mf4_t a = vlmul_trunc_v_u8m2_u8mf4(op1);
+  return a;
+}
+
+vuint8mf2_t test_vlmul_trunc_v_u8m2_u8mf2(vuint8m2_t op1)
+{
+  vuint8mf2_t a = vlmul_trunc_v_u8m2_u8mf2(op1);
+  return a;
+}
+
+vuint8m1_t test_vlmul_trunc_v_u8m2_u8m1(vuint8m2_t op1)
+{
+  vuint8m1_t a = vlmul_trunc_v_u8m2_u8m1(op1);
+  return a;
+}
+
+vuint8mf8_t test_vlmul_trunc_v_u8m4_u8mf8(vuint8m4_t op1)
+{
+  vuint8mf8_t a = vlmul_trunc_v_u8m4_u8mf8(op1);
+  return a;
+}
+
+vuint8mf4_t test_vlmul_trunc_v_u8m4_u8mf4(vuint8m4_t op1)
+{
+  vuint8mf4_t a = vlmul_trunc_v_u8m4_u8mf4(op1);
+  return a;
+}
+
+vuint8mf2_t test_vlmul_trunc_v_u8m4_u8mf2(vuint8m4_t op1)
+{
+  vuint8mf2_t a = vlmul_trunc_v_u8m4_u8mf2(op1);
+  return a;
+}
+
+vuint8m1_t test_vlmul_trunc_v_u8m4_u8m1(vuint8m4_t op1)
+{
+  vuint8m1_t a = vlmul_trunc_v_u8m4_u8m1(op1);
+  return a;
+}
+
+vuint8m2_t test_vlmul_trunc_v_u8m4_u8m2(vuint8m4_t op1)
+{
+  vuint8m2_t a = vlmul_trunc_v_u8m4_u8m2(op1);
+  return a;
+}
+
+vuint8mf8_t test_vlmul_trunc_v_u8m8_u8mf8(vuint8m8_t op1)
+{
+  vuint8mf8_t a = vlmul_trunc_v_u8m8_u8mf8(op1);
+  return a;
+}
+
+vuint8mf4_t test_vlmul_trunc_v_u8m8_u8mf4(vuint8m8_t op1)
+{
+  vuint8mf4_t a = vlmul_trunc_v_u8m8_u8mf4(op1);
+  return a;
+}
+
+vuint8mf2_t test_vlmul_trunc_v_u8m8_u8mf2(vuint8m8_t op1)
+{
+  vuint8mf2_t a = vlmul_trunc_v_u8m8_u8mf2(op1);
+  return a;
+}
+
+vuint8m1_t test_vlmul_trunc_v_u8m8_u8m1(vuint8m8_t op1)
+{
+  vuint8m1_t a = vlmul_trunc_v_u8m8_u8m1(op1);
+  return a;
+}
+
+vuint8m2_t test_vlmul_trunc_v_u8m8_u8m2(vuint8m8_t op1)
+{
+  vuint8m2_t a = vlmul_trunc_v_u8m8_u8m2(op1);
+  return a;
+}
+
+vuint8m4_t test_vlmul_trunc_v_u8m8_u8m4(vuint8m8_t op1)
+{
+  vuint8m4_t a = vlmul_trunc_v_u8m8_u8m4(op1);
+  return a;
+}
+
+vuint16mf4_t test_vlmul_trunc_v_u16mf2_u16mf4(vuint16mf2_t op1)
+{
+  vuint16mf4_t a = vlmul_trunc_v_u16mf2_u16mf4(op1);
+  return a;
+}
+
+vuint16mf4_t test_vlmul_trunc_v_u16m1_u16mf4(vuint16m1_t op1)
+{
+  vuint16mf4_t a = vlmul_trunc_v_u16m1_u16mf4(op1);
+  return a;
+}
+
+vuint16mf2_t test_vlmul_trunc_v_u16m1_u16mf2(vuint16m1_t op1)
+{
+  vuint16mf2_t a = vlmul_trunc_v_u16m1_u16mf2(op1);
+  return a;
+}
+
+vuint16mf4_t test_vlmul_trunc_v_u16m2_u16mf4(vuint16m2_t op1)
+{
+  vuint16mf4_t a = vlmul_trunc_v_u16m2_u16mf4(op1);
+  return a;
+}
+
+vuint16mf2_t test_vlmul_trunc_v_u16m2_u16mf2(vuint16m2_t op1)
+{
+  vuint16mf2_t a = vlmul_trunc_v_u16m2_u16mf2(op1);
+  return a;
+}
+
+vuint16m1_t test_vlmul_trunc_v_u16m2_u16m1(vuint16m2_t op1)
+{
+  vuint16m1_t a = vlmul_trunc_v_u16m2_u16m1(op1);
+  return a;
+}
+
+vuint16mf4_t test_vlmul_trunc_v_u16m4_u16mf4(vuint16m4_t op1)
+{
+  vuint16mf4_t a = vlmul_trunc_v_u16m4_u16mf4(op1);
+  return a;
+}
+
+vuint16mf2_t test_vlmul_trunc_v_u16m4_u16mf2(vuint16m4_t op1)
+{
+  vuint16mf2_t a = vlmul_trunc_v_u16m4_u16mf2(op1);
+  return a;
+}
+
+vuint16m1_t test_vlmul_trunc_v_u16m4_u16m1(vuint16m4_t op1)
+{
+  vuint16m1_t a = vlmul_trunc_v_u16m4_u16m1(op1);
+  return a;
+}
+
+vuint16m2_t test_vlmul_trunc_v_u16m4_u16m2(vuint16m4_t op1)
+{
+  vuint16m2_t a = vlmul_trunc_v_u16m4_u16m2(op1);
+  return a;
+}
+
+vuint16mf4_t test_vlmul_trunc_v_u16m8_u16mf4(vuint16m8_t op1)
+{
+  vuint16mf4_t a = vlmul_trunc_v_u16m8_u16mf4(op1);
+  return a;
+}
+
+vuint16mf2_t test_vlmul_trunc_v_u16m8_u16mf2(vuint16m8_t op1)
+{
+  vuint16mf2_t a = vlmul_trunc_v_u16m8_u16mf2(op1);
+  return a;
+}
+
+vuint16m1_t test_vlmul_trunc_v_u16m8_u16m1(vuint16m8_t op1)
+{
+  vuint16m1_t a = vlmul_trunc_v_u16m8_u16m1(op1);
+  return a;
+}
+
+vuint16m2_t test_vlmul_trunc_v_u16m8_u16m2(vuint16m8_t op1)
+{
+  vuint16m2_t a = vlmul_trunc_v_u16m8_u16m2(op1);
+  return a;
+}
+
+vuint16m4_t test_vlmul_trunc_v_u16m8_u16m4(vuint16m8_t op1)
+{
+  vuint16m4_t a = vlmul_trunc_v_u16m8_u16m4(op1);
+  return a;
+}
+
+vuint32mf2_t test_vlmul_trunc_v_u32m1_u32mf2(vuint32m1_t op1)
+{
+  vuint32mf2_t a = vlmul_trunc_v_u32m1_u32mf2(op1);
+  return a;
+}
+
+vuint32mf2_t test_vlmul_trunc_v_u32m2_u32mf2(vuint32m2_t op1)
+{
+  vuint32mf2_t a = vlmul_trunc_v_u32m2_u32mf2(op1);
+  return a;
+}
+
+vuint32m1_t test_vlmul_trunc_v_u32m2_u32m1(vuint32m2_t op1)
+{
+  vuint32m1_t a = vlmul_trunc_v_u32m2_u32m1(op1);
+  return a;
+}
+
+vuint32mf2_t test_vlmul_trunc_v_u32m4_u32mf2(vuint32m4_t op1)
+{
+  vuint32mf2_t a = vlmul_trunc_v_u32m4_u32mf2(op1);
+  return a;
+}
+
+vuint32m1_t test_vlmul_trunc_v_u32m4_u32m1(vuint32m4_t op1)
+{
+  vuint32m1_t a = vlmul_trunc_v_u32m4_u32m1(op1);
+  return a;
+}
+
+vuint32m2_t test_vlmul_trunc_v_u32m4_u32m2(vuint32m4_t op1)
+{
+  vuint32m2_t a = vlmul_trunc_v_u32m4_u32m2(op1);
+  return a;
+}
+
+vuint32mf2_t test_vlmul_trunc_v_u32m8_u32mf2(vuint32m8_t op1)
+{
+  vuint32mf2_t a = vlmul_trunc_v_u32m8_u32mf2(op1);
+  return a;
+}
+
+vuint32m1_t test_vlmul_trunc_v_u32m8_u32m1(vuint32m8_t op1)
+{
+  vuint32m1_t a = vlmul_trunc_v_u32m8_u32m1(op1);
+  return a;
+}
+
+vuint32m2_t test_vlmul_trunc_v_u32m8_u32m2(vuint32m8_t op1)
+{
+  vuint32m2_t a = vlmul_trunc_v_u32m8_u32m2(op1);
+  return a;
+}
+
+vuint32m4_t test_vlmul_trunc_v_u32m8_u32m4(vuint32m8_t op1)
+{
+  vuint32m4_t a = vlmul_trunc_v_u32m8_u32m4(op1);
+  return a;
+}
+
+vuint64m1_t test_vlmul_trunc_v_u64m2_u64m1(vuint64m2_t op1)
+{
+  vuint64m1_t a = vlmul_trunc_v_u64m2_u64m1(op1);
+  return a;
+}
+
+vuint64m1_t test_vlmul_trunc_v_u64m4_u64m1(vuint64m4_t op1)
+{
+  vuint64m1_t a = vlmul_trunc_v_u64m4_u64m1(op1);
+  return a;
+}
+
+vuint64m2_t test_vlmul_trunc_v_u64m4_u64m2(vuint64m4_t op1)
+{
+  vuint64m2_t a = vlmul_trunc_v_u64m4_u64m2(op1);
+  return a;
+}
+
+vuint64m1_t test_vlmul_trunc_v_u64m8_u64m1(vuint64m8_t op1)
+{
+  vuint64m1_t a = vlmul_trunc_v_u64m8_u64m1(op1);
+  return a;
+}
+
+vuint64m2_t test_vlmul_trunc_v_u64m8_u64m2(vuint64m8_t op1)
+{
+  vuint64m2_t a = vlmul_trunc_v_u64m8_u64m2(op1);
+  return a;
+}
+
+vuint64m4_t test_vlmul_trunc_v_u64m8_u64m4(vuint64m8_t op1)
+{
+  vuint64m4_t a = vlmul_trunc_v_u64m8_u64m4(op1);
+  return a;
+}
+
+vfloat32mf2_t test_vlmul_trunc_v_f32m1_f32mf2(vfloat32m1_t op1)
+{
+  vfloat32mf2_t a = vlmul_trunc_v_f32m1_f32mf2(op1);
+  return a;
+}
+
+vfloat32mf2_t test_vlmul_trunc_v_f32m2_f32mf2(vfloat32m2_t op1)
+{
+  vfloat32mf2_t a = vlmul_trunc_v_f32m2_f32mf2(op1);
+  return a;
+}
+
+vfloat32m1_t test_vlmul_trunc_v_f32m2_f32m1(vfloat32m2_t op1)
+{
+  vfloat32m1_t a = vlmul_trunc_v_f32m2_f32m1(op1);
+  return a;
+}
+
+vfloat32mf2_t test_vlmul_trunc_v_f32m4_f32mf2(vfloat32m4_t op1)
+{
+  vfloat32mf2_t a = vlmul_trunc_v_f32m4_f32mf2(op1);
+  return a;
+}
+
+vfloat32m1_t test_vlmul_trunc_v_f32m4_f32m1(vfloat32m4_t op1)
+{
+  vfloat32m1_t a = vlmul_trunc_v_f32m4_f32m1(op1);
+  return a;
+}
+
+vfloat32m2_t test_vlmul_trunc_v_f32m4_f32m2(vfloat32m4_t op1)
+{
+  vfloat32m2_t a = vlmul_trunc_v_f32m4_f32m2(op1);
+  return a;
+}
+
+vfloat32mf2_t test_vlmul_trunc_v_f32m8_f32mf2(vfloat32m8_t op1)
+{
+  vfloat32mf2_t a = vlmul_trunc_v_f32m8_f32mf2(op1);
+  return a;
+}
+
+vfloat32m1_t test_vlmul_trunc_v_f32m8_f32m1(vfloat32m8_t op1)
+{
+  vfloat32m1_t a = vlmul_trunc_v_f32m8_f32m1(op1);
+  return a;
+}
+
+vfloat32m2_t test_vlmul_trunc_v_f32m8_f32m2(vfloat32m8_t op1)
+{
+  vfloat32m2_t a = vlmul_trunc_v_f32m8_f32m2(op1);
+  return a;
+}
+
+vfloat32m4_t test_vlmul_trunc_v_f32m8_f32m4(vfloat32m8_t op1)
+{
+  vfloat32m4_t a = vlmul_trunc_v_f32m8_f32m4(op1);
+  return a;
+}
+
+vfloat64m1_t test_vlmul_trunc_v_f64m2_f64m1(vfloat64m2_t op1)
+{
+  vfloat64m1_t a = vlmul_trunc_v_f64m2_f64m1(op1);
+  return a;
+}
+
+vfloat64m1_t test_vlmul_trunc_v_f64m4_f64m1(vfloat64m4_t op1)
+{
+  vfloat64m1_t a = vlmul_trunc_v_f64m4_f64m1(op1);
+  return a;
+}
+
+vfloat64m2_t test_vlmul_trunc_v_f64m4_f64m2(vfloat64m4_t op1)
+{
+  vfloat64m2_t a = vlmul_trunc_v_f64m4_f64m2(op1);
+  return a;
+}
+
+vfloat64m1_t test_vlmul_trunc_v_f64m8_f64m1(vfloat64m8_t op1)
+{
+  vfloat64m1_t a = vlmul_trunc_v_f64m8_f64m1(op1);
+  return a;
+}
+
+vfloat64m2_t test_vlmul_trunc_v_f64m8_f64m2(vfloat64m8_t op1)
+{
+  vfloat64m2_t a = vlmul_trunc_v_f64m8_f64m2(op1);
+  return a;
+}
+
+vfloat64m4_t test_vlmul_trunc_v_f64m8_f64m4(vfloat64m8_t op1)
+{
+  vfloat64m4_t a = vlmul_trunc_v_f64m8_f64m4(op1);
+  return a;
+}
+
+vint8mf8_t test_vundefined_i8mf8()
+{
+  vint8mf8_t a = vundefined_i8mf8();
+  return a;
+}
+
+vint8mf4_t test_vundefined_i8mf4()
+{
+  vint8mf4_t a = vundefined_i8mf4();
+  return a;
+}
+
+vint8mf2_t test_vundefined_i8mf2()
+{
+  vint8mf2_t a = vundefined_i8mf2();
+  return a;
+}
+
+vint8m1_t test_vundefined_i8m1()
+{
+  vint8m1_t a = vundefined_i8m1();
+  return a;
+}
+
+vint8m2_t test_vundefined_i8m2()
+{
+  vint8m2_t a = vundefined_i8m2();
+  return a;
+}
+
+vint8m4_t test_vundefined_i8m4()
+{
+  vint8m4_t a = vundefined_i8m4();
+  return a;
+}
+
+vint8m8_t test_vundefined_i8m8()
+{
+  vint8m8_t a = vundefined_i8m8();
+  return a;
+}
+
+vint16mf4_t test_vundefined_i16mf4()
+{
+  vint16mf4_t a = vundefined_i16mf4();
+  return a;
+}
+
+vint16mf2_t test_vundefined_i16mf2()
+{
+  vint16mf2_t a = vundefined_i16mf2();
+  return a;
+}
+
+vint16m1_t test_vundefined_i16m1()
+{
+  vint16m1_t a = vundefined_i16m1();
+  return a;
+}
+
+vint16m2_t test_vundefined_i16m2()
+{
+  vint16m2_t a = vundefined_i16m2();
+  return a;
+}
+
+vint16m4_t test_vundefined_i16m4()
+{
+  vint16m4_t a = vundefined_i16m4();
+  return a;
+}
+
+vint16m8_t test_vundefined_i16m8()
+{
+  vint16m8_t a = vundefined_i16m8();
+  return a;
+}
+
+vint32mf2_t test_vundefined_i32mf2()
+{
+  vint32mf2_t a = vundefined_i32mf2();
+  return a;
+}
+
+vint32m1_t test_vundefined_i32m1()
+{
+  vint32m1_t a = vundefined_i32m1();
+  return a;
+}
+
+vint32m2_t test_vundefined_i32m2()
+{
+  vint32m2_t a = vundefined_i32m2();
+  return a;
+}
+
+vint32m4_t test_vundefined_i32m4()
+{
+  vint32m4_t a = vundefined_i32m4();
+  return a;
+}
+
+vint32m8_t test_vundefined_i32m8()
+{
+  vint32m8_t a = vundefined_i32m8();
+  return a;
+}
+
+vint64m1_t test_vundefined_i64m1()
+{
+  vint64m1_t a = vundefined_i64m1();
+  return a;
+}
+
+vint64m2_t test_vundefined_i64m2()
+{
+  vint64m2_t a = vundefined_i64m2();
+  return a;
+}
+
+vint64m4_t test_vundefined_i64m4()
+{
+  vint64m4_t a = vundefined_i64m4();
+  return a;
+}
+
+vint64m8_t test_vundefined_i64m8()
+{
+  vint64m8_t a = vundefined_i64m8();
+  return a;
+}
+
+vuint8mf8_t test_vundefined_u8mf8()
+{
+  vuint8mf8_t a = vundefined_u8mf8();
+  return a;
+}
+
+vuint8mf4_t test_vundefined_u8mf4()
+{
+  vuint8mf4_t a = vundefined_u8mf4();
+  return a;
+}
+
+vuint8mf2_t test_vundefined_u8mf2()
+{
+  vuint8mf2_t a = vundefined_u8mf2();
+  return a;
+}
+
+vuint8m1_t test_vundefined_u8m1()
+{
+  vuint8m1_t a = vundefined_u8m1();
+  return a;
+}
+
+vuint8m2_t test_vundefined_u8m2()
+{
+  vuint8m2_t a = vundefined_u8m2();
+  return a;
+}
+
+vuint8m4_t test_vundefined_u8m4()
+{
+  vuint8m4_t a = vundefined_u8m4();
+  return a;
+}
+
+vuint8m8_t test_vundefined_u8m8()
+{
+  vuint8m8_t a = vundefined_u8m8();
+  return a;
+}
+
+vuint16mf4_t test_vundefined_u16mf4()
+{
+  vuint16mf4_t a = vundefined_u16mf4();
+  return a;
+}
+
+vuint16mf2_t test_vundefined_u16mf2()
+{
+  vuint16mf2_t a = vundefined_u16mf2();
+  return a;
+}
+
+vuint16m1_t test_vundefined_u16m1()
+{
+  vuint16m1_t a = vundefined_u16m1();
+  return a;
+}
+
+vuint16m2_t test_vundefined_u16m2()
+{
+  vuint16m2_t a = vundefined_u16m2();
+  return a;
+}
+
+vuint16m4_t test_vundefined_u16m4()
+{
+  vuint16m4_t a = vundefined_u16m4();
+  return a;
+}
+
+vuint16m8_t test_vundefined_u16m8()
+{
+  vuint16m8_t a = vundefined_u16m8();
+  return a;
+}
+
+vuint32mf2_t test_vundefined_u32mf2()
+{
+  vuint32mf2_t a = vundefined_u32mf2();
+  return a;
+}
+
+vuint32m1_t test_vundefined_u32m1()
+{
+  vuint32m1_t a = vundefined_u32m1();
+  return a;
+}
+
+vuint32m2_t test_vundefined_u32m2()
+{
+  vuint32m2_t a = vundefined_u32m2();
+  return a;
+}
+
+vuint32m4_t test_vundefined_u32m4()
+{
+  vuint32m4_t a = vundefined_u32m4();
+  return a;
+}
+
+vuint32m8_t test_vundefined_u32m8()
+{
+  vuint32m8_t a = vundefined_u32m8();
+  return a;
+}
+
+vuint64m1_t test_vundefined_u64m1()
+{
+  vuint64m1_t a = vundefined_u64m1();
+  return a;
+}
+
+vuint64m2_t test_vundefined_u64m2()
+{
+  vuint64m2_t a = vundefined_u64m2();
+  return a;
+}
+
+vuint64m4_t test_vundefined_u64m4()
+{
+  vuint64m4_t a = vundefined_u64m4();
+  return a;
+}
+
+vuint64m8_t test_vundefined_u64m8()
+{
+  vuint64m8_t a = vundefined_u64m8();
+  return a;
+}
+
+vfloat32mf2_t test_vundefined_f32mf2()
+{
+  vfloat32mf2_t a = vundefined_f32mf2();
+  return a;
+}
+
+vfloat32m1_t test_vundefined_f32m1()
+{
+  vfloat32m1_t a = vundefined_f32m1();
+  return a;
+}
+
+vfloat32m2_t test_vundefined_f32m2()
+{
+  vfloat32m2_t a = vundefined_f32m2();
+  return a;
+}
+
+vfloat32m4_t test_vundefined_f32m4()
+{
+  vfloat32m4_t a = vundefined_f32m4();
+  return a;
+}
+
+vfloat32m8_t test_vundefined_f32m8()
+{
+  vfloat32m8_t a = vundefined_f32m8();
+  return a;
+}
+
+vfloat64m1_t test_vundefined_f64m1()
+{
+  vfloat64m1_t a = vundefined_f64m1();
+  return a;
+}
+
+vfloat64m2_t test_vundefined_f64m2()
+{
+  vfloat64m2_t a = vundefined_f64m2();
+  return a;
+}
+
+vfloat64m4_t test_vundefined_f64m4()
+{
+  vfloat64m4_t a = vundefined_f64m4();
+  return a;
+}
+
+vfloat64m8_t test_vundefined_f64m8()
+{
+  vfloat64m8_t a = vundefined_f64m8();
+  return a;
+}