Show patches with: Search = RISC-V       |    Archived = No       |   3475 patches
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Patch Series rb/tb S/W/F Date Submitter Delegate State
[v1] RISC-V: Refine the testcases for cond_widen_complicate-3 [v1] RISC-V: Refine the testcases for cond_widen_complicate-3 - - 12-- 2025-03-12 Li, Pan2 rdapp Accepted
RISC-V: Mask values before initializing bitmask vector [PR119114]. RISC-V: Mask values before initializing bitmask vector [PR119114]. - - 6-- 2025-03-11 Robin Dapp New
RISC-V: Do not delete fused vsetvl if it has uses [PR119115]. RISC-V: Do not delete fused vsetvl if it has uses [PR119115]. - - 11-- 2025-03-07 Robin Dapp JeffreyALaw Committed
[to-be-committed,RISC-V,PR,rtl-optimization/119099] Avoid infinite loop in ext-dce. [to-be-committed,RISC-V,PR,rtl-optimization/119099] Avoid infinite loop in ext-dce. - - 10-1 2025-03-06 Jeff Law JeffreyALaw Committed
[v1] RISC-V: Tweak asm check for test case multiple_rgroup_zbb.c [v1] RISC-V: Tweak asm check for test case multiple_rgroup_zbb.c - - 11-1 2025-03-06 Li, Pan2 JeffreyALaw Committed
[v2] RISC-V: Adjust LMUL when using maximum SEW [PR117955]. [v2] RISC-V: Adjust LMUL when using maximum SEW [PR117955]. - - 11-1 2025-03-05 Robin Dapp JeffreyALaw Committed
RISC-V: Imply C from Zca whenever possible [PR119122] RISC-V: Imply C from Zca whenever possible [PR119122] - - 111- 2025-03-05 Yuriy Kolerov New
RISC-V: Using O2 instead of O1 in testsuites when using -fdump-ext_dce RISC-V: Using O2 instead of O1 in testsuites when using -fdump-ext_dce - - 12-- 2025-03-03 Liao Shihua JeffreyALaw Superseded
[v1] RISC-V: Fix the test case bug-3.c failure [v1] RISC-V: Fix the test case bug-3.c failure - - 12-- 2025-03-03 Li, Pan2 rdapp Committed
[to-be-committed,RISC-V,PR,target/116256] Fix minor code quality regression in reassociated arithme… [to-be-committed,RISC-V,PR,target/116256] Fix minor code quality regression in reassociated arithme… - - 11-1 2025-03-02 Jeff Law JeffreyALaw Changes Requested
[to-be-committed,RISC-V,PR,target/118934] Fix ICE in RISC-V long branch supportvi !$ [to-be-committed,RISC-V,PR,target/118934] Fix ICE in RISC-V long branch supportvi !$ - - 911 2025-03-02 Jeff Law JeffreyALaw Committed
RISC-V: Adjust LMUL when using maximum SEW [PR117955]. RISC-V: Adjust LMUL when using maximum SEW [PR117955]. - - 11-1 2025-02-27 Robin Dapp Superseded
[v5] RISC-V: Fix bug for expand_const_vector interleave [PR118931] [v5] RISC-V: Fix bug for expand_const_vector interleave [PR118931] - - 12-- 2025-02-27 Li, Pan2 Committed
[v4] RISC-V: Fix bug for expand_const_vector interleave [PR118931] [v4] RISC-V: Fix bug for expand_const_vector interleave [PR118931] - - 10-- 2025-02-27 Li, Pan2 Superseded
[v3] RISC-V: Fix bug for expand_const_vector interleave [PR118931] [v3] RISC-V: Fix bug for expand_const_vector interleave [PR118931] - - 11-1 2025-02-26 Li, Pan2 Superseded
[v2] RISC-V: Fix bug for expand_const_vector interleave [PR118931] [v2] RISC-V: Fix bug for expand_const_vector interleave [PR118931] - - 11-1 2025-02-25 Li, Pan2 rdapp Superseded
RISC-V: Avoid updating vl right before branching on avl RISC-V: Avoid updating vl right before branching on avl - - 111- 2025-02-25 Edwin Lu Deferred
RISC-V: Include pattern stmts for dynamic LMUL computation [PR114516]. RISC-V: Include pattern stmts for dynamic LMUL computation [PR114516]. - - 9-2 2025-02-24 Robin Dapp JuzheZhong Committed
[v2] RISC-V: Fix a typo in zce to zcf implication [v2] RISC-V: Fix a typo in zce to zcf implication - - 12-- 2025-02-24 Yuriy Kolerov kitoc Committed
[v1] RISC-V: Fix bug for expand_const_vector interleave [PR118931] [v1] RISC-V: Fix bug for expand_const_vector interleave [PR118931] - - 11-1 2025-02-23 Li, Pan2 rdapp Superseded
RISC-V: Minimal support for Qualcomm uC Xqccmp extension. RISC-V: Minimal support for Qualcomm uC Xqccmp extension. - - 111- 2025-02-20 chendongyan JeffreyALaw Deferred
[RFC] RISC-V: The optimization ignored the side effects of the rounding mode, resulting in incorrec… [RFC] RISC-V: The optimization ignored the side effects of the rounding mode, resulting in incorrec… - - 55- 2025-02-18 Jin Ma JeffreyALaw Rejected
[to-be-committed,RISC-V,PR,target/118248] Avoid bogus alloca call in RISC-V backend [to-be-committed,RISC-V,PR,target/118248] Avoid bogus alloca call in RISC-V backend - - 10-2 2025-02-16 Jeff Law JeffreyALaw Committed
[v1] RISC-V: Fix ICE for target attributes has different xlen size [v1] RISC-V: Fix ICE for target attributes has different xlen size - - 101- 2025-02-15 Li, Pan2 JeffreyALaw Committed
[RISC-V] Tune for removal unnecessary sext in builtin overflows [PR108016] [RISC-V] Tune for removal unnecessary sext in builtin overflows [PR108016] - - 10-- 2025-02-14 Alexey Merzlyakov JeffreyALaw Deferred
[2/2] RISC-V: Implement TARGET_COMPUTE_MULTILIB_OS [1/2] Add TARGET_COMPUTE_MULTILIB_OS hook to override multi-lib-os result. - - 91- 2025-02-14 Jin Ma palmer Superseded
RISC-V: Fix some dynamic LMUL costing. RISC-V: Fix some dynamic LMUL costing. - - 9-1 2025-02-14 Robin Dapp JeffreyALaw Deferred
RISC-V: Fix some widen-complicate tests. RISC-V: Fix some widen-complicate tests. - - 91- 2025-02-14 Robin Dapp JeffreyALaw Committed
RISC-V: testsuite: Fix reduc-[89].c again. RISC-V: testsuite: Fix reduc-[89].c again. - - 10-- 2025-02-14 Robin Dapp JeffreyALaw Committed
RISC-V: testsuite: Adjust pr117722.c scan. RISC-V: testsuite: Adjust pr117722.c scan. - - 10-- 2025-02-14 Robin Dapp JeffreyALaw Committed
RISC-V: Bugfix ICE for RVV intrinisc when using no-extension parameters RISC-V: Bugfix ICE for RVV intrinisc when using no-extension parameters 1 - 9-1 2025-02-14 Jin Ma palmer Committed
[V3] RISC-V: Prevent speculative vsetvl insn scheduling [V3] RISC-V: Prevent speculative vsetvl insn scheduling - - 111- 2025-02-13 Edwin Lu JeffreyALaw Deferred
[V2] RISC-V: Prevent speculative vsetvl insn scheduling [V2] RISC-V: Prevent speculative vsetvl insn scheduling - - 11-- 2025-02-13 Edwin Lu Superseded
RISC-V: Prevent speculative vsetvl insn scheduling RISC-V: Prevent speculative vsetvl insn scheduling - - 10-- 2025-02-12 Edwin Lu Superseded
RISC-V: Avoid more unsplit insns in const expander [PR118832]. RISC-V: Avoid more unsplit insns in const expander [PR118832]. - - 11-- 2025-02-12 Robin Dapp JuzheZhong Committed
[COMMITTED] RISC-V: Vector pesudoinsns with x0 operand to use imm 0 [COMMITTED] RISC-V: Vector pesudoinsns with x0 operand to use imm 0 - - 8-3 2025-02-12 Vineet Gupta Committed
[v2] RISC-V: unrecognizable insn ICE in xtheadvector/pr114194.c on 32bit targets [v2] RISC-V: unrecognizable insn ICE in xtheadvector/pr114194.c on 32bit targets - - 12-- 2025-02-11 Jin Ma Committed
RISC-V: Drop __riscv_vendor_feature_bits RISC-V: Drop __riscv_vendor_feature_bits - - 12-- 2025-02-11 Yangyu Chen Committed
[committed,RISC-V,PR,target/115123] Fix testsuite fallout from sinking heuristic change [committed,RISC-V,PR,target/115123] Fix testsuite fallout from sinking heuristic change - - 6-4 2025-02-09 Jeff Law Committed
RISC-V: unrecognizable insn ICE in xtheadvector/pr114194.c on 32bit targets RISC-V: unrecognizable insn ICE in xtheadvector/pr114194.c on 32bit targets - - 111- 2025-02-09 Jin Ma kitoc Superseded
[to-be-committed,RISC-V,PR,target/118146] Fix ICE for unsupported modes [to-be-committed,RISC-V,PR,target/118146] Fix ICE for unsupported modes - - 10-2 2025-02-09 Jeff Law Committed
RISC-V: Add missing mode in bsetclr_zero_extract pattern RISC-V: Add missing mode in bsetclr_zero_extract pattern - - 12-- 2025-02-08 Liao Shihua JeffreyALaw Rejected
[v2] RISC-V: Vector pesudoinsns with x0 operand to use imm 0 [v2] RISC-V: Vector pesudoinsns with x0 operand to use imm 0 - - 12-- 2025-02-08 Vineet Gupta Committed
RISC-V: Vector pesudoinsns with x0 operand to use imm 0. (toggle) RISC-V: Vector pesudoinsns with x0 operand to use imm 0. (toggle) - - 111- 2025-02-07 Vineet Gupta Superseded
[v1] RISC-V: Make VXRM as global register [PR118103] [v1] RISC-V: Make VXRM as global register [PR118103] - - 11-1 2025-02-07 Li, Pan2 rdapp Committed
[committed,RISC-V] Fix risc-v expected test output after recent iv changes [committed,RISC-V] Fix risc-v expected test output after recent iv changes - - 6-4 2025-02-06 Jeff Law Committed
RISC-V: Fix ratio in vsetvl fuse rule [PR115703]. RISC-V: Fix ratio in vsetvl fuse rule [PR115703]. - - 11-1 2025-02-06 Robin Dapp JuzheZhong Committed
RISC-V: Move UNSPEC_SSP_SET and UNSPEC_SSP_TEST to correct enum RISC-V: Move UNSPEC_SSP_SET and UNSPEC_SSP_TEST to correct enum - - 6-4 2025-02-06 Craig Blackmore JeffreyALaw Committed
loop-iv, riscv: Fix get_biv_step_1 for RISC-V [PR117506] loop-iv, riscv: Fix get_biv_step_1 for RISC-V [PR117506] - - 5-1 2025-02-05 Jakub Jelinek Committed
[committed] testsuite: RISC-V: Ignore pr118170.c for E ABI [committed] testsuite: RISC-V: Ignore pr118170.c for E ABI - - 6-2 2025-02-04 Dimitar Dimitrov Committed
[v2] RISC-V: Fix wrong LMUL when only implict zve32f. [v2] RISC-V: Fix wrong LMUL when only implict zve32f. - - 91- 2025-02-04 Monk Chiang rdapp Superseded
RISC-V: Fix wrong LMUL when only implict zve32f. RISC-V: Fix wrong LMUL when only implict zve32f. - - 81- 2025-02-04 Monk Chiang Superseded
[COMMITTED] RISC-V: Add another test for FRM elimination bug [PR118646] [COMMITTED] RISC-V: Add another test for FRM elimination bug [PR118646] - - 10-- 2025-01-27 Vineet Gupta Committed
[v3,4/4] RISC-V: Fix incorrect code gen for scalar signed SAT_TRUNC [PR117688] [v3,1/4] RISC-V: Refactor SAT_* operand rtx extend to reg help func [NFC] - - 10-- 2025-01-27 Li, Pan2 JeffreyALaw Committed
[v3,3/4] RISC-V: Fix incorrect code gen for scalar signed SAT_SUB [PR117688] [v3,1/4] RISC-V: Refactor SAT_* operand rtx extend to reg help func [NFC] - - 10-- 2025-01-27 Li, Pan2 JeffreyALaw Committed
[v3,2/4] RISC-V: Fix incorrect code gen for scalar signed SAT_ADD [PR117688] [v3,1/4] RISC-V: Refactor SAT_* operand rtx extend to reg help func [NFC] - - 10-- 2025-01-27 Li, Pan2 JeffreyALaw Committed
[v3,1/4] RISC-V: Refactor SAT_* operand rtx extend to reg help func [NFC] [v3,1/4] RISC-V: Refactor SAT_* operand rtx extend to reg help func [NFC] - - 10-- 2025-01-27 Li, Pan2 JeffreyALaw Committed
libstdc++: correct symbol version of typeinfo for bfloat16_t on RISC-V libstdc++: correct symbol version of typeinfo for bfloat16_t on RISC-V - - 6-2 2025-01-27 Andreas Schwab Committed
RISC-V: testsuite: Fix reduc-8.c and reduc-9.c RISC-V: testsuite: Fix reduc-8.c and reduc-9.c - - 10-- 2025-01-27 Robin Dapp Committed
RISC-V: testsuite: Fix gather_load_64-12-zvbb.c RISC-V: testsuite: Fix gather_load_64-12-zvbb.c - - 10-- 2025-01-27 Robin Dapp Committed
[v1] RISC-V: Remove unnecessary frm restore volatile define_insn [v1] RISC-V: Remove unnecessary frm restore volatile define_insn - - 10-- 2025-01-26 Li, Pan2 Deferred
[v2] RISC-V: Make FRM as global register [PR118103] [PR118646] [v2] RISC-V: Make FRM as global register [PR118103] [PR118646] - - 9-1 2025-01-26 Li, Pan2 Committed
[to-be-committed,RISC-V,PR,target/116256] Improve handling of single bit constants [to-be-committed,RISC-V,PR,target/116256] Improve handling of single bit constants - - 811 2025-01-25 Jeff Law Committed
[v1] RISC-V: Make FRM as global register [PR118103] [PR118646] [v1] RISC-V: Make FRM as global register [PR118103] [PR118646] - - 10-- 2025-01-25 Li, Pan2 Superseded
RISC-V: ensure needed FRM restore is not eliminable [PR118646] RISC-V: ensure needed FRM restore is not eliminable [PR118646] - - 9-1 2025-01-24 Vineet Gupta Deferred
[v2,4/4] RISC-V: Fix incorrect code gen for scalar signed SAT_TRUNC [PR117688] [v2,1/4] RISC-V: Refactor SAT_* operand rtx extend to reg help func [NFC] - - 10-- 2025-01-23 Li, Pan2 JeffreyALaw Superseded
[v2,3/4] RISC-V: Fix incorrect code gen for scalar signed SAT_SUB [PR117688] [v2,1/4] RISC-V: Refactor SAT_* operand rtx extend to reg help func [NFC] - - 10-- 2025-01-23 Li, Pan2 JeffreyALaw Superseded
[v2,2/4] RISC-V: Fix incorrect code gen for scalar signed SAT_ADD [PR117688] [v2,1/4] RISC-V: Refactor SAT_* operand rtx extend to reg help func [NFC] - - 91- 2025-01-23 Li, Pan2 JeffreyALaw Superseded
[v2,1/4] RISC-V: Refactor SAT_* operand rtx extend to reg help func [NFC] [v2,1/4] RISC-V: Refactor SAT_* operand rtx extend to reg help func [NFC] - - 91- 2025-01-23 Li, Pan2 JeffreyALaw Superseded
RISC-V: Disable two-source permutes for now [PR117173]. RISC-V: Disable two-source permutes for now [PR117173]. - - 711 2025-01-22 Robin Dapp JeffreyALaw Committed
[v5] RISC-V: Add a new constraint to ensure that the vl of XTheadVector does not get a non-zero imm… [v5] RISC-V: Add a new constraint to ensure that the vl of XTheadVector does not get a non-zero imm… - - 712 2025-01-21 Jin Ma JeffreyALaw Committed
[v2] RISC-V: Enable and adjust the testsuite for XTheadVector. [v2] RISC-V: Enable and adjust the testsuite for XTheadVector. - - 7-3 2025-01-21 Jin Ma JeffreyALaw Committed
[to-be-committed,RISC-V,PR,target/116256] Fix incorrect return value for predicate [to-be-committed,RISC-V,PR,target/116256] Fix incorrect return value for predicate - - 10-- 2025-01-21 Jeff Law Committed
[2/2] RISC-V: Support RISC-V Profiles 23. RISC-V: Support RISC-V Profiles. - - 91- 2025-01-21 Jiawei Deferred
[v2,1/2] RISC-V: Support RISC-V Profiles 20/22. RISC-V: Support RISC-V Profiles. - - 91- 2025-01-21 Jiawei Deferred
[V5,2/2] RISC-V: Add intrinsics testcases for SiFive Xsfvcp extensions. RISC-V: Add intrinsics support and testcases for SiFive Xsfvcp extension. - - 91- 2025-01-21 yulong kitoc Deferred
[V5,1/2] RISC-V: Add intrinsics support for SiFive Xsfvcp extensions. RISC-V: Add intrinsics support and testcases for SiFive Xsfvcp extension. - - 91- 2025-01-21 yulong kitoc Deferred
[to-be-committed,RISC-V,PR,target/116256] Fix latent regression in pattern to associate arithmetic … [to-be-committed,RISC-V,PR,target/116256] Fix latent regression in pattern to associate arithmetic … - - 8-1 2025-01-20 Jeff Law JeffreyALaw Committed
[v1] RISC-V: Fix incorrect code gen for scalar signed SAT_SUB [PR117688] [v1] RISC-V: Fix incorrect code gen for scalar signed SAT_SUB [PR117688] - - 10-- 2025-01-20 Li, Pan2 Superseded
[committed] RISC-V: Add sifive_vector.h [committed] RISC-V: Add sifive_vector.h - - 422 2025-01-20 Kito Cheng Committed
[v2] RISC-V: Correct the mode that is causing the program to fail for XTheadCondMov [v2] RISC-V: Correct the mode that is causing the program to fail for XTheadCondMov - - 10-- 2025-01-20 Jin Ma JeffreyALaw Committed
RISC-V: Fix a typo in zce to zcf implication RISC-V: Fix a typo in zce to zcf implication - - 10-- 2025-01-19 Yuriy Kolerov rdapp Superseded
RISC-V: Fix ICE when prefetching addresses less than 12 bits for zicbop RISC-V: Fix ICE when prefetching addresses less than 12 bits for zicbop - - 10-- 2025-01-19 Jin Ma JeffreyALaw Rejected
RISC-V: Correct the mode that is causing the program to fail for XTheadCondMov RISC-V: Correct the mode that is causing the program to fail for XTheadCondMov - - 10-- 2025-01-19 Jin Ma Superseded
[v4] RISC-V: Add a new constraint to ensure that the vl of XTheadVector does not produce a non-zero… [v4] RISC-V: Add a new constraint to ensure that the vl of XTheadVector does not produce a non-zero… - - 91- 2025-01-19 Jin Ma JeffreyALaw Superseded
[to-be-committed,RISC-V,PR,target/116308] Fix generation of initial RTL for atomics [to-be-committed,RISC-V,PR,target/116308] Fix generation of initial RTL for atomics - - 6-2 2025-01-18 Jeff Law JeffreyALaw Committed
RISC-V: Disable fusing vsetvl instructions by VSETVL_VTYPE_CHANGE_ONLY for XTheadVector. RISC-V: Disable fusing vsetvl instructions by VSETVL_VTYPE_CHANGE_ONLY for XTheadVector. - - 10-- 2025-01-17 Jin Ma rdapp Committed
RISC-V: Enable and adjust the testsuite for XTheadVector. RISC-V: Enable and adjust the testsuite for XTheadVector. - - 9-1 2025-01-17 Jin Ma JeffreyALaw Superseded
[v3,2/2] RISC-V: Add a new constraint to ensure that the vl of XTheadVector does not produce a non-… [v3,1/2] RISC-V: Allocate the initial register in the expand phase for the vl of XTheadVector - - 9-- 2025-01-17 Jin Ma JeffreyALaw Superseded
[v3,1/2] RISC-V: Allocate the initial register in the expand phase for the vl of XTheadVector [v3,1/2] RISC-V: Allocate the initial register in the expand phase for the vl of XTheadVector - - 7-- 2025-01-17 Jin Ma JeffreyALaw Superseded
[v5,4/4] RISC-V: Add -fcf-protection=[full|branch|return] to enable zicfiss, zicfilp. [v5,1/4] RISC-V: Add Zicfiss ISA extension. - - 91- 2025-01-16 Monk Chiang Committed
[v5,3/4] RISC-V: Add .note.gnu.property for ZICFILP and ZICFISS ISA extension [v5,1/4] RISC-V: Add Zicfiss ISA extension. - - 81- 2025-01-16 Monk Chiang Committed
[v5,2/4] RISC-V: Add Zicfilp ISA extension. [v5,1/4] RISC-V: Add Zicfiss ISA extension. - - 71- 2025-01-16 Monk Chiang Committed
[v5,1/4] RISC-V: Add Zicfiss ISA extension. [v5,1/4] RISC-V: Add Zicfiss ISA extension. - - 51- 2025-01-16 Monk Chiang Committed
[v4,4/4] RISC-V: Add -fcf-protection=[full|branch|return] to enable zicfiss, zicfilp. [v4,1/4] RISC-V: Add Zicfiss ISA extension. - - 91- 2025-01-16 Monk Chiang Dropped
[v4,3/4] RISC-V: Add .note.gnu.property for ZICFILP and ZICFISS ISA extension [v4,1/4] RISC-V: Add Zicfiss ISA extension. - - 81- 2025-01-16 Monk Chiang Dropped
[v4,2/4] RISC-V: Add Zicfilp ISA extension. [v4,1/4] RISC-V: Add Zicfiss ISA extension. - - 71- 2025-01-16 Monk Chiang Dropped
[v4,1/4] RISC-V: Add Zicfiss ISA extension. [v4,1/4] RISC-V: Add Zicfiss ISA extension. - - 71- 2025-01-16 Monk Chiang Dropped
[v3,4/4] RISC-V: Add -fcf-protection=[full|branch|return] to enable zicfiss, zicfilp. [v3,1/4] RISC-V: Add Zicfiss ISA extension. - - 81- 2025-01-15 Monk Chiang Dropped
[v3,3/4] RISC-V: Add .note.gnu.property for ZICFILP and ZICFISS ISA extension [v3,1/4] RISC-V: Add Zicfiss ISA extension. - - 51- 2025-01-15 Monk Chiang Dropped
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