diff mbox series

[COMMITTED] RISC-V: Vector pesudoinsns with x0 operand to use imm 0

Message ID 20250212040141.15541-1-vineetg@rivosinc.com
State Committed
Commit 3880271e94b7598b4f5d98c615b7fcddddee6d4c
Headers
Series [COMMITTED] RISC-V: Vector pesudoinsns with x0 operand to use imm 0 |

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Commit Message

Vineet Gupta Feb. 12, 2025, 4:01 a.m. UTC 
  A couple of Vector pseudoinstructions use x0 scalar which could be
inefficient on wider uarches due to regfile crossing.

Instead use the imm 0 form, which should be functionally equivalent.

 pseudoinsn            orig insn with x0     this patch
 --------------------  --------------------  -------------------
 vneg.v vd,vs          vrsub.vx vd,vs,x0     vrsub.vi vd,vs,0
 vncvt.x.x.w vd,vs,vm  vnsrl.wx vd,vs,x0,vm  vnsrl.wi vd,vs,0,vm
 vwcvt.x.x.v vd,vs,vm  vwadd.vx vd,vs,x0,vm  (imm not supported)

gcc/ChangeLog:
	* config/riscv/vector.md: vncvt substitute vnsrl.
	vnsrl with x0 replace with immediate 0.
	vneg substitute vrsub.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv32-1.c: Change
	expected pattern.
	* gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv32-2.c: Ditto.
	* gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv64-1.c: Ditto.
	* gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv64-2.c: Ditto.
	* gcc.target/riscv/rvv/autovec/cond/cond_unary-1.c: Ditto.
	* gcc.target/riscv/rvv/autovec/cond/cond_unary-2.c: Ditto.
	* gcc.target/riscv/rvv/autovec/cond/cond_unary-3.c: Ditto.
	* gcc.target/riscv/rvv/autovec/cond/cond_unary-4.c: Ditto.
	* gcc.target/riscv/rvv/autovec/cond/cond_unary-5.c: Ditto.
	* gcc.target/riscv/rvv/autovec/cond/cond_unary-6.c: Ditto.
	* gcc.target/riscv/rvv/autovec/cond/cond_unary-7.c: Ditto.
	* gcc.target/riscv/rvv/autovec/cond/cond_unary-8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/conversions/vncvt-rv32gcv.c: Ditto.
	* gcc.target/riscv/rvv/autovec/conversions/vncvt-rv64gcv.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-1-u16.c: Ditto
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-1-u32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-1-u8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/unop/abs-rv32gcv.c: Ditto.
	* gcc.target/riscv/rvv/autovec/unop/abs-rv64gcv.c: Ditto.
	* gcc.target/riscv/rvv/autovec/unop/vneg-rv32gcv.c: Ditto.
	* gcc.target/riscv/rvv/autovec/unop/vneg-rv64gcv.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls/abs-2.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls/cond_convert-11.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls/cond_convert-12.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls/cond_neg-1.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls/cond_trunc-1.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls/cond_trunc-2.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls/cond_trunc-3.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls/convert-11.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls/convert-12.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls/neg-1.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls/trunc-1.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls/trunc-2.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls/trunc-3.c: Ditto.
	* gcc.target/riscv/rvv/base/simplify-vdiv.c: Ditto.
	* gcc.target/riscv/rvv/base/unop_v_constraint-1.c: Ditto.

Signed-off-by: Vineet Gupta <vineetg@rivosinc.com>
---
 gcc/config/riscv/vector.md                    | 16 ++++++++++---
 .../cond/cond_convert_int2int-rv32-1.c        |  4 ++--
 .../cond/cond_convert_int2int-rv32-2.c        |  4 ++--
 .../cond/cond_convert_int2int-rv64-1.c        |  4 ++--
 .../cond/cond_convert_int2int-rv64-2.c        |  4 ++--
 .../riscv/rvv/autovec/cond/cond_unary-1.c     |  6 ++---
 .../riscv/rvv/autovec/cond/cond_unary-2.c     |  6 ++---
 .../riscv/rvv/autovec/cond/cond_unary-3.c     |  6 ++---
 .../riscv/rvv/autovec/cond/cond_unary-4.c     |  6 ++---
 .../riscv/rvv/autovec/cond/cond_unary-5.c     |  6 ++---
 .../riscv/rvv/autovec/cond/cond_unary-6.c     |  6 ++---
 .../riscv/rvv/autovec/cond/cond_unary-7.c     |  6 ++---
 .../riscv/rvv/autovec/cond/cond_unary-8.c     |  6 ++---
 .../rvv/autovec/conversions/vncvt-rv32gcv.c   |  2 +-
 .../rvv/autovec/conversions/vncvt-rv64gcv.c   |  2 +-
 .../autovec/sat/vec_sat_u_sub_trunc-1-u16.c   |  2 +-
 .../autovec/sat/vec_sat_u_sub_trunc-1-u32.c   |  2 +-
 .../autovec/sat/vec_sat_u_sub_trunc-1-u8.c    |  2 +-
 .../riscv/rvv/autovec/unop/abs-rv32gcv.c      |  2 +-
 .../riscv/rvv/autovec/unop/abs-rv64gcv.c      |  2 +-
 .../riscv/rvv/autovec/unop/vneg-rv32gcv.c     |  2 +-
 .../riscv/rvv/autovec/unop/vneg-rv64gcv.c     |  2 +-
 .../gcc.target/riscv/rvv/autovec/vls/abs-2.c  |  2 +-
 .../riscv/rvv/autovec/vls/cond_convert-11.c   |  2 +-
 .../riscv/rvv/autovec/vls/cond_convert-12.c   |  2 +-
 .../riscv/rvv/autovec/vls/cond_neg-1.c        |  2 +-
 .../riscv/rvv/autovec/vls/cond_trunc-1.c      |  2 +-
 .../riscv/rvv/autovec/vls/cond_trunc-2.c      |  2 +-
 .../riscv/rvv/autovec/vls/cond_trunc-3.c      |  2 +-
 .../riscv/rvv/autovec/vls/convert-11.c        |  2 +-
 .../riscv/rvv/autovec/vls/convert-12.c        |  2 +-
 .../gcc.target/riscv/rvv/autovec/vls/neg-1.c  |  2 +-
 .../riscv/rvv/autovec/vls/trunc-1.c           |  2 +-
 .../riscv/rvv/autovec/vls/trunc-2.c           |  2 +-
 .../riscv/rvv/autovec/vls/trunc-3.c           |  2 +-
 .../gcc.target/riscv/rvv/base/simplify-vdiv.c |  2 +-
 .../riscv/rvv/base/unop_v_constraint-1.c      | 24 +++++++++----------
 37 files changed, 80 insertions(+), 70 deletions(-)
diff mbox series

Patch

diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index cf22b39d6cb3..8ee43cf0ce1c 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -3904,7 +3904,10 @@ 
 	    (match_operand:V_VLSI 3 "register_operand"       "vr,vr, vr, vr"))
 	  (match_operand:V_VLSI 2 "vector_merge_operand"     "vu, 0, vu,  0")))]
   "TARGET_VECTOR"
-  "v<insn>.v\t%0,%3%p1"
+  {
+    /* vneg.v = vrsub vd,vs,x0 = vrsub vd,vs,0.  */
+    return (<CODE> == NEG) ? "vrsub.vi\t%0,%3,0%p1" : "v<insn>.v\t%0,%3%p1";
+  }
   [(set_attr "type" "vialu")
    (set_attr "mode" "<MODE>")
    (set_attr "vl_op_idx" "4")
@@ -4258,7 +4261,13 @@ 
 	     (match_operand 4 "pmode_reg_or_uimm5_operand"             " rK, rK, rK, rK,   rK,   rK")))
 	  (match_operand:<V_DOUBLE_TRUNC> 2 "vector_merge_operand"     " vu,  0, vu,  0,   vu,    0")))]
   "TARGET_VECTOR"
-  "vn<insn>.w%o4\t%0,%3,%4%p1"
+  {
+    /* vnsrl vd,vs,x0 = vnsrl vd,vs,0.  */
+    if (REG_P (operands[4]) && REGNO (operands[4]) == 0)
+      return "vn<insn>.wi\t%0,%3,0%p1";
+
+    return "vn<insn>.w%o4\t%0,%3,%4%p1";
+  }
   [(set_attr "type" "vnshift")
    (set_attr "mode" "<V_DOUBLE_TRUNC>")
    (set_attr "spec_restriction" "none,none,thv,thv,none,none")])
@@ -4279,7 +4288,8 @@ 
 	    (match_operand:VWEXTI 3 "register_operand"                 "  0,  0,  0,  0,   vr,   vr"))
 	  (match_operand:<V_DOUBLE_TRUNC> 2 "vector_merge_operand"     " vu,  0, vu,  0,   vu,    0")))]
   "TARGET_VECTOR"
-  "vncvt.x.x.w\t%0,%3%p1"
+  ;; vncvt.x.x.w = vnsrl vd,vs,x0 = vnsrl vd,vs,0
+  "vnsrl.wi\t%0,%3,0%p1";
   [(set_attr "type" "vnshift")
    (set_attr "mode" "<V_DOUBLE_TRUNC>")
    (set_attr "vl_op_idx" "4")
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv32-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv32-1.c
index 5eb6030e348a..50f2ac6843be 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv32-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv32-1.c
@@ -10,8 +10,8 @@ 
 /* { dg-final { scan-assembler-times {\tvzext\.vf8\tv[0-9]+,v[0-9]+,v0\.t} 1 } } */
 /* { dg-final { scan-assembler-times {\tvsext\.vf8\tv[0-9]+,v[0-9]+,v0\.t} 1 } } */
 
-/* { dg-final { scan-assembler-times {\tvncvt\.x\.x\.w\tv[0-9]+,v[0-9]+,v0\.t} 12 } } */
-/* { dg-final { scan-assembler-times {\tvncvt\.x\.x\.w\tv[0-9]+,v[0-9]+\n} 8 } } */
+/* { dg-final { scan-assembler-times {\tvnsrl\.wi\tv[0-9]+,v[0-9]+,0,v0\.t} 12 } } */
+/* { dg-final { scan-assembler-times {\tvnsrl\.wi\tv[0-9]+,v[0-9]+,0\n} 8 } } */
 
 /* { dg-final { scan-assembler {\tvsetvli\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu} } } */
 /* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv32-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv32-2.c
index aa6d6d4b7f16..dc84325a6133 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv32-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv32-2.c
@@ -10,8 +10,8 @@ 
 /* { dg-final { scan-assembler-times {\tvzext\.vf8\tv[0-9]+,v[0-9]+,v0\.t} 1 } } */
 /* { dg-final { scan-assembler-times {\tvsext\.vf8\tv[0-9]+,v[0-9]+,v0\.t} 1 } } */
 
-/* { dg-final { scan-assembler-times {\tvncvt\.x\.x\.w\tv[0-9]+,v[0-9]+,v0\.t} 12 } } */
-/* { dg-final { scan-assembler-times {\tvncvt\.x\.x\.w\tv[0-9]+,v[0-9]+\n} 8 } } */
+/* { dg-final { scan-assembler-times {\tvnsrl\.wi\tv[0-9]+,v[0-9]+,0,v0\.t} 12 } } */
+/* { dg-final { scan-assembler-times {\tvnsrl\.wi\tv[0-9]+,v[0-9]+,0\n} 8 } } */
 
 /* { dg-final { scan-assembler {\tvsetvli\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu} } } */
 /* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv64-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv64-1.c
index 33cb9918ef91..980868d84689 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv64-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv64-1.c
@@ -10,8 +10,8 @@ 
 /* { dg-final { scan-assembler-times {\tvzext\.vf8\tv[0-9]+,v[0-9]+,v0\.t} 1 } } */
 /* { dg-final { scan-assembler-times {\tvsext\.vf8\tv[0-9]+,v[0-9]+,v0\.t} 1 } } */
 
-/* { dg-final { scan-assembler-times {\tvncvt\.x\.x\.w\tv[0-9]+,v[0-9]+,v0\.t} 12 } } */
-/* { dg-final { scan-assembler-times {\tvncvt\.x\.x\.w\tv[0-9]+,v[0-9]+\n} 8 } } */
+/* { dg-final { scan-assembler-times {\tvnsrl\.wi\tv[0-9]+,v[0-9]+,0,v0\.t} 12 } } */
+/* { dg-final { scan-assembler-times {\tvnsrl\.wi\tv[0-9]+,v[0-9]+,0\n} 8 } } */
 
 /* { dg-final { scan-assembler {\tvsetvli\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu} } } */
 /* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv64-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv64-2.c
index 082d9e1ed9aa..ecfeaabb701e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv64-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv64-2.c
@@ -10,8 +10,8 @@ 
 /* { dg-final { scan-assembler-times {\tvzext\.vf8\tv[0-9]+,v[0-9]+,v0\.t} 1 } } */
 /* { dg-final { scan-assembler-times {\tvsext\.vf8\tv[0-9]+,v[0-9]+,v0\.t} 1 } } */
 
-/* { dg-final { scan-assembler-times {\tvncvt\.x\.x\.w\tv[0-9]+,v[0-9]+,v0\.t} 12 } } */
-/* { dg-final { scan-assembler-times {\tvncvt\.x\.x\.w\tv[0-9]+,v[0-9]+\n} 8 } } */
+/* { dg-final { scan-assembler-times {\tvnsrl\.wi\tv[0-9]+,v[0-9]+,0,v0\.t} 12 } } */
+/* { dg-final { scan-assembler-times {\tvnsrl\.wi\tv[0-9]+,v[0-9]+,0\n} 8 } } */
 
 /* { dg-final { scan-assembler {\tvsetvli\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu} } } */
 /* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-1.c
index 4866b221ca4a..e908eba0b116 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-1.c
@@ -36,10 +36,10 @@ 
 
 TEST_ALL (DEF_LOOP)
 
-/* NOTE: int abs operator is converted to vneg.v + vmax.vv */
-/* { dg-final { scan-assembler-times {\tvneg\.v\tv[0-9]+,v[0-9]+} 8 } } */
+/* NOTE: int abs operator is converted to vneg.v (or vsrub.vi) + vmax.vv */
+/* { dg-final { scan-assembler-times {\tvrsub\.vi\tv[0-9]+,v[0-9]+} 8 } } */
 /* { dg-final { scan-assembler-times {\tvmax\.vv\tv[0-9]+,v[0-9]+,v[0-9]+} 4 } } */
-/* { dg-final { scan-assembler-times {\tvneg\.v\tv[0-9]+,v[0-9]+,v0\.t} 4 } } */
+/* { dg-final { scan-assembler-times {\tvrsub\.vi\tv[0-9]+,v[0-9]+,0,v0\.t} 4 } } */
 /* { dg-final { scan-assembler-times {\tvnot\.v\tv[0-9]+,v[0-9]+,v0\.t} 4 } } */
 /* { dg-final { scan-assembler-times {\tvfabs\.v\tv[0-9]+,v[0-9]+,v0\.t} 3 } } */
 /* { dg-final { scan-assembler-times {\tvfneg\.v\tv[0-9]+,v[0-9]+,v0\.t} 3 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-2.c
index 651df9f86461..8b8a3f4f16bc 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-2.c
@@ -39,10 +39,10 @@ 
 
 TEST_ALL (DEF_LOOP)
 
-/* NOTE: int abs operator is converted to vneg.v + vmax.vv */
-/* { dg-final { scan-assembler-times {\tvneg\.v\tv[0-9]+,v[0-9]+} 8 } } */
+/* NOTE: int abs operator is converted to vneg.v (or vsrub.vi) + vmax.vv */
+/* { dg-final { scan-assembler-times {\tvrsub\.vi\tv[0-9]+,v[0-9]+} 8 } } */
 /* { dg-final { scan-assembler-times {\tvmax\.vv\tv[0-9]+,v[0-9]+,v[0-9]+} 4 } } */
-/* { dg-final { scan-assembler-times {\tvneg\.v\tv[0-9]+,v[0-9]+,v0\.t} 4 } } */
+/* { dg-final { scan-assembler-times {\tvrsub\.vi\tv[0-9]+,v[0-9]+,0,v0\.t} 4 } } */
 /* { dg-final { scan-assembler-times {\tvnot\.v\tv[0-9]+,v[0-9]+,v0\.t} 4 } } */
 /* { dg-final { scan-assembler-times {\tvfabs\.v\tv[0-9]+,v[0-9]+,v0\.t} 3 } } */
 /* { dg-final { scan-assembler-times {\tvfneg\.v\tv[0-9]+,v[0-9]+,v0\.t} 3 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-3.c
index cc5f7883a649..6c098a9a8287 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-3.c
@@ -36,10 +36,10 @@ 
 
 TEST_ALL (DEF_LOOP)
 
-/* NOTE: int abs operator is converted to vneg.v + vmax.vv */
-/* { dg-final { scan-assembler-times {\tvneg\.v\tv[0-9]+,v[0-9]+} 8 } } */
+/* NOTE: int abs operator is converted to vneg.v (or vsrub.vi) + vmax.vv */
+/* { dg-final { scan-assembler-times {\tvrsub\.vi\tv[0-9]+,v[0-9]+} 8 } } */
 /* { dg-final { scan-assembler-times {\tvmax\.vv\tv[0-9]+,v[0-9]+,v[0-9]+} 4 } } */
-/* { dg-final { scan-assembler-times {\tvneg\.v\tv[0-9]+,v[0-9]+,v0\.t} 4 } } */
+/* { dg-final { scan-assembler-times {\tvrsub\.vi\tv[0-9]+,v[0-9]+,0,v0\.t} 4 } } */
 /* { dg-final { scan-assembler-times {\tvnot\.v\tv[0-9]+,v[0-9]+,v0\.t} 4 } } */
 /* { dg-final { scan-assembler-times {\tvfabs\.v\tv[0-9]+,v[0-9]+,v0\.t} 3 } } */
 /* { dg-final { scan-assembler-times {\tvfneg\.v\tv[0-9]+,v[0-9]+,v0\.t} 3 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-4.c
index b5f83444c5c9..6dd9ff6a2d33 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-4.c
@@ -36,10 +36,10 @@ 
 
 TEST_ALL (DEF_LOOP)
 
-/* NOTE: int abs operator is converted to vneg.v + vmax.vv */
-/* { dg-final { scan-assembler-times {\tvneg\.v\tv[0-9]+,v[0-9]+} 8 } } */
+/* NOTE: int abs operator is converted to vneg.v (or vsrub.vi) + vmax.vv */
+/* { dg-final { scan-assembler-times {\tvrsub\.vi\tv[0-9]+,v[0-9]+} 8 } } */
 /* { dg-final { scan-assembler-times {\tvmax\.vv\tv[0-9]+,v[0-9]+,v[0-9]+} 4 } } */
-/* { dg-final { scan-assembler-times {\tvneg\.v\tv[0-9]+,v[0-9]+,v0\.t} 4 } } */
+/* { dg-final { scan-assembler-times {\tvrsub\.vi\tv[0-9]+,v[0-9]+,0,v0\.t} 4 } } */
 /* { dg-final { scan-assembler-times {\tvnot\.v\tv[0-9]+,v[0-9]+,v0\.t} 4 } } */
 /* { dg-final { scan-assembler-times {\tvfabs\.v\tv[0-9]+,v[0-9]+,v0\.t} 3 } } */
 /* { dg-final { scan-assembler-times {\tvfneg\.v\tv[0-9]+,v[0-9]+,v0\.t} 3 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-5.c
index 76089549fbaf..613a29950a68 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-5.c
@@ -31,10 +31,10 @@ 
 
 TEST_ALL (DEF_LOOP)
 
-/* NOTE: int abs operator is converted to vneg.v + vmax.vv */
-/* { dg-final { scan-assembler-times {\tvneg\.v\tv[0-9]+,v[0-9]+} 12 } } */
+/* NOTE: int abs operator is converted to vneg.v (or vsrub.vi) + vmax.vv */
+/* { dg-final { scan-assembler-times {\tvrsub\.vi\tv[0-9]+,v[0-9]+} 12 } } */
 /* { dg-final { scan-assembler-times {\tvmax\.vv\tv[0-9]+,v[0-9]+,v[0-9]+} 6 } } */
-/* { dg-final { scan-assembler-times {\tvneg\.v\tv[0-9]+,v[0-9]+,v0\.t} 6 } } */
+/* { dg-final { scan-assembler-times {\tvrsub\.vi\tv[0-9]+,v[0-9]+,0,v0\.t} 6 } } */
 /* { dg-final { scan-assembler-times {\tvnot\.v\tv[0-9]+,v[0-9]+,v0\.t} 6 } } */
 /* NOTE: int abs operator cannot combine the vmerge.  */
 /* { dg-final { scan-assembler-times {\tvf?merge\.v[vxi]m\t} 6 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-6.c
index 6dfb57e52c00..8008f5b4c6de 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-6.c
@@ -34,10 +34,10 @@ 
 
 TEST_ALL (DEF_LOOP)
 
-/* NOTE: int abs operator is converted to vneg.v + vmax.vv */
-/* { dg-final { scan-assembler-times {\tvneg\.v\tv[0-9]+,v[0-9]+} 12 } } */
+/* NOTE: int abs operator is converted to vneg.v (or vsrub.vi) + vmax.vv */
+/* { dg-final { scan-assembler-times {\tvrsub\.vi\tv[0-9]+,v[0-9]+} 12 } } */
 /* { dg-final { scan-assembler-times {\tvmax\.vv\tv[0-9]+,v[0-9]+,v[0-9]+} 6 } } */
-/* { dg-final { scan-assembler-times {\tvneg\.v\tv[0-9]+,v[0-9]+,v0\.t} 6 } } */
+/* { dg-final { scan-assembler-times {\tvrsub\.vi\tv[0-9]+,v[0-9]+,0,v0\.t} 6 } } */
 /* { dg-final { scan-assembler-times {\tvnot\.v\tv[0-9]+,v[0-9]+,v0\.t} 6 } } */
 /* NOTE: int abs operator cannot combine the vmerge.  */
 /* { dg-final { scan-assembler-times {\tvf?merge\.v[vxi]m\t} 6 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-7.c
index ca24a3320556..e5456b7f6a35 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-7.c
@@ -31,10 +31,10 @@ 
 
 TEST_ALL (DEF_LOOP)
 
-/* NOTE: int abs operator is converted to vneg.v + vmax.vv */
-/* { dg-final { scan-assembler-times {\tvneg\.v\tv[0-9]+,v[0-9]+} 12 } } */
+/* NOTE: int abs operator is converted to vneg.v (or vsrub.vi) + vmax.vv */
+/* { dg-final { scan-assembler-times {\tvrsub\.vi\tv[0-9]+,v[0-9]+} 12 } } */
 /* { dg-final { scan-assembler-times {\tvmax\.vv\tv[0-9]+,v[0-9]+,v[0-9]+} 6 } } */
-/* { dg-final { scan-assembler-times {\tvneg\.v\tv[0-9]+,v[0-9]+,v0\.t} 6 } } */
+/* { dg-final { scan-assembler-times {\tvrsub\.vi\tv[0-9]+,v[0-9]+,0,v0\.t} 6 } } */
 /* { dg-final { scan-assembler-times {\tvnot\.v\tv[0-9]+,v[0-9]+,v0\.t} 6 } } */
 /* NOTE: int abs operator cannot combine the vmerge.  */
 /* { dg-final { scan-assembler-times {\tvf?merge\.v[vxi]m\t} 6 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-8.c
index 7be4b373a2c5..c88f87675757 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-8.c
@@ -31,10 +31,10 @@ 
 
 TEST_ALL (DEF_LOOP)
 
-/* NOTE: int abs operator is converted to vneg.v + vmax.vv */
-/* { dg-final { scan-assembler-times {\tvneg\.v\tv[0-9]+,v[0-9]+} 12 } } */
+/* NOTE: int abs operator is converted to vneg.v (or vsrub.vi) + vmax.vv */
+/* { dg-final { scan-assembler-times {\tvrsub\.vi\tv[0-9]+,v[0-9]+} 12 } } */
 /* { dg-final { scan-assembler-times {\tvmax\.vv\tv[0-9]+,v[0-9]+,v[0-9]+} 6 } } */
-/* { dg-final { scan-assembler-times {\tvneg\.v\tv[0-9]+,v[0-9]+,v0\.t} 6 } } */
+/* { dg-final { scan-assembler-times {\tvrsub\.vi\tv[0-9]+,v[0-9]+,0,v0\.t} 6 } } */
 /* { dg-final { scan-assembler-times {\tvnot\.v\tv[0-9]+,v[0-9]+,v0\.t} 6 } } */
 /* NOTE: int abs operator cannot combine the vmerge.  */
 /* { dg-final { scan-assembler-times {\tvf?merge\.v[vxi]m\t} 6 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vncvt-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vncvt-rv32gcv.c
index cc3d6245e122..011248c24383 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vncvt-rv32gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vncvt-rv32gcv.c
@@ -3,4 +3,4 @@ 
 
 #include "vncvt-template.h"
 
-/* { dg-final { scan-assembler-times {\tvncvt.x.x.w} 10 } } */
+/* { dg-final { scan-assembler-times {\tvnsrl.wi} 10 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vncvt-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vncvt-rv64gcv.c
index 0b43787c13c1..9e58f5d5211c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vncvt-rv64gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vncvt-rv64gcv.c
@@ -3,4 +3,4 @@ 
 
 #include "vncvt-template.h"
 
-/* { dg-final { scan-assembler-times {\tvncvt.x.x.w} 10 } } */
+/* { dg-final { scan-assembler-times {\tvnsrl.wi} 10 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-1-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-1-u16.c
index 2d00b9bbb82e..2261872e3de2 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-1-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-1-u16.c
@@ -7,4 +7,4 @@  DEF_VEC_SAT_U_SUB_TRUNC_FMT_1(uint16_t, uint32_t)
 
 /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */
 /* { dg-final { scan-assembler-times {vssubu\.vx} 1 } } */
-/* { dg-final { scan-assembler-times {vncvt\.x\.x\.w} 1 } } */
+/* { dg-final { scan-assembler-times {vnsrl\.wi} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-1-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-1-u32.c
index 287adf0480cd..4250567686a6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-1-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-1-u32.c
@@ -7,4 +7,4 @@  DEF_VEC_SAT_U_SUB_TRUNC_FMT_1(uint32_t, uint64_t)
 
 /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */
 /* { dg-final { scan-assembler-times {vssubu\.vx} 1 } } */
-/* { dg-final { scan-assembler-times {vncvt\.x\.x\.w} 1 } } */
+/* { dg-final { scan-assembler-times {vnsrl\.wi} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-1-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-1-u8.c
index 946480ce8565..656aad70165c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-1-u8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-1-u8.c
@@ -7,4 +7,4 @@  DEF_VEC_SAT_U_SUB_TRUNC_FMT_1(uint8_t, uint16_t)
 
 /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */
 /* { dg-final { scan-assembler-times {vssubu\.vx} 1 } } */
-/* { dg-final { scan-assembler-times {vncvt\.x\.x\.w} 1 } } */
+/* { dg-final { scan-assembler-times {vnsrl\.wi} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-rv32gcv.c
index 3f62d0eafe7a..379df7fb3e6d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-rv32gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-rv32gcv.c
@@ -4,6 +4,6 @@ 
 #include "abs-template.h"
 
 /* { dg-final { scan-assembler-times {\tvseti?vli\s+[a-z0-9,]+,ta,ma} 7 } } */
-/* { dg-final { scan-assembler-times {\tvneg\.v} 4 } } */
+/* { dg-final { scan-assembler-times {\tvrsub\.vi} 4 } } */
 /* { dg-final { scan-assembler-times {\tvmax\.vv\sv[0-9]+,v[0-9]+,v[0-9]+} 4 } } */
 /* { dg-final { scan-assembler-times {\tvfabs.v} 3 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-rv64gcv.c
index 64302191cdac..e75ae2e15a15 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-rv64gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-rv64gcv.c
@@ -4,6 +4,6 @@ 
 #include "abs-template.h"
 
 /* { dg-final { scan-assembler-times {\tvseti?vli\s+[a-z0-9,]+,ta,ma} 7 } } */
-/* { dg-final { scan-assembler-times {\tvneg\.v} 4 } } */
+/* { dg-final { scan-assembler-times {\tvrsub\.vi} 4 } } */
 /* { dg-final { scan-assembler-times {\tvmax\.vv\sv[0-9]+,v[0-9]+,v[0-9]+} 4 } } */
 /* { dg-final { scan-assembler-times {\tvfabs.v} 3 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-rv32gcv.c
index 66b512eee206..3ea1dc3ab523 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-rv32gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-rv32gcv.c
@@ -3,5 +3,5 @@ 
 
 #include "vneg-template.h"
 
-/* { dg-final { scan-assembler-times {\tvneg\.v} 4 } } */
+/* { dg-final { scan-assembler-times {\tvrsub\.vi} 4 } } */
 /* { dg-final { scan-assembler-times {\tvfneg\.v} 3 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-rv64gcv.c
index d32c6a187c13..ed84820b17ff 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-rv64gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-rv64gcv.c
@@ -3,5 +3,5 @@ 
 
 #include "vneg-template.h"
 
-/* { dg-final { scan-assembler-times {\tvneg\.v} 4 } } */
+/* { dg-final { scan-assembler-times {\tvrsub\.vi} 4 } } */
 /* { dg-final { scan-assembler-times {\tvfneg\.v} 3 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/abs-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/abs-2.c
index 510939a0c154..e0272ddd3764 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/abs-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/abs-2.c
@@ -45,7 +45,7 @@  DEF_OP_V (neg, 128, int64_t, __builtin_abs)
 DEF_OP_V (neg, 256, int64_t, __builtin_abs)
 DEF_OP_V (neg, 512, int64_t, __builtin_abs)
 
-/* { dg-final { scan-assembler-times {vneg\.v} 38 } } */
+/* { dg-final { scan-assembler-times {vrsub\.vi} 38 } } */
 /* { dg-final { scan-assembler-times {vmax\.vv} 38 } } */
 /* { dg-final { scan-assembler-not {csrr} } } */
 /* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-11.c
index 2a9a9ada0eb7..07740f8d6101 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-11.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-11.c
@@ -37,7 +37,7 @@  DEF_COND_FP_CONVERT (fncvt, df, uhi, uint16_t, 128)
 DEF_COND_FP_CONVERT (fncvt, df, uhi, uint16_t, 256)
 DEF_COND_FP_CONVERT (fncvt, df, uhi, uint16_t, 512)
 
-/* { dg-final { scan-assembler-times {vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 30 } } */
+/* { dg-final { scan-assembler-times {vnsrl\.wi\s+v[0-9]+,\s*v[0-9]+,0,\s*v0.t} 30 } } */
 /* { dg-final { scan-assembler-not {csrr} } } */
 /* { dg-final { scan-assembler-not {vmerge} } } */
 /* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-12.c
index 4444ad8dfb48..cc5a7cda04cd 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-12.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-12.c
@@ -19,7 +19,7 @@  DEF_COND_FP_CONVERT (fncvt, df, uqi, uint8_t, 128)
 DEF_COND_FP_CONVERT (fncvt, df, uqi, uint8_t, 256)
 DEF_COND_FP_CONVERT (fncvt, df, uqi, uint8_t, 512)
 
-/* { dg-final { scan-assembler-times {vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 14 } } */
+/* { dg-final { scan-assembler-times {vnsrl\.wi\s+v[0-9]+,\s*v[0-9]+,0,\s*v0.t} 14 } } */
 /* { dg-final { scan-assembler-not {csrr} } } */
 /* { dg-final { scan-assembler-not {vmerge} } } */
 /* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_neg-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_neg-1.c
index 1da9312fa694..f356887f84bc 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_neg-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_neg-1.c
@@ -45,7 +45,7 @@  DEF_COND_UNOP (cond_neg, 128, v128di, -)
 DEF_COND_UNOP (cond_neg, 256, v256di, -)
 DEF_COND_UNOP (cond_neg, 512, v512di, -)
 
-/* { dg-final { scan-assembler-times {vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 38 } } */
+/* { dg-final { scan-assembler-times {vrsub\.vi\s+v[0-9]+,\s*v[0-9]+,0,\s*v0.t} 38 } } */
 /* { dg-final { scan-assembler-not {csrr} } } */
 /* { dg-final { scan-assembler-not {vmerge} } } */
 /* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_trunc-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_trunc-1.c
index dce94c587e43..7b3bc5e17c47 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_trunc-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_trunc-1.c
@@ -55,7 +55,7 @@  DEF_COND_CONVERT (trunc, v128udi, v128usi, 128)
 DEF_COND_CONVERT (trunc, v256udi, v256usi, 256)
 DEF_COND_CONVERT (trunc, v512udi, v512usi, 512)
 
-/* { dg-final { scan-assembler-times {vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 46 } } */
+/* { dg-final { scan-assembler-times {vnsrl\.wi\s+v[0-9]+,\s*v[0-9]+,0,\s*v0.t} 46 } } */
 /* { dg-final { scan-assembler-not {csrr} } } */
 /* { dg-final { scan-assembler-not {vmerge} } } */
 /* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_trunc-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_trunc-2.c
index 2a0d8bdf6c67..fa7ef1918ee5 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_trunc-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_trunc-2.c
@@ -37,7 +37,7 @@  DEF_COND_CONVERT (trunc, v128udi, v128uhi, 128)
 DEF_COND_CONVERT (trunc, v256udi, v256uhi, 256)
 DEF_COND_CONVERT (trunc, v512udi, v512uhi, 512)
 
-/* { dg-final { scan-assembler-times {vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 30 } } */
+/* { dg-final { scan-assembler-times {vnsrl\.wi\s+v[0-9]+,\s*v[0-9]+,0,\s*v0.t} 30 } } */
 /* { dg-final { scan-assembler-not {csrr} } } */
 /* { dg-final { scan-assembler-not {vmerge} } } */
 /* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_trunc-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_trunc-3.c
index 510c656b7ccc..532c50bf800c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_trunc-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_trunc-3.c
@@ -19,7 +19,7 @@  DEF_COND_CONVERT (trunc, v128udi, v128uqi, 128)
 DEF_COND_CONVERT (trunc, v256udi, v256uqi, 256)
 DEF_COND_CONVERT (trunc, v512udi, v512uqi, 512)
 
-/* { dg-final { scan-assembler-times {vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 14 } } */
+/* { dg-final { scan-assembler-times {vnsrl\.wi\s+v[0-9]+,\s*v[0-9]+,0,\s*v0.t} 14 } } */
 /* { dg-final { scan-assembler-not {csrr} } } */
 /* { dg-final { scan-assembler-not {vmerge} } } */
 /* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-11.c
index 9f96da75cbd7..c3191fd30ab4 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-11.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-11.c
@@ -38,7 +38,7 @@  DEF_CONVERT (fncvt, double, uint16_t, 256)
 DEF_CONVERT (fncvt, double, uint16_t, 512)
 
 /* { dg-final { scan-assembler-times {vfncvt\.rtz\.x\.f.w} 30 } } */
-/* { dg-final { scan-assembler-times {vncvt\.x\.x\.w} 30 } } */
+/* { dg-final { scan-assembler-times {vnsrl\.wi} 30 } } */
 /* { dg-final { scan-assembler-not {csrr} } } */
 /* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */
 /* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-12.c
index 858c915d44a9..730195cd5546 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-12.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-12.c
@@ -20,7 +20,7 @@  DEF_CONVERT (fncvt, double, uint8_t, 256)
 DEF_CONVERT (fncvt, double, uint8_t, 512)
 
 /* { dg-final { scan-assembler-times {vfncvt\.rtz\.x\.f.w} 14 } } */
-/* { dg-final { scan-assembler-times {vncvt\.x\.x\.w} 28 } } */
+/* { dg-final { scan-assembler-times {vnsrl\.wi} 28 } } */
 /* { dg-final { scan-assembler-not {csrr} } } */
 /* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */
 /* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/neg-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/neg-1.c
index fb58d2e6d7d9..305a53351677 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/neg-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/neg-1.c
@@ -53,5 +53,5 @@  DEF_OP_V (neg, 128, int64_t, -)
 DEF_OP_V (neg, 256, int64_t, -)
 DEF_OP_V (neg, 512, int64_t, -)
 
-/* { dg-final { scan-assembler-times {vneg\.v\s+v[0-9]+,\s*v[0-9]+} 42 } } */
+/* { dg-final { scan-assembler-times {vrsub\.vi\s+v[0-9]+,\s*v[0-9]+,\s*0} 42 } } */
 /* { dg-final { scan-assembler-not {csrr} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/trunc-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/trunc-1.c
index c197db32114e..dbb671c14a8d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/trunc-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/trunc-1.c
@@ -55,7 +55,7 @@  DEF_CONVERT (trunc, uint64_t, uint32_t, 64)
 DEF_CONVERT (trunc, uint64_t, uint32_t, 128)
 DEF_CONVERT (trunc, uint64_t, uint32_t, 256)
 
-/* { dg-final { scan-assembler-times {vncvt\.x\.x\.w} 46 } } */
+/* { dg-final { scan-assembler-times {vnsrl\.wi} 46 } } */
 /* { dg-final { scan-assembler-not {csrr} } } */
 /* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */
 /* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/trunc-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/trunc-2.c
index 25bb2a246623..93374f44b2bb 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/trunc-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/trunc-2.c
@@ -37,7 +37,7 @@  DEF_CONVERT (trunc, uint64_t, uint16_t, 128)
 DEF_CONVERT (trunc, uint64_t, uint16_t, 256)
 DEF_CONVERT (trunc, uint64_t, uint16_t, 512)
 
-/* { dg-final { scan-assembler-times {vncvt\.x\.x\.w} 60 } } */
+/* { dg-final { scan-assembler-times {vnsrl\.wi} 60 } } */
 /* { dg-final { scan-assembler-not {csrr} } } */
 /* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */
 /* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/trunc-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/trunc-3.c
index 1993c63ae2da..29770367aad6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/trunc-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/trunc-3.c
@@ -19,7 +19,7 @@  DEF_CONVERT (trunc, uint64_t, uint8_t, 128)
 DEF_CONVERT (trunc, uint64_t, uint8_t, 256)
 DEF_CONVERT (trunc, uint64_t, uint8_t, 512)
 
-/* { dg-final { scan-assembler-times {vncvt\.x\.x\.w} 42 } } */
+/* { dg-final { scan-assembler-times {vnsrl\.wi} 42 } } */
 /* { dg-final { scan-assembler-not {csrr} } } */
 /* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */
 /* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/simplify-vdiv.c b/gcc/testsuite/gcc.target/riscv/rvv/base/simplify-vdiv.c
index b9fcfe704514..3c7b89a42516 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/simplify-vdiv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/simplify-vdiv.c
@@ -15,4 +15,4 @@ 
 VDIV_WITH_LMUL (1, 16)
 VDIV_WITH_LMUL (1, 32)
 
-/* { dg-final { scan-assembler-times {vneg\.v} 2 } } */
+/* { dg-final { scan-assembler-times {vrsub\.vi} 2 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/unop_v_constraint-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/unop_v_constraint-1.c
index 64f4407d0b6e..3db832b744bf 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/unop_v_constraint-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/unop_v_constraint-1.c
@@ -8,8 +8,8 @@ 
 **  ...
 **	vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **	vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
-**	vneg\.v\tv[0-9]+,\s*v[0-9]+
-**	vneg\.v\tv[0-9]+,\s*v[0-9]+
+**	vrsub\.vi\tv[0-9]+,\s*v[0-9]+,\s*0
+**	vrsub\.vi\tv[0-9]+,\s*v[0-9]+,\s*0
 **	vse32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **	ret
 */
@@ -28,8 +28,8 @@  void f1 (void * in, void *out)
 **	vlm.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
 **	vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
-**	vneg\.v\tv[0-9]+,\s*v[0-9]+
-**	vneg\.v\tv[1-9][0-9]?,\s*v[0-9]+,\s*v0.t
+**	vrsub\.vi\tv[0-9]+,\s*v[0-9]+,\s*0
+**	vrsub\.vi\tv[0-9]+,\s*v[0-9]+,\s*0,\s*v0.t
 **	vse32.v\tv[0-9]+,0\([a-x0-9]+\)
 **	ret
 */
@@ -51,8 +51,8 @@  void f2 (void * in, void *out)
 **  ...
 **	vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **	vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
-**	vneg\.v\tv[0-9]+,\s*v[0-9]+
-**	vneg\.v\tv[1-9][0-9]?,\s*v[0-9]+,\s*v0.t
+**	vrsub\.vi\tv[0-9]+,\s*v[0-9]+,\s*0
+**	vrsub\.vi\tv[0-9]+,\s*v[0-9]+,\s*0,\s*v0.t
 **	vse32.v\tv[0-9]+,0\([a-x0-9]+\)
 **	ret
 */
@@ -72,8 +72,8 @@  void f3 (void * in, void *out)
 **  ...
 **	vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **	vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
-**	vneg\.v\tv[0-9]+,\s*v[0-9]+
-**	vneg\.v\tv[0-9]+,\s*v[0-9]+
+**	vrsub\.vi\tv[0-9]+,\s*v[0-9]+,\s*0
+**	vrsub\.vi\tv[0-9]+,\s*v[0-9]+,\s*0
 **	vse8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **	ret
 */
@@ -92,8 +92,8 @@  void f4 (void * in, void *out)
 **	vlm.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
 **	vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
-**	vneg\.v\tv[0-9]+,\s*v[0-9]+
-**	vneg\.v\tv[1-9][0-9]?,\s*v[0-9]+,\s*v0.t
+**	vrsub\.vi\tv[0-9]+,\s*v[0-9]+,\s*0
+**	vrsub\.vi\tv[0-9]+,\s*v[0-9]+,\s*0,\s*v0.t
 **	vse8.v\tv[0-9]+,0\([a-x0-9]+\)
 **	ret
 */
@@ -115,8 +115,8 @@  void f5 (void * in, void *out)
 **  ...
 **	vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **	vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
-**	vneg\.v\tv[0-9]+,\s*v[0-9]+
-**	vneg\.v\tv[1-9][0-9]?,\s*v[0-9]+,\s*v0.t
+**	vrsub\.vi\tv[0-9]+,\s*v[0-9]+,\s*0
+**	vrsub\.vi\tv[0-9]+,\s*v[0-9]+,\s*0,\s*v0.t
 **	vse8.v\tv[0-9]+,0\([a-x0-9]+\)
 **	ret
 */