[01/07] RISC-V: Add auto-vectorization support
Commit Message
This patch adds foundational support in the form of:
1. New predicates
2. New function prototypes
3. Exporting emit_vlmax_vsetvl to global scope
4. Add a new command line option -mriscv_vector_lmul
gcc/ChangeLog:
* config/riscv/riscv-protos.h (riscv_classify_vlmul_field):
New external declaration.
(riscv_vector_preferred_simd_mode): Ditto.
(riscv_tuple_mode_p): Ditto.
(riscv_vector_mask_mode_p): Ditto.
(riscv_classify_nf): Ditto.
(riscv_vlmul_regsize): Ditto.
(riscv_vector_preferred_simd_mode): Ditto.
(riscv_vector_get_mask_mode): Ditto.
(emit_vlmax_vsetvl): Ditto.
(get_mask_policy_no_pred): Ditto.
(get_tail_policy_no_pred): Ditto.
* config/riscv/riscv-opts.h (riscv_vector_bits_enum): New enum.
(riscv_vector_lmul_enum): Ditto.
(vlmul_field_enum): Ditto.
* config/riscv/riscv-v.cc (emit_vlmax_vsetvl):
Remove static scope.
* config/riscv/riscv.opt (riscv_vector_lmul):
New option -mriscv_vector_lmul.
* config/riscv/predicates.md (p_reg_or_const_csr_operand):
New predicate.
(vector_reg_or_const_dup_operand): Ditto.
---
gcc/config/riscv/predicates.md | 13 +++++++++++
gcc/config/riscv/riscv-opts.h | 40 +++++++++++++++++++++++++++++++++
gcc/config/riscv/riscv-protos.h | 16 +++++++++++++
gcc/config/riscv/riscv-v.cc | 2 +-
gcc/config/riscv/riscv.opt | 20 +++++++++++++++++
5 files changed, 90 insertions(+), 1 deletion(-)
Use hardware floating-point divide and square root instructions.
Comments
Please don't use the same title for all the patches. This will puzzle
people running "git log" once they are committed.
And when you send 01-07, use "reply" instead of "new" so they will show
up in the correct location in a mail client. Or use git send-email
which is much eaiser to use.
On Thu, 2023-03-02 at 23:52 -0500, Michael Collison wrote:
> This patch adds foundational support in the form of:
>
> 1. New predicates
>
> 2. New function prototypes
>
> 3. Exporting emit_vlmax_vsetvl to global scope
>
> 4. Add a new command line option -mriscv_vector_lmul
>
> gcc/ChangeLog:
>
> * config/riscv/riscv-protos.h (riscv_classify_vlmul_field):
The change log entries should be indented with one tab, not some
whitespaces.
Hi Michael Collison:
It's REALLY NOT OK that you didn't mention RiVAI and Ju-Zhe in either
changelog or add he as co-author,
apparently you HAVE references and even copy his code from
https://github.com/riscv-collab/riscv-gcc/tree/riscv-gcc-rvv-next
@@ -264,6 +264,14 @@
})
;; Predicates for the V extension.
+(define_special_predicate "p_reg_or_const_csr_operand"
+ (match_code "reg, subreg, const_int")
+{
+ if (CONST_INT_P (op))
+ return satisfies_constraint_K (op);
+ return GET_MODE (op) == Pmode;
+})
+
(define_special_predicate "vector_length_operand"
(ior (match_operand 0 "pmode_register_operand")
(match_operand 0 "const_csr_operand")))
@@ -287,6 +295,11 @@
(ior (match_operand 0 "register_operand")
(match_test "op == CONSTM1_RTX (GET_MODE (op))")))
+(define_predicate "vector_reg_or_const_dup_operand"
+ (ior (match_operand 0 "register_operand")
+ (match_test "const_vec_duplicate_p (op)
+ && !CONST_POLY_INT_P (CONST_VECTOR_ELT (op, 0))")))
+
(define_predicate "vector_mask_operand"
(ior (match_operand 0 "register_operand")
(match_operand 0 "vector_all_trues_mask_operand")))
@@ -67,6 +67,46 @@ enum stack_protector_guard {
SSP_GLOBAL /* global canary */
};
+/* RVV vector register sizes. */
+enum riscv_vector_bits_enum
+{
+ RVV_SCALABLE,
+ RVV_NOT_IMPLEMENTED = RVV_SCALABLE,
+ RVV_64 = 64,
+ RVV_128 = 128,
+ RVV_256 = 256,
+ RVV_512 = 512,
+ RVV_1024 = 1024,
+ RVV_2048 = 2048,
+ RVV_4096 = 4096,
+ RVV_8192 = 8192,
+ RVV_16384 = 16384,
+ RVV_32768 = 32768,
+ RVV_65536 = 65536
+};
+
+/* vectorization factor. */
+enum riscv_vector_lmul_enum
+{
+ RVV_LMUL1 = 1,
+ RVV_LMUL2 = 2,
+ RVV_LMUL4 = 4,
+ RVV_LMUL8 = 8
+};
+
+enum vlmul_field_enum
+{
+ VLMUL_FIELD_000, /* LMUL = 1 */
+ VLMUL_FIELD_001, /* LMUL = 2 */
+ VLMUL_FIELD_010, /* LMUL = 4 */
+ VLMUL_FIELD_011, /* LMUL = 8 */
+ VLMUL_FIELD_100, /* RESERVED */
+ VLMUL_FIELD_101, /* LMUL = 1/8 */
+ VLMUL_FIELD_110, /* LMUL = 1/4 */
+ VLMUL_FIELD_111, /* LMUL = 1/2 */
+ MAX_VLMUL_FIELD
+};
+
#define MASK_ZICSR (1 << 0)
#define MASK_ZIFENCEI (1 << 1)
b/gcc/config/riscv/riscv-protos.h
@@ -200,4 +200,19 @@ const unsigned int RISCV_BUILTIN_SHIFT = 1;
/* Mask that selects the riscv_builtin_class part of a function code. */
const unsigned int RISCV_BUILTIN_CLASS = (1 << RISCV_BUILTIN_SHIFT) - 1;
+/* Routines implemented in riscv-v.cc*/
+
+namespace riscv_vector {
+extern unsigned int riscv_classify_vlmul_field (enum machine_mode m);
+extern machine_mode riscv_vector_preferred_simd_mode (scalar_mode mode,
unsigned vf);
+extern bool riscv_tuple_mode_p (machine_mode);
+extern bool riscv_vector_mask_mode_p (machine_mode);
+extern int riscv_classify_nf (machine_mode);
+extern int riscv_vlmul_regsize(machine_mode);
+extern machine_mode riscv_vector_preferred_simd_mode (scalar_mode mode,
unsigned vf);
+extern opt_machine_mode riscv_vector_get_mask_mode (machine_mode mode);
+extern rtx emit_vlmax_vsetvl (machine_mode vmode);
+extern rtx get_mask_policy_no_pred ();
+extern rtx get_tail_policy_no_pred ();
+}
#endif /* ! GCC_RISCV_PROTOS_H */
@@ -108,7 +108,7 @@ const_vec_all_same_in_range_p (rtx x, HOST_WIDE_INT
minval,
&& IN_RANGE (INTVAL (elt), minval, maxval));
}
-static rtx
+rtx
emit_vlmax_vsetvl (machine_mode vmode)
{
rtx vl = gen_reg_rtx (Pmode);
@@ -70,6 +70,26 @@ Enum(abi_type) String(lp64f) Value(ABI_LP64F)
EnumValue
Enum(abi_type) String(lp64d) Value(ABI_LP64D)
+Enum
+Name(riscv_vector_lmul) Type(enum riscv_vector_lmul_enum)
+The possible vectorization factor:
+
+EnumValue
+Enum(riscv_vector_lmul) String(1) Value(RVV_LMUL1)
+
+EnumValue
+Enum(riscv_vector_lmul) String(2) Value(RVV_LMUL2)
+
+EnumValue
+Enum(riscv_vector_lmul) String(4) Value(RVV_LMUL4)
+
+EnumValue
+Enum(riscv_vector_lmul) String(8) Value(RVV_LMUL8)
+
+mriscv-vector-lmul=
+Target RejectNegative Joined Enum(riscv_vector_lmul)
Var(riscv_vector_lmul) Init(RVV_LMUL1)
+-mriscv-vector-lmul=<lmul> Set the vf using lmul in auto-vectorization.
+
mfdiv
Target Mask(FDIV)