From patchwork Fri Mar 3 04:52:42 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Michael Collison X-Patchwork-Id: 65949 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 107C03850874 for ; Fri, 3 Mar 2023 04:53:01 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-qt1-x833.google.com (mail-qt1-x833.google.com [IPv6:2607:f8b0:4864:20::833]) by sourceware.org (Postfix) with ESMTPS id 43BF93858CDB for ; Fri, 3 Mar 2023 04:52:44 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 43BF93858CDB Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivosinc.com Received: by mail-qt1-x833.google.com with SMTP id h19so1722626qtk.7 for ; Thu, 02 Mar 2023 20:52:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:content-language:to:subject:from :user-agent:mime-version:date:message-id:from:to:cc:subject:date :message-id:reply-to; bh=eknxH/T0RuOkYWLSr2kWkCtooA5JrT2JlcaWRYvHlmM=; b=lW5pThQsGROCrDkbt5azrlWGNAD4bh+9KbS/sBsjjA5aKRJRS8kInYGo+57GMKtb0a d/fPfqFC3NMhJGw7vMvCAU7m8Ip8GLfTqKRP6Jxs7czJlUQvn75GQ/Bp1tMn7vDVwijw rU+rj7CT8Q6Lz17f2uU94gzhpKk1NRSpmQ3YlcGufVmSK4utt3RAbeF1g2OKQjsM1xkL tAagMv/G9EXTxm+D913tRqQg6H2WckBWFw/TqSkYoh0HRByJumle+Cz/GhPuS+aCsye1 DB4RGt1Mn4fI/80509w2B6dRTyjsJZ3l0JtXPQidkMNldGJyBalg4QrDEHYZygNbpdLG ++AA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:content-language:to:subject:from :user-agent:mime-version:date:message-id:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=eknxH/T0RuOkYWLSr2kWkCtooA5JrT2JlcaWRYvHlmM=; b=oYFgseOg2TV0+Wc/Kd/ZdJIqXhw4sueaIdAmn2xrAOnjGYwpqq3sn2pX/8LFzTnRkb imlx09iLFfteeg9iQ+rpjatxN9F2lv3nIqP73VMi1p4o1DO4gTJNWj9SIR4wWgOo7ujY Z+7AtwLMJnDdxhdVYl23LwZ1M4dbv5AC2zeNyZ3+9HGt+zUjT2U2krGJWItUavjrxsDf ZkcdSoo5HtG3jTIt/yV9EYnFH5deGY1y3tpj1CiWtoGrLCcFBYChU+4byvO6xpYlkyYZ PFb/cGtAPjQKAN4S9uTjgEItiYCdNnd0J0wTnBgIWhrRCbfb2sgDVuSppvUWP4a+Msgb F8jA== X-Gm-Message-State: AO0yUKXb2Tebuldz7QFmu3Acwgpzxk5reJ8LZDVZpkFKQ/n0j20Fib/U lOhe6NgHhPb1/Z5wF6Uiw6AEYluGEWzBBIZ0 X-Google-Smtp-Source: AK7set9qIfJssHHziP8yY8vkSqFnDGIS+wsDuo9+QnZJ/ZODfPEwnYGA7SuGto8Rqbv7kNSubgQ4CQ== X-Received: by 2002:a05:622a:1a01:b0:3b9:bc8c:c1f6 with SMTP id f1-20020a05622a1a0100b003b9bc8cc1f6mr7649399qtb.1.1677819163403; Thu, 02 Mar 2023 20:52:43 -0800 (PST) Received: from [192.168.86.117] ([136.57.172.92]) by smtp.gmail.com with ESMTPSA id l19-20020a05620a211300b007423c122457sm1009039qkl.63.2023.03.02.20.52.43 for (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 02 Mar 2023 20:52:43 -0800 (PST) Message-ID: Date: Thu, 2 Mar 2023 23:52:42 -0500 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.7.1 From: Michael Collison Subject: [PATCH 01/07] RISC-V: Add auto-vectorization support To: gcc-patches Content-Language: en-US X-Spam-Status: No, score=-10.5 required=5.0 tests=BAYES_00, BODY_8BITS, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" This patch adds foundational support in the form of: 1. New predicates 2. New function prototypes 3. Exporting emit_vlmax_vsetvl to global scope 4. Add a new command line option -mriscv_vector_lmul gcc/ChangeLog:     * config/riscv/riscv-protos.h (riscv_classify_vlmul_field):     New external declaration.     (riscv_vector_preferred_simd_mode): Ditto.     (riscv_tuple_mode_p): Ditto.     (riscv_vector_mask_mode_p): Ditto.     (riscv_classify_nf): Ditto.     (riscv_vlmul_regsize): Ditto.     (riscv_vector_preferred_simd_mode): Ditto.     (riscv_vector_get_mask_mode): Ditto.     (emit_vlmax_vsetvl): Ditto.     (get_mask_policy_no_pred): Ditto.     (get_tail_policy_no_pred): Ditto.     * config/riscv/riscv-opts.h (riscv_vector_bits_enum): New enum.     (riscv_vector_lmul_enum): Ditto.     (vlmul_field_enum): Ditto.     * config/riscv/riscv-v.cc (emit_vlmax_vsetvl):     Remove static scope.     * config/riscv/riscv.opt (riscv_vector_lmul):     New option -mriscv_vector_lmul.     * config/riscv/predicates.md (p_reg_or_const_csr_operand):     New predicate.     (vector_reg_or_const_dup_operand): Ditto. ---  gcc/config/riscv/predicates.md  | 13 +++++++++++  gcc/config/riscv/riscv-opts.h   | 40 +++++++++++++++++++++++++++++++++  gcc/config/riscv/riscv-protos.h | 16 +++++++++++++  gcc/config/riscv/riscv-v.cc     |  2 +-  gcc/config/riscv/riscv.opt      | 20 +++++++++++++++++  5 files changed, 90 insertions(+), 1 deletion(-)  Use hardware floating-point divide and square root instructions. diff --git a/gcc/config/riscv/predicates.md b/gcc/config/riscv/predicates.md index 7bc7c0b4f4d..31517ae4606 100644 --- a/gcc/config/riscv/predicates.md +++ b/gcc/config/riscv/predicates.md @@ -264,6 +264,14 @@  })  ;; Predicates for the V extension. +(define_special_predicate "p_reg_or_const_csr_operand" +  (match_code "reg, subreg, const_int") +{ +  if (CONST_INT_P (op)) +    return satisfies_constraint_K (op); +  return GET_MODE (op) == Pmode; +}) +  (define_special_predicate "vector_length_operand"    (ior (match_operand 0 "pmode_register_operand")         (match_operand 0 "const_csr_operand"))) @@ -287,6 +295,11 @@    (ior (match_operand 0 "register_operand")         (match_test "op == CONSTM1_RTX (GET_MODE (op))"))) +(define_predicate "vector_reg_or_const_dup_operand" +  (ior (match_operand 0 "register_operand") +       (match_test "const_vec_duplicate_p (op) +          && !CONST_POLY_INT_P (CONST_VECTOR_ELT (op, 0))"))) +  (define_predicate "vector_mask_operand"    (ior (match_operand 0 "register_operand")         (match_operand 0 "vector_all_trues_mask_operand"))) diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h index ff398c0a2ae..2057a14e153 100644 --- a/gcc/config/riscv/riscv-opts.h +++ b/gcc/config/riscv/riscv-opts.h @@ -67,6 +67,46 @@ enum stack_protector_guard {    SSP_GLOBAL            /* global canary */  }; +/* RVV vector register sizes.  */ +enum riscv_vector_bits_enum +{ +  RVV_SCALABLE, +  RVV_NOT_IMPLEMENTED = RVV_SCALABLE, +  RVV_64 = 64, +  RVV_128 = 128, +  RVV_256 = 256, +  RVV_512 = 512, +  RVV_1024 = 1024, +  RVV_2048 = 2048, +  RVV_4096 = 4096, +  RVV_8192 = 8192, +  RVV_16384 = 16384, +  RVV_32768 = 32768, +  RVV_65536 = 65536 +}; + +/* vectorization factor.  */ +enum riscv_vector_lmul_enum +{ +  RVV_LMUL1 = 1, +  RVV_LMUL2 = 2, +  RVV_LMUL4 = 4, +  RVV_LMUL8 = 8 +}; + +enum vlmul_field_enum +{ +  VLMUL_FIELD_000, /* LMUL = 1 */ +  VLMUL_FIELD_001, /* LMUL = 2 */ +  VLMUL_FIELD_010, /* LMUL = 4 */ +  VLMUL_FIELD_011, /* LMUL = 8 */ +  VLMUL_FIELD_100, /* RESERVED */ +  VLMUL_FIELD_101, /* LMUL = 1/8 */ +  VLMUL_FIELD_110, /* LMUL = 1/4 */ +  VLMUL_FIELD_111, /* LMUL = 1/2 */ +  MAX_VLMUL_FIELD +}; +  #define MASK_ZICSR    (1 << 0)  #define MASK_ZIFENCEI (1 << 1) diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h index 37c634eca1d..70c8dc4ce69 100644 --- a/gcc/config/riscv/riscv-protos.h +++ b/gcc/config/riscv/riscv-protos.h @@ -200,4 +200,19 @@ const unsigned int RISCV_BUILTIN_SHIFT = 1;  /* Mask that selects the riscv_builtin_class part of a function code.  */  const unsigned int RISCV_BUILTIN_CLASS = (1 << RISCV_BUILTIN_SHIFT) - 1; +/* Routines implemented in riscv-v.cc*/ + +namespace riscv_vector { +extern unsigned int riscv_classify_vlmul_field (enum machine_mode m); +extern machine_mode riscv_vector_preferred_simd_mode (scalar_mode mode, unsigned vf); +extern bool riscv_tuple_mode_p (machine_mode); +extern bool riscv_vector_mask_mode_p (machine_mode); +extern int riscv_classify_nf (machine_mode); +extern int riscv_vlmul_regsize(machine_mode); +extern machine_mode riscv_vector_preferred_simd_mode (scalar_mode mode, unsigned vf); +extern opt_machine_mode riscv_vector_get_mask_mode (machine_mode mode); +extern rtx emit_vlmax_vsetvl (machine_mode vmode); +extern rtx get_mask_policy_no_pred (); +extern rtx get_tail_policy_no_pred (); +}  #endif /* ! GCC_RISCV_PROTOS_H */ diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc index 59c25c65cd5..58007cc16eb 100644 --- a/gcc/config/riscv/riscv-v.cc +++ b/gcc/config/riscv/riscv-v.cc @@ -108,7 +108,7 @@ const_vec_all_same_in_range_p (rtx x, HOST_WIDE_INT minval,        && IN_RANGE (INTVAL (elt), minval, maxval));  } -static rtx +rtx  emit_vlmax_vsetvl (machine_mode vmode)  {    rtx vl = gen_reg_rtx (Pmode); diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt index 95535235354..27005fb0f4a 100644 --- a/gcc/config/riscv/riscv.opt +++ b/gcc/config/riscv/riscv.opt @@ -70,6 +70,26 @@ Enum(abi_type) String(lp64f) Value(ABI_LP64F)  EnumValue  Enum(abi_type) String(lp64d) Value(ABI_LP64D) +Enum +Name(riscv_vector_lmul) Type(enum riscv_vector_lmul_enum) +The possible vectorization factor: + +EnumValue +Enum(riscv_vector_lmul) String(1) Value(RVV_LMUL1) + +EnumValue +Enum(riscv_vector_lmul) String(2) Value(RVV_LMUL2) + +EnumValue +Enum(riscv_vector_lmul) String(4) Value(RVV_LMUL4) + +EnumValue +Enum(riscv_vector_lmul) String(8) Value(RVV_LMUL8) + +mriscv-vector-lmul= +Target RejectNegative Joined Enum(riscv_vector_lmul) Var(riscv_vector_lmul) Init(RVV_LMUL1) +-mriscv-vector-lmul=    Set the vf using lmul in auto-vectorization. +  mfdiv  Target Mask(FDIV)