testsuite: Add extra RISC-V options so that -fprefetch-loop-arrays works

  This patch adds the additional options on RISC-V target.
"-fprefetch-loop-arrays" option needs enable prefetch instruction,
for RISC-V that contained in "zicbop" extension.
Use "-march" with "zicbop" will enable this feature.

gcc/testsuite/ChangeLog:

        * gcc.dg/pr106397.c: New dg-additional-options for RISC-V.

---
 gcc/testsuite/gcc.dg/pr106397.c | 2 ++
 1 file changed, 2 insertions(+)
  

On Thu, 28 Jul 2022, jiawei wrote:

> This patch adds the additional options on RISC-V target.
> "-fprefetch-loop-arrays" option needs enable prefetch instruction,
> for RISC-V that contained in "zicbop" extension.
> Use "-march" with "zicbop" will enable this feature.

OK.

Note -fprefetch-loop-arrays is just required to trigger an ICE,
do you see a diagnostic when prefetching is not supported?  Maybe
simply adding -w is better then.

> gcc/testsuite/ChangeLog:
> 
>         * gcc.dg/pr106397.c: New dg-additional-options for RISC-V.
> 
> ---
>  gcc/testsuite/gcc.dg/pr106397.c | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/gcc/testsuite/gcc.dg/pr106397.c b/gcc/testsuite/gcc.dg/pr106397.c
> index 2bc17f8cf80..19274fa8771 100644
> --- a/gcc/testsuite/gcc.dg/pr106397.c
> +++ b/gcc/testsuite/gcc.dg/pr106397.c
> @@ -1,6 +1,8 @@
>  /* { dg-do compile } */
>  /* { dg-options "-O3 -fprefetch-loop-arrays --param l2-cache-size=0 --param prefetch-latency=3 -fprefetch-loop-arrays" } */
>  /* { dg-additional-options "-march=i686 -msse" { target { { i?86-*-* x86_64-*-* } && ia32 } } } */
> +/* { dg-additional-options "-march=rv64gc_zicbop" { target { riscv64-*-* } } */
> +/* { dg-additional-options "-march=rv32gc_zicbop" { target { riscv32-*-* } } */
>  
>  int
>  bar (void)
>
  

> -----原始邮件-----
&gt; 发件人: "Richard Biener" <rguenther@suse.de>
&gt; 发送时间: 2022-07-28 15:45:27 (星期四)
&gt; 收件人: jiawei <jiawei@iscas.ac.cn>
&gt; 抄送: gcc-patches@gcc.gnu.org, jakub@redhat.com, palmer@rivosinc.com, kito.cheng@gmail.com, jim.wilson.gcc@gmail.com, wuwei2016@iscas.ac.cn
&gt; 主题: Re: [PATCH] testsuite: Add extra RISC-V options so that -fprefetch-loop-arrays works
&gt; 
&gt; On Thu, 28 Jul 2022, jiawei wrote:
&gt; 
&gt; &gt; This patch adds the additional options on RISC-V target.
&gt; &gt; "-fprefetch-loop-arrays" option needs enable prefetch instruction,
&gt; &gt; for RISC-V that contained in "zicbop" extension.
&gt; &gt; Use "-march" with "zicbop" will enable this feature.
&gt; 
&gt; OK.
&gt; 
&gt; Note -fprefetch-loop-arrays is just required to trigger an ICE,
&gt; do you see a diagnostic when prefetching is not supported?  Maybe
&gt; simply adding -w is better then.

Yes, without -march support it report warning info:
============================================================================================
cc1: warning: '-fprefetch-loop-arrays' not supported for this target (try '-march' switches)
============================================================================================
after add -w the warning ignored.

&gt; 
&gt; &gt; gcc/testsuite/ChangeLog:
&gt; &gt; 
&gt; &gt;         * gcc.dg/pr106397.c: New dg-additional-options for RISC-V.
&gt; &gt; 
&gt; &gt; ---
&gt; &gt;  gcc/testsuite/gcc.dg/pr106397.c | 2 ++
&gt; &gt;  1 file changed, 2 insertions(+)
&gt; &gt; 
&gt; &gt; diff --git a/gcc/testsuite/gcc.dg/pr106397.c b/gcc/testsuite/gcc.dg/pr106397.c
&gt; &gt; index 2bc17f8cf80..19274fa8771 100644
&gt; &gt; --- a/gcc/testsuite/gcc.dg/pr106397.c
&gt; &gt; +++ b/gcc/testsuite/gcc.dg/pr106397.c
&gt; &gt; @@ -1,6 +1,8 @@
&gt; &gt;  /* { dg-do compile } */
&gt; &gt;  /* { dg-options "-O3 -fprefetch-loop-arrays --param l2-cache-size=0 --param prefetch-latency=3 -fprefetch-loop-arrays" } */
&gt; &gt;  /* { dg-additional-options "-march=i686 -msse" { target { { i?86-*-* x86_64-*-* } &amp;&amp; ia32 } } } */
&gt; &gt; +/* { dg-additional-options "-march=rv64gc_zicbop" { target { riscv64-*-* } } */
&gt; &gt; +/* { dg-additional-options "-march=rv32gc_zicbop" { target { riscv32-*-* } } */
&gt; &gt;  
&gt; &gt;  int
&gt; &gt;  bar (void)
&gt; &gt; 
&gt; 
&gt; -- 
&gt; Richard Biener <rguenther@suse.de>
&gt; SUSE Software Solutions Germany GmbH, Frankenstrasse 146, 90461 Nuernberg,
&gt; Germany; GF: Ivo Totev, Andrew Myers, Andrew McDonald, Boudien Moerman;
&gt; HRB 36809 (AG Nuernberg)
</rguenther@suse.de></jiawei@iscas.ac.cn></rguenther@suse.de>