From patchwork Thu Jul 28 03:25:44 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiawei X-Patchwork-Id: 56379 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 906C2385AE62 for ; Thu, 28 Jul 2022 03:26:22 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from cstnet.cn (smtp84.cstnet.cn [159.226.251.84]) by sourceware.org (Postfix) with ESMTP id 89CC6385829F for ; Thu, 28 Jul 2022 03:26:04 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 89CC6385829F Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=iscas.ac.cn Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=iscas.ac.cn Received: from localhost.localdomain (unknown [47.113.87.88]) by APP-05 (Coremail) with SMTP id zQCowAA3WX7FAeJita2MEw--.57295S2; Thu, 28 Jul 2022 11:25:58 +0800 (CST) From: jiawei To: gcc-patches@gcc.gnu.org Subject: [PATCH] testsuite: Add extra RISC-V options so that -fprefetch-loop-arrays works Date: Thu, 28 Jul 2022 11:25:44 +0800 Message-Id: <20220728032544.2571608-1-jiawei@iscas.ac.cn> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-CM-TRANSID: zQCowAA3WX7FAeJita2MEw--.57295S2 X-Coremail-Antispam: 1UD129KBjvdXoWrKryDAr18uFWDKr4furW8tFb_yoWkJrXEqa 13Gw4kGr4UAw48tFnY9r4rtrZYkw4kurySgay2k3ZFvFyDXFZ0yw4kuFnrAryj9FW0qFWa qr1Svryayr9rKjkaLaAFLSUrUUUUUb8apTn2vfkv8UJUUUU8Yxn0WfASr-VFAUDa7-sFnT 9fnUUIcSsGvfJTRUUUbc8FF20E14v26r4j6ryUM7CY07I20VC2zVCF04k26cxKx2IYs7xG 6rWj6s0DM7CIcVAFz4kK6r1j6r18M28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48ve4kI8w A2z4x0Y4vE2Ix0cI8IcVAFwI0_Xr0_Ar1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI0_Gr0_ Cr1l84ACjcxK6I8E87Iv67AKxVW8Jr0_Cr1UM28EF7xvwVC2z280aVCY1x0267AKxVW8Jr 0_Cr1UM2AIxVAIcxkEcVAq07x20xvEncxIr21l5I8CrVACY4xI64kE6c02F40Ex7xfMcIj 6xIIjxv20xvE14v26r1j6r18McIj6I8E87Iv67AKxVWUJVW8JwAm72CE4IkC6x0Yz7v_Jr 0_Gr1lF7xvr2IYc2Ij64vIr41lF7I21c0EjII2zVCS5cI20VAGYxC7MxkIecxEwVAFjwCF 04k20xvY0x0EwIxGrwCFx2IqxVCFs4IE7xkEbVWUJVW8JwC20s026c02F40E14v26r1j6r 18MI8I3I0E7480Y4vE14v26r106r1rMI8E67AF67kF1VAFwI0_Jw0_GFylIxkGc2Ij64vI r41lIxAIcVC0I7IYx2IY67AKxVWUJVWUCwCI42IY6xIIjxv20xvEc7CjxVAFwI0_Jr0_Gr 1lIxAIcVCF04k26cxKx2IYs7xG6rW3Jr0E3s1lIxAIcVC2z280aVAFwI0_Jr0_Gr1lIxAI cVC2z280aVCY1x0267AKxVWUJVW8JbIYCTnIWIevJa73UjIFyTuYvjfUj18BUUUUU X-Originating-IP: [47.113.87.88] X-CM-SenderInfo: 5mld4v3l6l2u1dvotugofq/1tbiCQsBAGKY1puEWAAAso X-Spam-Status: No, score=-11.9 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jakub@redhat.com, rguenther@suse.de, kito.cheng@gmail.com, jiawei , wuwei2016@iscas.ac.cn Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" This patch adds the additional options on RISC-V target. "-fprefetch-loop-arrays" option needs enable prefetch instruction, for RISC-V that contained in "zicbop" extension. Use "-march" with "zicbop" will enable this feature. gcc/testsuite/ChangeLog: * gcc.dg/pr106397.c: New dg-additional-options for RISC-V. --- gcc/testsuite/gcc.dg/pr106397.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/gcc/testsuite/gcc.dg/pr106397.c b/gcc/testsuite/gcc.dg/pr106397.c index 2bc17f8cf80..19274fa8771 100644 --- a/gcc/testsuite/gcc.dg/pr106397.c +++ b/gcc/testsuite/gcc.dg/pr106397.c @@ -1,6 +1,8 @@ /* { dg-do compile } */ /* { dg-options "-O3 -fprefetch-loop-arrays --param l2-cache-size=0 --param prefetch-latency=3 -fprefetch-loop-arrays" } */ /* { dg-additional-options "-march=i686 -msse" { target { { i?86-*-* x86_64-*-* } && ia32 } } } */ +/* { dg-additional-options "-march=rv64gc_zicbop" { target { riscv64-*-* } } */ +/* { dg-additional-options "-march=rv32gc_zicbop" { target { riscv32-*-* } } */ int bar (void)