Message ID | 20220524225156.4026293-1-philipp.tomsich@vrull.eu |
---|---|
State | Deferred, archived |
Headers |
Return-Path: <gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org> X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id A7E45383D80F for <patchwork@sourceware.org>; Tue, 24 May 2022 22:52:24 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-lf1-x12e.google.com (mail-lf1-x12e.google.com [IPv6:2a00:1450:4864:20::12e]) by sourceware.org (Postfix) with ESMTPS id CD9033857BAC for <gcc-patches@gcc.gnu.org>; Tue, 24 May 2022 22:52:07 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org CD9033857BAC Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=vrull.eu Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=vrull.eu Received: by mail-lf1-x12e.google.com with SMTP id c19so20154737lfv.5 for <gcc-patches@gcc.gnu.org>; Tue, 24 May 2022 15:52:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vrull.eu; s=google; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=VpIuUJygMx9V5512QntYxGNS9y2oi2a3cUg/bO23TV8=; b=Q0Bc1KVOyHuM8W6ABeqDas+oQRQTTHVxPvvkURW7Un2LZU5wGmvBbl5v58S/wxdhZ6 I55erGODPHAeFobUC99pEZakqT/EZYpH6jCchuMy2agSkwbb/nXsK34gCuciBRJTFjJK l0tf3Q2vli3Dn5tYkYk+Rq5T2Mzfgj2EGmUuJMSi4IvAuJB/farsBMUqNVVONH/yqiLH NY7kX4CN6zg3B2WCrxLFH+P36oXTURoydat5FHXxMRu5vggYS6sgIXpPBQEc/ALUfGG9 5Pw6X5r6/R6lUI2J4WSbJnl9krE3RnM3/u/3gqGwVd3AKI0epxc9gsYyCq/ldBXo8k+2 jNlQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=VpIuUJygMx9V5512QntYxGNS9y2oi2a3cUg/bO23TV8=; b=wrmwkz2qteduXI4V9tsOst5oncDoBg3amDn1Nr9WxMMLL0iJXs/x5Zmy7P+CJ/l7vp bJP0dN/seCakVU4BHhe/dONioRXnEPd1+ghJEBZY/7WUptEjnPRYQc79mf7vz1BHRfOR ierv4/xm7k6f6DPxHdv2B37AR4QtK6cMEjbouKIVrWDJTo/FMQoUcpydsI1+C1BDYv06 ++tFwAchyZb5VSmkKzg6tm9JZ3VfetwJIKvG/xmsiieshHZs3Fft5hsPeAmYGhlEXS3l kh7HzxwD/wEp1Kmmr6vqw16t4iT+tR/P1eVPXEAxS3D/KH0RP4u1CvSpFrpYbplxPQz+ X2Xg== X-Gm-Message-State: AOAM532p8VF5zFUBpEPxJvY58M7brJ85qLPOss/z4UXTOqpDLuF0w2vQ vgojnbFLEm95WKG1X0UPsezPULBydUJcvkn/ X-Google-Smtp-Source: ABdhPJzsoiubl+S02ML8o0PC+o/SSwQ8DYU3nUIbRTVaWdyfKVogiEX1jfQHCya0Q1ewLhyDsvurmg== X-Received: by 2002:a19:5043:0:b0:477:cc18:840a with SMTP id z3-20020a195043000000b00477cc18840amr19390479lfj.437.1653432725852; Tue, 24 May 2022 15:52:05 -0700 (PDT) Received: from ubuntu-focal.. ([2a01:4f9:3a:1e26::2]) by smtp.gmail.com with ESMTPSA id k8-20020a2ea288000000b0024f3d1dae84sm2750660lja.12.2022.05.24.15.52.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 24 May 2022 15:52:05 -0700 (PDT) From: Philipp Tomsich <philipp.tomsich@vrull.eu> To: gcc-patches@gcc.gnu.org Subject: [PATCH v1 1/3] RISC-V: Split "(a & (1 << BIT_NO)) ? 0 : -1" to bexti + addi Date: Wed, 25 May 2022 00:51:54 +0200 Message-Id: <20220524225156.4026293-1-philipp.tomsich@vrull.eu> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-11.6 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, JMQ_SPF_NEUTRAL, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list <gcc-patches.gcc.gnu.org> List-Unsubscribe: <https://gcc.gnu.org/mailman/options/gcc-patches>, <mailto:gcc-patches-request@gcc.gnu.org?subject=unsubscribe> List-Archive: <https://gcc.gnu.org/pipermail/gcc-patches/> List-Post: <mailto:gcc-patches@gcc.gnu.org> List-Help: <mailto:gcc-patches-request@gcc.gnu.org?subject=help> List-Subscribe: <https://gcc.gnu.org/mailman/listinfo/gcc-patches>, <mailto:gcc-patches-request@gcc.gnu.org?subject=subscribe> Cc: Andrew Waterman <andrew@sifive.com>, Vineet Gupta <vineetg@rivosinc.com>, Kito Cheng <kito.cheng@gmail.com>, Philipp Tomsich <philipp.tomsich@vrull.eu>, Christoph Muellner <christoph.muellner@vrull.eu> Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" <gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org> |
Series |
[v1,1/3] RISC-V: Split "(a & (1 << BIT_NO)) ? 0 : -1" to bexti + addi
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Commit Message
Philipp Tomsich
May 24, 2022, 10:51 p.m. UTC
Consider creating a polarity-reversed mask from a set-bit (i.e., if
the bit is set, produce all-ones; otherwise: all-zeros). Using Zbb,
this can be expressed as bexti, followed by an addi of minus-one. To
enable the combiner to discover this opportunity, we need to split the
canonical expression for "(a & (1 << BIT_NO)) ? 0 : -1" into a form
combinable into bexti.
Consider the function:
long f(long a)
{
return (a & (1 << BIT_NO)) ? 0 : -1;
}
This produces the following sequence prior to this change:
andi a0,a0,16
seqz a0,a0
neg a0,a0
ret
Following this change, it results in:
bexti a0,a0,4
addi a0,a0,-1
ret
Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
gcc/ChangeLog:
* config/riscv/bitmanip.md: Add a splitter to generate
polarity-reversed masks from a set bit using bexti + addi.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/zbs-bexti.c: New test.
---
gcc/config/riscv/bitmanip.md | 13 +++++++++++++
gcc/testsuite/gcc.target/riscv/zbs-bexti.c | 14 ++++++++++++++
2 files changed, 27 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/zbs-bexti.c
Comments
Kito, Looks like this series fell by the wayside (possibly, because it didn't have a cover-letter and was easier to miss)? Thanks, Philipp. On Wed, 25 May 2022 at 00:52, Philipp Tomsich <philipp.tomsich@vrull.eu> wrote: > > Consider creating a polarity-reversed mask from a set-bit (i.e., if > the bit is set, produce all-ones; otherwise: all-zeros). Using Zbb, > this can be expressed as bexti, followed by an addi of minus-one. To > enable the combiner to discover this opportunity, we need to split the > canonical expression for "(a & (1 << BIT_NO)) ? 0 : -1" into a form > combinable into bexti. > > Consider the function: > long f(long a) > { > return (a & (1 << BIT_NO)) ? 0 : -1; > } > This produces the following sequence prior to this change: > andi a0,a0,16 > seqz a0,a0 > neg a0,a0 > ret > Following this change, it results in: > bexti a0,a0,4 > addi a0,a0,-1 > ret > > Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu> > > gcc/ChangeLog: > > * config/riscv/bitmanip.md: Add a splitter to generate > polarity-reversed masks from a set bit using bexti + addi. > > gcc/testsuite/ChangeLog: > > * gcc.target/riscv/zbs-bexti.c: New test. > > --- > > gcc/config/riscv/bitmanip.md | 13 +++++++++++++ > gcc/testsuite/gcc.target/riscv/zbs-bexti.c | 14 ++++++++++++++ > 2 files changed, 27 insertions(+) > create mode 100644 gcc/testsuite/gcc.target/riscv/zbs-bexti.c > > diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md > index 0ab9ffe3c0b..ea5dea13cfb 100644 > --- a/gcc/config/riscv/bitmanip.md > +++ b/gcc/config/riscv/bitmanip.md > @@ -340,3 +340,16 @@ (define_insn "*bexti" > "TARGET_ZBS" > "bexti\t%0,%1,%2" > [(set_attr "type" "bitmanip")]) > + > +;; We can create a polarity-reversed mask (i.e. bit N -> { set = 0, clear = -1 }) > +;; using a bext(i) followed by an addi instruction. > +;; This splits the canonical representation of "(a & (1 << BIT_NO)) ? 0 : -1". > +(define_split > + [(set (match_operand:GPR 0 "register_operand") > + (neg:GPR (eq:GPR (zero_extract:GPR (match_operand:GPR 1 "register_operand") > + (const_int 1) > + (match_operand 2)) > + (const_int 0))))] > + "TARGET_ZBS" > + [(set (match_dup 0) (zero_extract:GPR (match_dup 1) (const_int 1) (match_dup 2))) > + (set (match_dup 0) (plus:GPR (match_dup 0) (const_int -1)))]) > diff --git a/gcc/testsuite/gcc.target/riscv/zbs-bexti.c b/gcc/testsuite/gcc.target/riscv/zbs-bexti.c > new file mode 100644 > index 00000000000..99e3b58309c > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/zbs-bexti.c > @@ -0,0 +1,14 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=rv64gc_zbs -mabi=lp64 -O2" } */ > + > +/* bexti */ > +#define BIT_NO 4 > + > +long > +foo0 (long a) > +{ > + return (a & (1 << BIT_NO)) ? 0 : -1; > +} > + > +/* { dg-final { scan-assembler "bexti" } } */ > +/* { dg-final { scan-assembler "addi" } } */ > -- > 2.34.1 >
Hi Philipp: This patch series is LGTM, but plz introduce new pseudo when can_create_pseudo_p like what we discussed in https://gcc.gnu.org/pipermail/gcc-patches/2022-June/596305.html, you can commit with the change with a [committed] patch mail :) On Thu, Jun 16, 2022 at 5:32 PM Philipp Tomsich <philipp.tomsich@vrull.eu> wrote: > > Kito, > > Looks like this series fell by the wayside (possibly, because it > didn't have a cover-letter and was easier to miss)? > > Thanks, > Philipp. > > On Wed, 25 May 2022 at 00:52, Philipp Tomsich <philipp.tomsich@vrull.eu> wrote: > > > > Consider creating a polarity-reversed mask from a set-bit (i.e., if > > the bit is set, produce all-ones; otherwise: all-zeros). Using Zbb, > > this can be expressed as bexti, followed by an addi of minus-one. To > > enable the combiner to discover this opportunity, we need to split the > > canonical expression for "(a & (1 << BIT_NO)) ? 0 : -1" into a form > > combinable into bexti. > > > > Consider the function: > > long f(long a) > > { > > return (a & (1 << BIT_NO)) ? 0 : -1; > > } > > This produces the following sequence prior to this change: > > andi a0,a0,16 > > seqz a0,a0 > > neg a0,a0 > > ret > > Following this change, it results in: > > bexti a0,a0,4 > > addi a0,a0,-1 > > ret > > > > Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu> > > > > gcc/ChangeLog: > > > > * config/riscv/bitmanip.md: Add a splitter to generate > > polarity-reversed masks from a set bit using bexti + addi. > > > > gcc/testsuite/ChangeLog: > > > > * gcc.target/riscv/zbs-bexti.c: New test. > > > > --- > > > > gcc/config/riscv/bitmanip.md | 13 +++++++++++++ > > gcc/testsuite/gcc.target/riscv/zbs-bexti.c | 14 ++++++++++++++ > > 2 files changed, 27 insertions(+) > > create mode 100644 gcc/testsuite/gcc.target/riscv/zbs-bexti.c > > > > diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md > > index 0ab9ffe3c0b..ea5dea13cfb 100644 > > --- a/gcc/config/riscv/bitmanip.md > > +++ b/gcc/config/riscv/bitmanip.md > > @@ -340,3 +340,16 @@ (define_insn "*bexti" > > "TARGET_ZBS" > > "bexti\t%0,%1,%2" > > [(set_attr "type" "bitmanip")]) > > + > > +;; We can create a polarity-reversed mask (i.e. bit N -> { set = 0, clear = -1 }) > > +;; using a bext(i) followed by an addi instruction. > > +;; This splits the canonical representation of "(a & (1 << BIT_NO)) ? 0 : -1". > > +(define_split > > + [(set (match_operand:GPR 0 "register_operand") > > + (neg:GPR (eq:GPR (zero_extract:GPR (match_operand:GPR 1 "register_operand") > > + (const_int 1) > > + (match_operand 2)) > > + (const_int 0))))] > > + "TARGET_ZBS" > > + [(set (match_dup 0) (zero_extract:GPR (match_dup 1) (const_int 1) (match_dup 2))) > > + (set (match_dup 0) (plus:GPR (match_dup 0) (const_int -1)))]) > > diff --git a/gcc/testsuite/gcc.target/riscv/zbs-bexti.c b/gcc/testsuite/gcc.target/riscv/zbs-bexti.c > > new file mode 100644 > > index 00000000000..99e3b58309c > > --- /dev/null > > +++ b/gcc/testsuite/gcc.target/riscv/zbs-bexti.c > > @@ -0,0 +1,14 @@ > > +/* { dg-do compile } */ > > +/* { dg-options "-march=rv64gc_zbs -mabi=lp64 -O2" } */ > > + > > +/* bexti */ > > +#define BIT_NO 4 > > + > > +long > > +foo0 (long a) > > +{ > > + return (a & (1 << BIT_NO)) ? 0 : -1; > > +} > > + > > +/* { dg-final { scan-assembler "bexti" } } */ > > +/* { dg-final { scan-assembler "addi" } } */ > > -- > > 2.34.1 > >
diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md index 0ab9ffe3c0b..ea5dea13cfb 100644 --- a/gcc/config/riscv/bitmanip.md +++ b/gcc/config/riscv/bitmanip.md @@ -340,3 +340,16 @@ (define_insn "*bexti" "TARGET_ZBS" "bexti\t%0,%1,%2" [(set_attr "type" "bitmanip")]) + +;; We can create a polarity-reversed mask (i.e. bit N -> { set = 0, clear = -1 }) +;; using a bext(i) followed by an addi instruction. +;; This splits the canonical representation of "(a & (1 << BIT_NO)) ? 0 : -1". +(define_split + [(set (match_operand:GPR 0 "register_operand") + (neg:GPR (eq:GPR (zero_extract:GPR (match_operand:GPR 1 "register_operand") + (const_int 1) + (match_operand 2)) + (const_int 0))))] + "TARGET_ZBS" + [(set (match_dup 0) (zero_extract:GPR (match_dup 1) (const_int 1) (match_dup 2))) + (set (match_dup 0) (plus:GPR (match_dup 0) (const_int -1)))]) diff --git a/gcc/testsuite/gcc.target/riscv/zbs-bexti.c b/gcc/testsuite/gcc.target/riscv/zbs-bexti.c new file mode 100644 index 00000000000..99e3b58309c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/zbs-bexti.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zbs -mabi=lp64 -O2" } */ + +/* bexti */ +#define BIT_NO 4 + +long +foo0 (long a) +{ + return (a & (1 << BIT_NO)) ? 0 : -1; +} + +/* { dg-final { scan-assembler "bexti" } } */ +/* { dg-final { scan-assembler "addi" } } */