From patchwork Tue May 24 22:51:54 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Philipp Tomsich X-Patchwork-Id: 54360 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id A7E45383D80F for ; Tue, 24 May 2022 22:52:24 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-lf1-x12e.google.com (mail-lf1-x12e.google.com [IPv6:2a00:1450:4864:20::12e]) by sourceware.org (Postfix) with ESMTPS id CD9033857BAC for ; Tue, 24 May 2022 22:52:07 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org CD9033857BAC Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=vrull.eu Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=vrull.eu Received: by mail-lf1-x12e.google.com with SMTP id c19so20154737lfv.5 for ; Tue, 24 May 2022 15:52:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vrull.eu; s=google; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=VpIuUJygMx9V5512QntYxGNS9y2oi2a3cUg/bO23TV8=; b=Q0Bc1KVOyHuM8W6ABeqDas+oQRQTTHVxPvvkURW7Un2LZU5wGmvBbl5v58S/wxdhZ6 I55erGODPHAeFobUC99pEZakqT/EZYpH6jCchuMy2agSkwbb/nXsK34gCuciBRJTFjJK l0tf3Q2vli3Dn5tYkYk+Rq5T2Mzfgj2EGmUuJMSi4IvAuJB/farsBMUqNVVONH/yqiLH NY7kX4CN6zg3B2WCrxLFH+P36oXTURoydat5FHXxMRu5vggYS6sgIXpPBQEc/ALUfGG9 5Pw6X5r6/R6lUI2J4WSbJnl9krE3RnM3/u/3gqGwVd3AKI0epxc9gsYyCq/ldBXo8k+2 jNlQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=VpIuUJygMx9V5512QntYxGNS9y2oi2a3cUg/bO23TV8=; b=wrmwkz2qteduXI4V9tsOst5oncDoBg3amDn1Nr9WxMMLL0iJXs/x5Zmy7P+CJ/l7vp bJP0dN/seCakVU4BHhe/dONioRXnEPd1+ghJEBZY/7WUptEjnPRYQc79mf7vz1BHRfOR ierv4/xm7k6f6DPxHdv2B37AR4QtK6cMEjbouKIVrWDJTo/FMQoUcpydsI1+C1BDYv06 ++tFwAchyZb5VSmkKzg6tm9JZ3VfetwJIKvG/xmsiieshHZs3Fft5hsPeAmYGhlEXS3l kh7HzxwD/wEp1Kmmr6vqw16t4iT+tR/P1eVPXEAxS3D/KH0RP4u1CvSpFrpYbplxPQz+ X2Xg== X-Gm-Message-State: AOAM532p8VF5zFUBpEPxJvY58M7brJ85qLPOss/z4UXTOqpDLuF0w2vQ vgojnbFLEm95WKG1X0UPsezPULBydUJcvkn/ X-Google-Smtp-Source: ABdhPJzsoiubl+S02ML8o0PC+o/SSwQ8DYU3nUIbRTVaWdyfKVogiEX1jfQHCya0Q1ewLhyDsvurmg== X-Received: by 2002:a19:5043:0:b0:477:cc18:840a with SMTP id z3-20020a195043000000b00477cc18840amr19390479lfj.437.1653432725852; Tue, 24 May 2022 15:52:05 -0700 (PDT) Received: from ubuntu-focal.. ([2a01:4f9:3a:1e26::2]) by smtp.gmail.com with ESMTPSA id k8-20020a2ea288000000b0024f3d1dae84sm2750660lja.12.2022.05.24.15.52.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 24 May 2022 15:52:05 -0700 (PDT) From: Philipp Tomsich To: gcc-patches@gcc.gnu.org Subject: [PATCH v1 1/3] RISC-V: Split "(a & (1 << BIT_NO)) ? 0 : -1" to bexti + addi Date: Wed, 25 May 2022 00:51:54 +0200 Message-Id: <20220524225156.4026293-1-philipp.tomsich@vrull.eu> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-Spam-Status: No, score=-11.6 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, JMQ_SPF_NEUTRAL, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Andrew Waterman , Vineet Gupta , Kito Cheng , Philipp Tomsich , Christoph Muellner Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" Consider creating a polarity-reversed mask from a set-bit (i.e., if the bit is set, produce all-ones; otherwise: all-zeros). Using Zbb, this can be expressed as bexti, followed by an addi of minus-one. To enable the combiner to discover this opportunity, we need to split the canonical expression for "(a & (1 << BIT_NO)) ? 0 : -1" into a form combinable into bexti. Consider the function: long f(long a) { return (a & (1 << BIT_NO)) ? 0 : -1; } This produces the following sequence prior to this change: andi a0,a0,16 seqz a0,a0 neg a0,a0 ret Following this change, it results in: bexti a0,a0,4 addi a0,a0,-1 ret Signed-off-by: Philipp Tomsich gcc/ChangeLog: * config/riscv/bitmanip.md: Add a splitter to generate polarity-reversed masks from a set bit using bexti + addi. gcc/testsuite/ChangeLog: * gcc.target/riscv/zbs-bexti.c: New test. --- gcc/config/riscv/bitmanip.md | 13 +++++++++++++ gcc/testsuite/gcc.target/riscv/zbs-bexti.c | 14 ++++++++++++++ 2 files changed, 27 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/zbs-bexti.c diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md index 0ab9ffe3c0b..ea5dea13cfb 100644 --- a/gcc/config/riscv/bitmanip.md +++ b/gcc/config/riscv/bitmanip.md @@ -340,3 +340,16 @@ (define_insn "*bexti" "TARGET_ZBS" "bexti\t%0,%1,%2" [(set_attr "type" "bitmanip")]) + +;; We can create a polarity-reversed mask (i.e. bit N -> { set = 0, clear = -1 }) +;; using a bext(i) followed by an addi instruction. +;; This splits the canonical representation of "(a & (1 << BIT_NO)) ? 0 : -1". +(define_split + [(set (match_operand:GPR 0 "register_operand") + (neg:GPR (eq:GPR (zero_extract:GPR (match_operand:GPR 1 "register_operand") + (const_int 1) + (match_operand 2)) + (const_int 0))))] + "TARGET_ZBS" + [(set (match_dup 0) (zero_extract:GPR (match_dup 1) (const_int 1) (match_dup 2))) + (set (match_dup 0) (plus:GPR (match_dup 0) (const_int -1)))]) diff --git a/gcc/testsuite/gcc.target/riscv/zbs-bexti.c b/gcc/testsuite/gcc.target/riscv/zbs-bexti.c new file mode 100644 index 00000000000..99e3b58309c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/zbs-bexti.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zbs -mabi=lp64 -O2" } */ + +/* bexti */ +#define BIT_NO 4 + +long +foo0 (long a) +{ + return (a & (1 << BIT_NO)) ? 0 : -1; +} + +/* { dg-final { scan-assembler "bexti" } } */ +/* { dg-final { scan-assembler "addi" } } */ From patchwork Tue May 24 22:51:55 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Philipp Tomsich X-Patchwork-Id: 54361 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 576C53839C5F for ; Tue, 24 May 2022 22:52:54 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-lf1-x129.google.com (mail-lf1-x129.google.com [IPv6:2a00:1450:4864:20::129]) by sourceware.org (Postfix) with ESMTPS id A6FE33857BB0 for ; Tue, 24 May 2022 22:52:08 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org A6FE33857BB0 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=vrull.eu Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=vrull.eu Received: by mail-lf1-x129.google.com with SMTP id bq30so33283190lfb.3 for ; Tue, 24 May 2022 15:52:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vrull.eu; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Ptk9W1e3iuE1JBU0MdSXrGr6RhtVAO8B7Y4LWqTdDAc=; b=aNpYmxsXoveSpq6hD7+Fz+sS4sQRq7wMGZ1SUYWRJB3MBhHCpj83ymQXQVxASfli1B KY1D1tviJSB+tz8d8vkckpC9awZhyn0hlcCqTGLE/QhRp0sky52olRuoKcVx9ao0Q8bS PE+/+x0T0BD83X/cqxuBasZHXGj5L/KwrxYVXjokmPakMjg8jze5uLelCANbBvr72fir pZSRBRY8aoLWjtaqAw88rOJT0sq4gkRlllWZY4r+e2rtcb3G069vtJo941O1R/52bycL xzp7xPjVmce5LX9mjZkldtMsnrVH2kqMICRNMpCNHau3H2Wc3+K/rnXU9ZyZJR9xjdL+ m0+g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Ptk9W1e3iuE1JBU0MdSXrGr6RhtVAO8B7Y4LWqTdDAc=; b=5tUqRS3eM/7BcsicyThSKO2NgK5+9M+Z+4tVw43QyLd3r9ZISVs7Qmc9ickpeZH4Q2 Cm3zUt3H1MWXoaGeKSPftCB+0kxna6xkeo40UCFTppzwNcjel249XACG8J3t3bVVghAh PuekiBw2ateK7C0ThTe+Ppa1viRa92c80fVit0KinsNzLmmJExtPIVTo31Gzd4s5B8Ed yLppgf3Xad1S0TafUGLwTE7AmSssBt4TKVXT7tjIbEZITFcwJ4uq7jBjXLe18hIvgKAY phP3zKEAAz4iG6vxu7TXgm5krznZHC3rgo6MeBX8UbuboJzcn//NVlX7nCpkSjrz1Yu7 nRyQ== X-Gm-Message-State: AOAM531v1LICW/aG64nEy0hC9xduo3gSrGgmVtV7NgL5xMbAMcNtWQci yX8nllg0wQbZapjPlWmZxYl6gBVe8g5i3wTG X-Google-Smtp-Source: ABdhPJxT9Z810VEfvWNasuf2Fexfcti2A1DxfH0rNbixZSPzmf2F95/TtqcYOuT5upb0GGhKtXdzYw== X-Received: by 2002:a05:6512:108a:b0:478:68e8:adce with SMTP id j10-20020a056512108a00b0047868e8adcemr10831415lfg.617.1653432727020; Tue, 24 May 2022 15:52:07 -0700 (PDT) Received: from ubuntu-focal.. ([2a01:4f9:3a:1e26::2]) by smtp.gmail.com with ESMTPSA id k8-20020a2ea288000000b0024f3d1dae84sm2750660lja.12.2022.05.24.15.52.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 24 May 2022 15:52:06 -0700 (PDT) From: Philipp Tomsich To: gcc-patches@gcc.gnu.org Subject: [PATCH v1 2/3] RISC-V: Split "(a & (1UL << bitno)) ? 0 : -1" to bext + addi Date: Wed, 25 May 2022 00:51:55 +0200 Message-Id: <20220524225156.4026293-2-philipp.tomsich@vrull.eu> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220524225156.4026293-1-philipp.tomsich@vrull.eu> References: <20220524225156.4026293-1-philipp.tomsich@vrull.eu> MIME-Version: 1.0 X-Spam-Status: No, score=-11.6 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, JMQ_SPF_NEUTRAL, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Andrew Waterman , Vineet Gupta , Kito Cheng , Philipp Tomsich , Christoph Muellner Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" For a straightforward application of bext for the following function long bext64(long a, char bitno) { return (a & (1UL << bitno)) ? 0 : -1; } we generate srl a0,a0,a1 # 7 [c=4 l=4] lshrdi3 andi a0,a0,1 # 8 [c=4 l=4] anddi3/1 addi a0,a0,-1 # 14 [c=4 l=4] adddi3/1 due to the following failed match at combine time: (set (reg:DI 82) (zero_extract:DI (reg:DI 83) (const_int 1 [0x1]) (reg:DI 84))) The existing pattern for bext requires the 3rd argument to zero_extract to be a QImode register wrapped in a zero_extension. This adds an additional pattern that allows an Xmode argument. With this change, the testcase compiles to bext a0,a0,a1 # 8 [c=4 l=4] *bextdi addi a0,a0,-1 # 14 [c=4 l=4] adddi3/1 gcc/ChangeLog: * config/riscv/bitmanip.md (*bext): Add an additional pattern that allows the 3rd argument to zero_extract to be an Xmode register operand. gcc/testsuite/ChangeLog: * gcc.target/riscv/zbs-bext.c: Add testcases. * gcc.target/riscv/zbs-bexti.c: Add testcases. Signed-off-by: Philipp Tomsich Co-developed-by: Manolis Tsamis --- gcc/config/riscv/bitmanip.md | 12 +++++++++++ gcc/testsuite/gcc.target/riscv/zbs-bext.c | 23 +++++++++++++++++++--- gcc/testsuite/gcc.target/riscv/zbs-bexti.c | 23 ++++++++++++++++------ 3 files changed, 49 insertions(+), 9 deletions(-) diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md index ea5dea13cfb..5d7c20e9fdc 100644 --- a/gcc/config/riscv/bitmanip.md +++ b/gcc/config/riscv/bitmanip.md @@ -332,6 +332,18 @@ (define_insn "*bext" "bext\t%0,%1,%2" [(set_attr "type" "bitmanip")]) +;; When performing `(a & (1UL << bitno)) ? 0 : -1` the combiner +;; usually has the `bitno` typed as X-mode (i.e. no further +;; zero-extension is performed around the bitno). +(define_insn "*bext" + [(set (match_operand:X 0 "register_operand" "=r") + (zero_extract:X (match_operand:X 1 "register_operand" "r") + (const_int 1) + (match_operand:X 2 "register_operand" "r")))] + "TARGET_ZBS" + "bext\t%0,%1,%2" + [(set_attr "type" "bitmanip")]) + (define_insn "*bexti" [(set (match_operand:X 0 "register_operand" "=r") (zero_extract:X (match_operand:X 1 "register_operand" "r") diff --git a/gcc/testsuite/gcc.target/riscv/zbs-bext.c b/gcc/testsuite/gcc.target/riscv/zbs-bext.c index 47982396119..8de9c5a167c 100644 --- a/gcc/testsuite/gcc.target/riscv/zbs-bext.c +++ b/gcc/testsuite/gcc.target/riscv/zbs-bext.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* { dg-options "-march=rv64gc_zbs -mabi=lp64" } */ -/* { dg-skip-if "" { *-*-* } { "-O0" } } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" } } */ /* bext */ long @@ -16,6 +16,23 @@ foo1 (long i) return 1L & (i >> 20); } +long bext64_1(long a, char bitno) +{ + return (a & (1UL << bitno)) ? 1 : 0; +} + +long bext64_2(long a, char bitno) +{ + return (a & (1UL << bitno)) ? 0 : -1; +} + +long bext64_3(long a, char bitno) +{ + return (a & (1UL << bitno)) ? -1 : 0; +} + /* { dg-final { scan-assembler-times "bexti\t" 1 } } */ -/* { dg-final { scan-assembler-times "bext\t" 1 } } */ -/* { dg-final { scan-assembler-not "andi" } } */ +/* { dg-final { scan-assembler-times "bext\t" 4 } } */ +/* { dg-final { scan-assembler-times "addi\t" 1 } } */ +/* { dg-final { scan-assembler-times "neg\t" 1 } } */ +/* { dg-final { scan-assembler-not "andi" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/riscv/zbs-bexti.c b/gcc/testsuite/gcc.target/riscv/zbs-bexti.c index 99e3b58309c..8182a61707d 100644 --- a/gcc/testsuite/gcc.target/riscv/zbs-bexti.c +++ b/gcc/testsuite/gcc.target/riscv/zbs-bexti.c @@ -1,14 +1,25 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc_zbs -mabi=lp64 -O2" } */ +/* { dg-options "-march=rv64gc_zbs -mabi=lp64" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" } } */ /* bexti */ #define BIT_NO 4 -long -foo0 (long a) +long bexti64_1(long a, char bitno) { - return (a & (1 << BIT_NO)) ? 0 : -1; + return (a & (1UL << BIT_NO)) ? 1 : 0; } -/* { dg-final { scan-assembler "bexti" } } */ -/* { dg-final { scan-assembler "addi" } } */ +long bexti64_2(long a, char bitno) +{ + return (a & (1UL << BIT_NO)) ? 0 : -1; +} + +long bexti64_3(long a, char bitno) +{ + return (a & (1UL << BIT_NO)) ? -1 : 0; +} + +/* { dg-final { scan-assembler-times "bexti\t" 3 } } */ +/* { dg-final { scan-assembler-times "addi\t" 1 } } */ +/* { dg-final { scan-assembler-times "neg\t" 1 } } */ \ No newline at end of file From patchwork Tue May 24 22:51:56 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Philipp Tomsich X-Patchwork-Id: 54362 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id E349D383D804 for ; Tue, 24 May 2022 22:53:23 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-lf1-x12d.google.com (mail-lf1-x12d.google.com [IPv6:2a00:1450:4864:20::12d]) by sourceware.org (Postfix) with ESMTPS id 2FD153857BAC for ; Tue, 24 May 2022 22:52:10 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 2FD153857BAC Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=vrull.eu Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=vrull.eu Received: by mail-lf1-x12d.google.com with SMTP id bq30so33283253lfb.3 for ; Tue, 24 May 2022 15:52:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vrull.eu; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=N2wRijQKjfdOlJ6HI3Y9oz1u0pOg+cxwSGz4zse0y34=; b=dLfrQ+n9ZYWX6+ozQ5ZKgd9cdjlM+QX4bT7Ba34T4bCQ4D5XZvJsGfNIvdvMBcCxx1 d+8dlxlb1cv4LnpW2zInMA8aEUPWEoJFCFGh8qyD+tL+WY5I+CN7b2deYBGxMjglfnT6 KCq7NnQCTonXj2D90PfFIhWd+RJ6KbNvlO4+wJ3qjFrxrFmJpoafAkHC99IZp0cBDFE2 1cjqREmZV3slcuSqlyPB6Pe1z97T5xLsPytchAqR0+op0PzrTG6LS2e5Fdv84WLOjFUh WnmWVdbXweO0sczh1DV8dUXjFqDsR9qYOAIozZZ6gjePHmIypLTwzCeWT1KU+kxBxb0x +8Sw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=N2wRijQKjfdOlJ6HI3Y9oz1u0pOg+cxwSGz4zse0y34=; b=SVI4crDHrlK4ICb6Efy2/fpqVRtpVIkdbQwrUTvl/JxUowPe0H3zBTfKHlhdSNRKo8 boJYzO1CxuhZXTLKBzfhFAGgGEC6+0c8y2iW0i6Xsln40x0wD1rJISlL9G0LgKW8PPw6 /ZZhnDbvOhyOHewHqQBIBnMm0HnchqIL5UvdHQHJMnvbpwehae5KgNi2oSZ1MvcgVqly iStiv9kw5qjPuifoiXo0QGXqYjHSCEDaSziZpaakgdVEA8mJrVxC3pZQJk1V7UbTDxdD ADcOrFubfjnpkMFr8UBKWK/PPnEMvjbzJUuxsP4iOf85yaA2oH1C3G0cOsoHGkoU9Rt9 J7Zw== X-Gm-Message-State: AOAM533rRBq6M13N4KHld9I3065E2Dmn1S8WYPrwyfSymGRNS7Z7ZTxZ 7Nzeeu28cDXcxZ/3nNTONJgLzXroivGOkD/S X-Google-Smtp-Source: ABdhPJxmPKWXaW55AXbuN8L0rHqx5zqGp/5SgvazlVcRxnAb4RmK/KDtb+AIMa+vPmDXn/xxXuYQoQ== X-Received: by 2002:a05:6512:3c3:b0:472:5211:ad3 with SMTP id w3-20020a05651203c300b0047252110ad3mr21361107lfp.650.1653432728514; Tue, 24 May 2022 15:52:08 -0700 (PDT) Received: from ubuntu-focal.. ([2a01:4f9:3a:1e26::2]) by smtp.gmail.com with ESMTPSA id k8-20020a2ea288000000b0024f3d1dae84sm2750660lja.12.2022.05.24.15.52.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 24 May 2022 15:52:08 -0700 (PDT) From: Philipp Tomsich To: gcc-patches@gcc.gnu.org Subject: [PATCH v1 3/3] RISC-V: Split "(a & (1UL << bitno)) ? 0 : 1" to bext + xori Date: Wed, 25 May 2022 00:51:56 +0200 Message-Id: <20220524225156.4026293-3-philipp.tomsich@vrull.eu> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220524225156.4026293-1-philipp.tomsich@vrull.eu> References: <20220524225156.4026293-1-philipp.tomsich@vrull.eu> MIME-Version: 1.0 X-Spam-Status: No, score=-11.7 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, JMQ_SPF_NEUTRAL, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Andrew Waterman , Vineet Gupta , Kito Cheng , Philipp Tomsich , Christoph Muellner Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" We avoid reassociating "(~(a >> BIT_NO)) & 1" into "((~a) >> BIT_NO) & 1" by splitting it into a zero-extraction (bext) and an xori. This both avoids burning a register on a temporary and generates a sequence that clearly captures 'extract bit, then invert bit'. This change improves the previously generated srl a0,a0,a1 not a0,a0 andi a0,a0,1 into bext a0,a0,a1 xori a0,a0,1 Signed-off-by: Philipp Tomsich gcc/ChangeLog: * config/riscv/bitmanip.md: Add split covering "(a & (1 << BIT_NO)) ? 0 : 1". gcc/testsuite/ChangeLog: * gcc.target/riscv/zbs-bext.c: Add testcases. * gcc.target/riscv/zbs-bexti.c: Add testcases. --- gcc/config/riscv/bitmanip.md | 13 +++++++++++++ gcc/testsuite/gcc.target/riscv/zbs-bext.c | 10 ++++++++-- gcc/testsuite/gcc.target/riscv/zbs-bexti.c | 10 ++++++++-- 3 files changed, 29 insertions(+), 4 deletions(-) diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md index 5d7c20e9fdc..c4b61880e0c 100644 --- a/gcc/config/riscv/bitmanip.md +++ b/gcc/config/riscv/bitmanip.md @@ -365,3 +365,16 @@ (define_split "TARGET_ZBS" [(set (match_dup 0) (zero_extract:GPR (match_dup 1) (const_int 1) (match_dup 2))) (set (match_dup 0) (plus:GPR (match_dup 0) (const_int -1)))]) + +;; Split for "(a & (1 << BIT_NO)) ? 0 : 1": +;; We avoid reassociating "(~(a >> BIT_NO)) & 1" into "((~a) >> BIT_NO) & 1", +;; so we don't have to use a temporary. Instead we extract the bit and then +;; invert bit 0 ("a ^ 1") only. +(define_split + [(set (match_operand:X 0 "register_operand") + (and:X (not:X (lshiftrt:X (match_operand:X 1 "register_operand") + (subreg:QI (match_operand:X 2 "register_operand") 0))) + (const_int 1)))] + "TARGET_ZBS" + [(set (match_dup 0) (zero_extract:X (match_dup 1) (const_int 1) (match_dup 2))) + (set (match_dup 0) (xor:X (match_dup 0) (const_int 1)))]) diff --git a/gcc/testsuite/gcc.target/riscv/zbs-bext.c b/gcc/testsuite/gcc.target/riscv/zbs-bext.c index 8de9c5a167c..a8aadb60390 100644 --- a/gcc/testsuite/gcc.target/riscv/zbs-bext.c +++ b/gcc/testsuite/gcc.target/riscv/zbs-bext.c @@ -23,16 +23,22 @@ long bext64_1(long a, char bitno) long bext64_2(long a, char bitno) { - return (a & (1UL << bitno)) ? 0 : -1; + return (a & (1UL << bitno)) ? 0 : 1; } long bext64_3(long a, char bitno) +{ + return (a & (1UL << bitno)) ? 0 : -1; +} + +long bext64_4(long a, char bitno) { return (a & (1UL << bitno)) ? -1 : 0; } /* { dg-final { scan-assembler-times "bexti\t" 1 } } */ -/* { dg-final { scan-assembler-times "bext\t" 4 } } */ +/* { dg-final { scan-assembler-times "bext\t" 5 } } */ +/* { dg-final { scan-assembler-times "xori\t|snez\t" 1 } } */ /* { dg-final { scan-assembler-times "addi\t" 1 } } */ /* { dg-final { scan-assembler-times "neg\t" 1 } } */ /* { dg-final { scan-assembler-not "andi" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/riscv/zbs-bexti.c b/gcc/testsuite/gcc.target/riscv/zbs-bexti.c index 8182a61707d..aa13487b357 100644 --- a/gcc/testsuite/gcc.target/riscv/zbs-bexti.c +++ b/gcc/testsuite/gcc.target/riscv/zbs-bexti.c @@ -12,14 +12,20 @@ long bexti64_1(long a, char bitno) long bexti64_2(long a, char bitno) { - return (a & (1UL << BIT_NO)) ? 0 : -1; + return (a & (1UL << BIT_NO)) ? 0 : 1; } long bexti64_3(long a, char bitno) +{ + return (a & (1UL << BIT_NO)) ? 0 : -1; +} + +long bexti64_4(long a, char bitno) { return (a & (1UL << BIT_NO)) ? -1 : 0; } -/* { dg-final { scan-assembler-times "bexti\t" 3 } } */ +/* { dg-final { scan-assembler-times "bexti\t" 4 } } */ +/* { dg-final { scan-assembler-times "xori\t|snez\t" 1 } } */ /* { dg-final { scan-assembler-times "addi\t" 1 } } */ /* { dg-final { scan-assembler-times "neg\t" 1 } } */ \ No newline at end of file