Message ID | 25e731db-6177-6f20-5f04-0a98d3ac39f8@linux.ibm.com |
---|---|
State | New |
Headers |
Return-Path: <gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org> X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id CE3C7385841B for <patchwork@sourceware.org>; Thu, 23 Dec 2021 02:10:08 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org CE3C7385841B DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1640225408; bh=sLRDVKC7e1+uditzu0DzcsBS0bdVWO4jZi+Nuv7GlaE=; h=Subject:To:Date:List-Id:List-Unsubscribe:List-Archive:List-Post: List-Help:List-Subscribe:From:Reply-To:Cc:From; b=ndu/yNpeLW9SV8w0zN+bs7qDx/V0ofcvA6MrEdgztT6WXxGu8yeH4lv58LdKtgMfK H5iQV38pcTLDA3s/L70igsU4PQF8YxuFSqzhh+Zk/UAApIqqZVV9jJCozJ+KMYRj1O mfpBxxmCICCnd3y6cVGVNRuPs3vM3BHALAdtmi80= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mx0a-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com [148.163.158.5]) by sourceware.org (Postfix) with ESMTPS id 243FF3858C60 for <gcc-patches@gcc.gnu.org>; Thu, 23 Dec 2021 02:09:40 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 243FF3858C60 Received: from pps.filterd (m0098413.ppops.net [127.0.0.1]) by mx0b-001b2d01.pphosted.com (8.16.1.2/8.16.1.2) with SMTP id 1BN1BkeJ030818; Thu, 23 Dec 2021 02:09:38 GMT Received: from pps.reinject (localhost [127.0.0.1]) by mx0b-001b2d01.pphosted.com with ESMTP id 3d4f7ygtdr-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 23 Dec 2021 02:09:38 +0000 Received: from m0098413.ppops.net (m0098413.ppops.net [127.0.0.1]) by pps.reinject (8.16.0.43/8.16.0.43) with SMTP id 1BN202IP027081; Thu, 23 Dec 2021 02:09:38 GMT Received: from ppma05fra.de.ibm.com (6c.4a.5195.ip4.static.sl-reverse.com [149.81.74.108]) by mx0b-001b2d01.pphosted.com with ESMTP id 3d4f7ygtd4-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 23 Dec 2021 02:09:38 +0000 Received: from pps.filterd (ppma05fra.de.ibm.com [127.0.0.1]) by ppma05fra.de.ibm.com (8.16.1.2/8.16.1.2) with SMTP id 1BN1r8Ho004000; Thu, 23 Dec 2021 02:09:36 GMT Received: from b06cxnps4074.portsmouth.uk.ibm.com (d06relay11.portsmouth.uk.ibm.com [9.149.109.196]) by ppma05fra.de.ibm.com with ESMTP id 3d1799s03w-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 23 Dec 2021 02:09:36 +0000 Received: from b06wcsmtp001.portsmouth.uk.ibm.com (b06wcsmtp001.portsmouth.uk.ibm.com [9.149.105.160]) by b06cxnps4074.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 1BN29WZB44499396 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Thu, 23 Dec 2021 02:09:32 GMT Received: from b06wcsmtp001.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 98A85A405B; Thu, 23 Dec 2021 02:09:32 +0000 (GMT) Received: from b06wcsmtp001.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 03C5DA4054; Thu, 23 Dec 2021 02:09:31 +0000 (GMT) Received: from kewenlins-mbp.cn.ibm.com (unknown [9.200.147.85]) by b06wcsmtp001.portsmouth.uk.ibm.com (Postfix) with ESMTP; Thu, 23 Dec 2021 02:09:30 +0000 (GMT) Subject: [PATCH] rs6000: Disable MMA if no P9 VECTOR support [PR103627] To: GCC Patches <gcc-patches@gcc.gnu.org> Message-ID: <25e731db-6177-6f20-5f04-0a98d3ac39f8@linux.ibm.com> Date: Thu, 23 Dec 2021 10:09:27 +0800 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:78.0) Gecko/20100101 Thunderbird/78.10.0 MIME-Version: 1.0 Content-Type: text/plain; charset=gbk Content-Language: en-US Content-Transfer-Encoding: 7bit X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: WNtb03P8r9AjGVTVuTk9jnxShqjc8GJk X-Proofpoint-GUID: Gvfmq96j35nY_ZCxWJKARQQgu94LzbC5 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.790,Hydra:6.0.425,FMLib:17.11.62.513 definitions=2021-12-22_09,2021-12-22_01,2021-12-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 adultscore=0 mlxscore=0 clxscore=1015 malwarescore=0 mlxlogscore=980 lowpriorityscore=0 priorityscore=1501 bulkscore=0 spamscore=0 suspectscore=0 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2110150000 definitions=main-2112230008 X-Spam-Status: No, score=-10.9 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, RCVD_IN_MSPIKE_H2, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list <gcc-patches.gcc.gnu.org> List-Unsubscribe: <https://gcc.gnu.org/mailman/options/gcc-patches>, <mailto:gcc-patches-request@gcc.gnu.org?subject=unsubscribe> List-Archive: <https://gcc.gnu.org/pipermail/gcc-patches/> List-Post: <mailto:gcc-patches@gcc.gnu.org> List-Help: <mailto:gcc-patches-request@gcc.gnu.org?subject=help> List-Subscribe: <https://gcc.gnu.org/mailman/listinfo/gcc-patches>, <mailto:gcc-patches-request@gcc.gnu.org?subject=subscribe> From: "Kewen.Lin via Gcc-patches" <gcc-patches@gcc.gnu.org> Reply-To: "Kewen.Lin" <linkw@linux.ibm.com> Cc: Peter Bergner <bergner@linux.ibm.com>, Bill Schmidt <wschmidt@linux.ibm.com>, David Edelsohn <dje.gcc@gmail.com>, Segher Boessenkool <segher@kernel.crashing.org> Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" <gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org> |
Series |
rs6000: Disable MMA if no P9 VECTOR support [PR103627]
|
|
Commit Message
Kewen.Lin
Dec. 23, 2021, 2:09 a.m. UTC
Hi, As PR103627 shows, there is an unexpected case where !TARGET_VSX and TARGET_MMA co-exist. As ISA3.1 claims, SIMD is a requirement for MMA. By looking into the ICE, I noticed that the current MMA implementation depends on vector pairs load/store, but since we don't have a separated option to control Power10 vector, this patch is to check for Power9 vector instead. Bootstrapped and regtested on powerpc64le-linux-gnu P9 and powerpc64-linux-gnu P8. Is it ok for trunk? BR, Kewen ----- gcc/ChangeLog: PR target/103627 * config/rs6000/rs6000.c (rs6000_option_override_internal): Disable MMA if !TARGET_P9_VECTOR. gcc/testsuite/ChangeLog: PR target/103627 * gcc.target/powerpc/pr103627-1.c: New test. * gcc.target/powerpc/pr103627-2.c: New test. --- gcc/config/rs6000/rs6000.c | 11 +++++++++++ gcc/testsuite/gcc.target/powerpc/pr103627-1.c | 16 ++++++++++++++++ gcc/testsuite/gcc.target/powerpc/pr103627-2.c | 16 ++++++++++++++++ 3 files changed, 43 insertions(+) create mode 100644 gcc/testsuite/gcc.target/powerpc/pr103627-1.c create mode 100644 gcc/testsuite/gcc.target/powerpc/pr103627-2.c -- 2.27.0
Comments
Gentle ping: https://gcc.gnu.org/pipermail/gcc-patches/2021-December/587310.html on 2021/12/23 上午10:09, Kewen.Lin via Gcc-patches wrote: > Hi, > > As PR103627 shows, there is an unexpected case where !TARGET_VSX > and TARGET_MMA co-exist. As ISA3.1 claims, SIMD is a requirement > for MMA. By looking into the ICE, I noticed that the current > MMA implementation depends on vector pairs load/store, but since > we don't have a separated option to control Power10 vector, this > patch is to check for Power9 vector instead. > > Bootstrapped and regtested on powerpc64le-linux-gnu P9 and > powerpc64-linux-gnu P8. > > Is it ok for trunk? > > BR, > Kewen > ----- > gcc/ChangeLog: > > PR target/103627 > * config/rs6000/rs6000.c (rs6000_option_override_internal): Disable > MMA if !TARGET_P9_VECTOR. > > gcc/testsuite/ChangeLog: > > PR target/103627 > * gcc.target/powerpc/pr103627-1.c: New test. > * gcc.target/powerpc/pr103627-2.c: New test. > --- > gcc/config/rs6000/rs6000.c | 11 +++++++++++ > gcc/testsuite/gcc.target/powerpc/pr103627-1.c | 16 ++++++++++++++++ > gcc/testsuite/gcc.target/powerpc/pr103627-2.c | 16 ++++++++++++++++ > 3 files changed, 43 insertions(+) > create mode 100644 gcc/testsuite/gcc.target/powerpc/pr103627-1.c > create mode 100644 gcc/testsuite/gcc.target/powerpc/pr103627-2.c > > diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c > index c020947abc8..ec3b46682a7 100644 > --- a/gcc/config/rs6000/rs6000.c > +++ b/gcc/config/rs6000/rs6000.c > @@ -4505,6 +4505,17 @@ rs6000_option_override_internal (bool global_init_p) > rs6000_isa_flags &= ~OPTION_MASK_MMA; > } > > + /* MMA requires SIMD support as ISA 3.1 claims and our implementation > + such as "*movoo" uses vector pair access which are only supported > + from ISA 3.1. But since we don't have one separated option to > + control Power10 vector, check for Power9 vector instead. */ > + if (TARGET_MMA && !TARGET_P9_VECTOR) > + { > + if ((rs6000_isa_flags_explicit & OPTION_MASK_MMA) != 0) > + error ("%qs requires %qs", "-mmma", "-mpower9-vector"); > + rs6000_isa_flags &= ~OPTION_MASK_MMA; > + } > + > if (!TARGET_PCREL && TARGET_PCREL_OPT) > rs6000_isa_flags &= ~OPTION_MASK_PCREL_OPT; > > diff --git a/gcc/testsuite/gcc.target/powerpc/pr103627-1.c b/gcc/testsuite/gcc.target/powerpc/pr103627-1.c > new file mode 100644 > index 00000000000..6c6c16188fb > --- /dev/null > +++ b/gcc/testsuite/gcc.target/powerpc/pr103627-1.c > @@ -0,0 +1,16 @@ > +/* { dg-require-effective-target power10_ok } */ > +/* { dg-options "-mdejagnu-cpu=power10 -mno-power9-vector" } */ > + > +/* Verify compiler emits error message instead of ICE. */ > + > +extern float *dest; > +extern __vector_quad src; > + > +int > +foo () > +{ > + __builtin_mma_disassemble_acc (dest, &src); > + /* { dg-error "'__builtin_mma_disassemble_acc' requires the '-mmma' option" "" { target *-*-* } .-1 } */ > + return 0; > +} > + > diff --git a/gcc/testsuite/gcc.target/powerpc/pr103627-2.c b/gcc/testsuite/gcc.target/powerpc/pr103627-2.c > new file mode 100644 > index 00000000000..6604872c0e8 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/powerpc/pr103627-2.c > @@ -0,0 +1,16 @@ > +/* { dg-require-effective-target power10_ok } */ > +/* { dg-options "-mdejagnu-cpu=power10 -mmma -mno-power9-vector" } */ > + > +/* Verify the emitted error message. */ > + > +extern float *dest; > +extern __vector_quad src; > + > +int > +foo () > +{ > + __builtin_mma_disassemble_acc (dest, &src); > + /* { dg-error "'-mmma' requires '-mpower9-vector'" "mma" { target *-*-* } 0 } */ > + return 0; > +} > + > -- > 2.27.0 >
Gentle ping: https://gcc.gnu.org/pipermail/gcc-patches/2021-December/587310.html BR, Kewen > on 2021/12/23 上午10:09, Kewen.Lin via Gcc-patches wrote: >> Hi, >> >> As PR103627 shows, there is an unexpected case where !TARGET_VSX >> and TARGET_MMA co-exist. As ISA3.1 claims, SIMD is a requirement >> for MMA. By looking into the ICE, I noticed that the current >> MMA implementation depends on vector pairs load/store, but since >> we don't have a separated option to control Power10 vector, this >> patch is to check for Power9 vector instead. >> >> Bootstrapped and regtested on powerpc64le-linux-gnu P9 and >> powerpc64-linux-gnu P8. >> >> Is it ok for trunk? >> >> BR, >> Kewen >> ----- >> gcc/ChangeLog: >> >> PR target/103627 >> * config/rs6000/rs6000.c (rs6000_option_override_internal): Disable >> MMA if !TARGET_P9_VECTOR. >> >> gcc/testsuite/ChangeLog: >> >> PR target/103627 >> * gcc.target/powerpc/pr103627-1.c: New test. >> * gcc.target/powerpc/pr103627-2.c: New test. >> --- >> gcc/config/rs6000/rs6000.c | 11 +++++++++++ >> gcc/testsuite/gcc.target/powerpc/pr103627-1.c | 16 ++++++++++++++++ >> gcc/testsuite/gcc.target/powerpc/pr103627-2.c | 16 ++++++++++++++++ >> 3 files changed, 43 insertions(+) >> create mode 100644 gcc/testsuite/gcc.target/powerpc/pr103627-1.c >> create mode 100644 gcc/testsuite/gcc.target/powerpc/pr103627-2.c >> >> diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c >> index c020947abc8..ec3b46682a7 100644 >> --- a/gcc/config/rs6000/rs6000.c >> +++ b/gcc/config/rs6000/rs6000.c >> @@ -4505,6 +4505,17 @@ rs6000_option_override_internal (bool global_init_p) >> rs6000_isa_flags &= ~OPTION_MASK_MMA; >> } >> >> + /* MMA requires SIMD support as ISA 3.1 claims and our implementation >> + such as "*movoo" uses vector pair access which are only supported >> + from ISA 3.1. But since we don't have one separated option to >> + control Power10 vector, check for Power9 vector instead. */ >> + if (TARGET_MMA && !TARGET_P9_VECTOR) >> + { >> + if ((rs6000_isa_flags_explicit & OPTION_MASK_MMA) != 0) >> + error ("%qs requires %qs", "-mmma", "-mpower9-vector"); >> + rs6000_isa_flags &= ~OPTION_MASK_MMA; >> + } >> + >> if (!TARGET_PCREL && TARGET_PCREL_OPT) >> rs6000_isa_flags &= ~OPTION_MASK_PCREL_OPT; >> >> diff --git a/gcc/testsuite/gcc.target/powerpc/pr103627-1.c b/gcc/testsuite/gcc.target/powerpc/pr103627-1.c >> new file mode 100644 >> index 00000000000..6c6c16188fb >> --- /dev/null >> +++ b/gcc/testsuite/gcc.target/powerpc/pr103627-1.c >> @@ -0,0 +1,16 @@ >> +/* { dg-require-effective-target power10_ok } */ >> +/* { dg-options "-mdejagnu-cpu=power10 -mno-power9-vector" } */ >> + >> +/* Verify compiler emits error message instead of ICE. */ >> + >> +extern float *dest; >> +extern __vector_quad src; >> + >> +int >> +foo () >> +{ >> + __builtin_mma_disassemble_acc (dest, &src); >> + /* { dg-error "'__builtin_mma_disassemble_acc' requires the '-mmma' option" "" { target *-*-* } .-1 } */ >> + return 0; >> +} >> + >> diff --git a/gcc/testsuite/gcc.target/powerpc/pr103627-2.c b/gcc/testsuite/gcc.target/powerpc/pr103627-2.c >> new file mode 100644 >> index 00000000000..6604872c0e8 >> --- /dev/null >> +++ b/gcc/testsuite/gcc.target/powerpc/pr103627-2.c >> @@ -0,0 +1,16 @@ >> +/* { dg-require-effective-target power10_ok } */ >> +/* { dg-options "-mdejagnu-cpu=power10 -mmma -mno-power9-vector" } */ >> + >> +/* Verify the emitted error message. */ >> + >> +extern float *dest; >> +extern __vector_quad src; >> + >> +int >> +foo () >> +{ >> + __builtin_mma_disassemble_acc (dest, &src); >> + /* { dg-error "'-mmma' requires '-mpower9-vector'" "mma" { target *-*-* } 0 } */ >> + return 0; >> +} >> + >> -- >> 2.27.0 >>
Hi! On Thu, Dec 23, 2021 at 10:09:27AM +0800, Kewen.Lin wrote: > As PR103627 shows, there is an unexpected case where !TARGET_VSX > and TARGET_MMA co-exist. As ISA3.1 claims, SIMD is a requirement > for MMA. By looking into the ICE, I noticed that the current > MMA implementation depends on vector pairs load/store, but since > we don't have a separated option to control Power10 vector, this > patch is to check for Power9 vector instead. > > Bootstrapped and regtested on powerpc64le-linux-gnu P9 and > powerpc64-linux-gnu P8. > > Is it ok for trunk? No, sorry. > + /* MMA requires SIMD support as ISA 3.1 claims and our implementation > + such as "*movoo" uses vector pair access which are only supported > + from ISA 3.1. But since we don't have one separated option to > + control Power10 vector, check for Power9 vector instead. */ > + if (TARGET_MMA && !TARGET_P9_VECTOR) > + { > + if ((rs6000_isa_flags_explicit & OPTION_MASK_MMA) != 0) > + error ("%qs requires %qs", "-mmma", "-mpower9-vector"); > + rs6000_isa_flags &= ~OPTION_MASK_MMA; > + } -mpower9-vector is a workaround that should go away. TARGET_MMA should require ISA 3.1 (or POWER10) directly, and require VSX. > +/* { dg-options "-mdejagnu-cpu=power10 -mno-power9-vector" } */ It should be impossible to select this at all. Either you have vectors or you don't, but it should be impossible to selectively disable part of vector support. That way madness lies. We can allow no VSRs, only VRs, or all VSRs. There is precedent for that (see -msoft-float for example, which means "do not use FPRs") -- when compiling certain code we want to disallow whole register banks. But disallowing or allowing some instructions separately is not a good idea: it doesn't give any useful extra functionality, it is hard to use, and it is a lot of extra work for us (it is impossible to test, already, too many combinations). Segher
Hi Segher, on 2022/1/27 上午6:19, Segher Boessenkool wrote: > Hi! > > On Thu, Dec 23, 2021 at 10:09:27AM +0800, Kewen.Lin wrote: >> As PR103627 shows, there is an unexpected case where !TARGET_VSX >> and TARGET_MMA co-exist. As ISA3.1 claims, SIMD is a requirement >> for MMA. By looking into the ICE, I noticed that the current >> MMA implementation depends on vector pairs load/store, but since >> we don't have a separated option to control Power10 vector, this >> patch is to check for Power9 vector instead. >> >> Bootstrapped and regtested on powerpc64le-linux-gnu P9 and >> powerpc64-linux-gnu P8. >> >> Is it ok for trunk? > > No, sorry. > >> + /* MMA requires SIMD support as ISA 3.1 claims and our implementation >> + such as "*movoo" uses vector pair access which are only supported >> + from ISA 3.1. But since we don't have one separated option to >> + control Power10 vector, check for Power9 vector instead. */ >> + if (TARGET_MMA && !TARGET_P9_VECTOR) >> + { >> + if ((rs6000_isa_flags_explicit & OPTION_MASK_MMA) != 0) >> + error ("%qs requires %qs", "-mmma", "-mpower9-vector"); >> + rs6000_isa_flags &= ~OPTION_MASK_MMA; >> + } > > -mpower9-vector is a workaround that should go away. TARGET_MMA should > require ISA 3.1 (or POWER10) directly, and require VSX. OK, I see. Thanks for the detailed explanation below. I guess that's why we don't have one option like "-mpower10-vector" any more? I posted patch v2 guarded with VSX at the below link instead https://gcc.gnu.org/pipermail/gcc-patches/2022-January/589325.html Hope it looks better to you. :) BR, Kewen > >> +/* { dg-options "-mdejagnu-cpu=power10 -mno-power9-vector" } */ > > It should be impossible to select this at all. Either you have vectors > or you don't, but it should be impossible to selectively disable part of > vector support. That way madness lies. > > We can allow no VSRs, only VRs, or all VSRs. There is precedent for > that (see -msoft-float for example, which means "do not use FPRs") -- > when compiling certain code we want to disallow whole register banks. > But disallowing or allowing some instructions separately is not a good > idea: it doesn't give any useful extra functionality, it is hard to use, > and it is a lot of extra work for us (it is impossible to test, already, > too many combinations). > > > Segher >
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index c020947abc8..ec3b46682a7 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -4505,6 +4505,17 @@ rs6000_option_override_internal (bool global_init_p) rs6000_isa_flags &= ~OPTION_MASK_MMA; } + /* MMA requires SIMD support as ISA 3.1 claims and our implementation + such as "*movoo" uses vector pair access which are only supported + from ISA 3.1. But since we don't have one separated option to + control Power10 vector, check for Power9 vector instead. */ + if (TARGET_MMA && !TARGET_P9_VECTOR) + { + if ((rs6000_isa_flags_explicit & OPTION_MASK_MMA) != 0) + error ("%qs requires %qs", "-mmma", "-mpower9-vector"); + rs6000_isa_flags &= ~OPTION_MASK_MMA; + } + if (!TARGET_PCREL && TARGET_PCREL_OPT) rs6000_isa_flags &= ~OPTION_MASK_PCREL_OPT; diff --git a/gcc/testsuite/gcc.target/powerpc/pr103627-1.c b/gcc/testsuite/gcc.target/powerpc/pr103627-1.c new file mode 100644 index 00000000000..6c6c16188fb --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr103627-1.c @@ -0,0 +1,16 @@ +/* { dg-require-effective-target power10_ok } */ +/* { dg-options "-mdejagnu-cpu=power10 -mno-power9-vector" } */ + +/* Verify compiler emits error message instead of ICE. */ + +extern float *dest; +extern __vector_quad src; + +int +foo () +{ + __builtin_mma_disassemble_acc (dest, &src); + /* { dg-error "'__builtin_mma_disassemble_acc' requires the '-mmma' option" "" { target *-*-* } .-1 } */ + return 0; +} + diff --git a/gcc/testsuite/gcc.target/powerpc/pr103627-2.c b/gcc/testsuite/gcc.target/powerpc/pr103627-2.c new file mode 100644 index 00000000000..6604872c0e8 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr103627-2.c @@ -0,0 +1,16 @@ +/* { dg-require-effective-target power10_ok } */ +/* { dg-options "-mdejagnu-cpu=power10 -mmma -mno-power9-vector" } */ + +/* Verify the emitted error message. */ + +extern float *dest; +extern __vector_quad src; + +int +foo () +{ + __builtin_mma_disassemble_acc (dest, &src); + /* { dg-error "'-mmma' requires '-mpower9-vector'" "mma" { target *-*-* } 0 } */ + return 0; +} +