[15/19] <sys/platform/x86.h>: Add MSRLIST support
Commit Message
Add MSRLIST support to <sys/platform/x86.h>.
---
manual/platform.texi | 4 ++++
sysdeps/x86/bits/platform/x86.h | 1 +
sysdeps/x86/tst-get-cpu-features.c | 1 +
3 files changed, 6 insertions(+)
Comments
On Wed, Apr 5, 2023 at 11:26 AM H.J. Lu via Libc-alpha
<libc-alpha@sourceware.org> wrote:
>
> Add MSRLIST support to <sys/platform/x86.h>.
> ---
> manual/platform.texi | 4 ++++
> sysdeps/x86/bits/platform/x86.h | 1 +
> sysdeps/x86/tst-get-cpu-features.c | 1 +
> 3 files changed, 6 insertions(+)
>
> diff --git a/manual/platform.texi b/manual/platform.texi
> index af75e5c413..bfccd024a5 100644
> --- a/manual/platform.texi
> +++ b/manual/platform.texi
> @@ -464,6 +464,10 @@ the indirect branch predictor barrier (IBPB).
> @item
> @code{MSR} -- Model Specific Registers RDMSR and WRMSR instructions.
>
> +@item
> +@code{MSRLIST} -- RDMSRLIST/WRMSRLIST instructions and IA32_BARRIER
> +MSR.
> +
> @item
> @code{MTRR} -- Memory Type Range Registers.
>
> diff --git a/sysdeps/x86/bits/platform/x86.h b/sysdeps/x86/bits/platform/x86.h
> index abc0116607..57973e9a6c 100644
> --- a/sysdeps/x86/bits/platform/x86.h
> +++ b/sysdeps/x86/bits/platform/x86.h
> @@ -302,6 +302,7 @@ enum
> x86_cpu_HRESET = x86_cpu_index_7_ecx_1_eax + 22,
> x86_cpu_AVX_IFMA = x86_cpu_index_7_ecx_1_eax + 23,
> x86_cpu_LAM = x86_cpu_index_7_ecx_1_eax + 26,
> + x86_cpu_MSRLIST = x86_cpu_index_7_ecx_1_eax + 27,
>
> x86_cpu_index_19_ebx
> = (CPUID_INDEX_19 * 8 * 4 * sizeof (unsigned int)
> diff --git a/sysdeps/x86/tst-get-cpu-features.c b/sysdeps/x86/tst-get-cpu-features.c
> index 3a2d4671ec..0c948c2b04 100644
> --- a/sysdeps/x86/tst-get-cpu-features.c
> +++ b/sysdeps/x86/tst-get-cpu-features.c
> @@ -214,6 +214,7 @@ do_test (void)
> CHECK_CPU_FEATURE_PRESENT (HRESET);
> CHECK_CPU_FEATURE_PRESENT (AVX_IFMA);
> CHECK_CPU_FEATURE_PRESENT (LAM);
> + CHECK_CPU_FEATURE_PRESENT (MSRLIST);
> CHECK_CPU_FEATURE_PRESENT (AESKLE);
> CHECK_CPU_FEATURE_PRESENT (WIDE_KL);
> CHECK_CPU_FEATURE_PRESENT (PTWRITE);
> --
> 2.39.2
>
LGTM
Reviewed-by: Noah Goldstein <goldstein.w.n@gmail.com>
@@ -464,6 +464,10 @@ the indirect branch predictor barrier (IBPB).
@item
@code{MSR} -- Model Specific Registers RDMSR and WRMSR instructions.
+@item
+@code{MSRLIST} -- RDMSRLIST/WRMSRLIST instructions and IA32_BARRIER
+MSR.
+
@item
@code{MTRR} -- Memory Type Range Registers.
@@ -302,6 +302,7 @@ enum
x86_cpu_HRESET = x86_cpu_index_7_ecx_1_eax + 22,
x86_cpu_AVX_IFMA = x86_cpu_index_7_ecx_1_eax + 23,
x86_cpu_LAM = x86_cpu_index_7_ecx_1_eax + 26,
+ x86_cpu_MSRLIST = x86_cpu_index_7_ecx_1_eax + 27,
x86_cpu_index_19_ebx
= (CPUID_INDEX_19 * 8 * 4 * sizeof (unsigned int)
@@ -214,6 +214,7 @@ do_test (void)
CHECK_CPU_FEATURE_PRESENT (HRESET);
CHECK_CPU_FEATURE_PRESENT (AVX_IFMA);
CHECK_CPU_FEATURE_PRESENT (LAM);
+ CHECK_CPU_FEATURE_PRESENT (MSRLIST);
CHECK_CPU_FEATURE_PRESENT (AESKLE);
CHECK_CPU_FEATURE_PRESENT (WIDE_KL);
CHECK_CPU_FEATURE_PRESENT (PTWRITE);