diff mbox series

[09/19] <sys/platform/x86.h>: Add LASS support

Message ID 20230405162144.984598-10-hjl.tools@gmail.com
State Committed
Commit aa528a579b3fc98eab43986619087cafe3f260d0
Headers
Series <sys/platform/x86.h>: Update CPUID features |

Checks

Context Check Description
dj/TryBot-apply_patch success Patch applied to master at the time it was sent

Commit Message

H.J. Lu April 5, 2023, 4:21 p.m. UTC 
  Add Linear Address Space Separation (LASS) support to <sys/platform/x86.h>.
---
 manual/platform.texi               | 3 +++
 sysdeps/x86/bits/platform/x86.h    | 1 +
 sysdeps/x86/tst-get-cpu-features.c | 1 +
 3 files changed, 5 insertions(+)

Comments

Noah Goldstein April 5, 2023, 9:04 p.m. UTC | #1 
On Wed, Apr 5, 2023 at 11:26 AM H.J. Lu via Libc-alpha
<libc-alpha@sourceware.org> wrote:
>
> Add Linear Address Space Separation (LASS) support to <sys/platform/x86.h>.
> ---
>  manual/platform.texi               | 3 +++
>  sysdeps/x86/bits/platform/x86.h    | 1 +
>  sysdeps/x86/tst-get-cpu-features.c | 1 +
>  3 files changed, 5 insertions(+)
>
> diff --git a/manual/platform.texi b/manual/platform.texi
> index a6e33b1572..be04194c88 100644
> --- a/manual/platform.texi
> +++ b/manual/platform.texi
> @@ -406,6 +406,9 @@ the indirect branch predictor barrier (IBPB).
>  @item
>  @code{LAM} -- Linear Address Masking.
>
> +@item
> +@code{LASS} -- Linear Address Space Separation.
> +
>  @item
>  @code{LBR} -- Architectural LBR.
>
> diff --git a/sysdeps/x86/bits/platform/x86.h b/sysdeps/x86/bits/platform/x86.h
> index 6fc3b69651..c9ee8fcf90 100644
> --- a/sysdeps/x86/bits/platform/x86.h
> +++ b/sysdeps/x86/bits/platform/x86.h
> @@ -291,6 +291,7 @@ enum
>    x86_cpu_RAO_INT              = x86_cpu_index_7_ecx_1_eax + 3,
>    x86_cpu_AVX_VNNI             = x86_cpu_index_7_ecx_1_eax + 4,
>    x86_cpu_AVX512_BF16          = x86_cpu_index_7_ecx_1_eax + 5,
> +  x86_cpu_LASS                 = x86_cpu_index_7_ecx_1_eax + 6,
>    x86_cpu_FZLRM                        = x86_cpu_index_7_ecx_1_eax + 10,
>    x86_cpu_FSRS                 = x86_cpu_index_7_ecx_1_eax + 11,
>    x86_cpu_FSRCS                        = x86_cpu_index_7_ecx_1_eax + 12,
> diff --git a/sysdeps/x86/tst-get-cpu-features.c b/sysdeps/x86/tst-get-cpu-features.c
> index 6a3f29db98..9da561a559 100644
> --- a/sysdeps/x86/tst-get-cpu-features.c
> +++ b/sysdeps/x86/tst-get-cpu-features.c
> @@ -203,6 +203,7 @@ do_test (void)
>    CHECK_CPU_FEATURE_PRESENT (RAO_INT);
>    CHECK_CPU_FEATURE_PRESENT (AVX_VNNI);
>    CHECK_CPU_FEATURE_PRESENT (AVX512_BF16);
> +  CHECK_CPU_FEATURE_PRESENT (LASS);
>    CHECK_CPU_FEATURE_PRESENT (FZLRM);
>    CHECK_CPU_FEATURE_PRESENT (FSRS);
>    CHECK_CPU_FEATURE_PRESENT (FSRCS);
> --
> 2.39.2
>

LGTM
Reviewed-by: Noah Goldstein <goldstein.w.n@gmail.com>
diff mbox series

Patch

diff --git a/manual/platform.texi b/manual/platform.texi
index a6e33b1572..be04194c88 100644
--- a/manual/platform.texi
+++ b/manual/platform.texi
@@ -406,6 +406,9 @@  the indirect branch predictor barrier (IBPB).
 @item
 @code{LAM} -- Linear Address Masking.
 
+@item
+@code{LASS} -- Linear Address Space Separation.
+
 @item
 @code{LBR} -- Architectural LBR.
 
diff --git a/sysdeps/x86/bits/platform/x86.h b/sysdeps/x86/bits/platform/x86.h
index 6fc3b69651..c9ee8fcf90 100644
--- a/sysdeps/x86/bits/platform/x86.h
+++ b/sysdeps/x86/bits/platform/x86.h
@@ -291,6 +291,7 @@  enum
   x86_cpu_RAO_INT		= x86_cpu_index_7_ecx_1_eax + 3,
   x86_cpu_AVX_VNNI		= x86_cpu_index_7_ecx_1_eax + 4,
   x86_cpu_AVX512_BF16		= x86_cpu_index_7_ecx_1_eax + 5,
+  x86_cpu_LASS			= x86_cpu_index_7_ecx_1_eax + 6,
   x86_cpu_FZLRM			= x86_cpu_index_7_ecx_1_eax + 10,
   x86_cpu_FSRS			= x86_cpu_index_7_ecx_1_eax + 11,
   x86_cpu_FSRCS			= x86_cpu_index_7_ecx_1_eax + 12,
diff --git a/sysdeps/x86/tst-get-cpu-features.c b/sysdeps/x86/tst-get-cpu-features.c
index 6a3f29db98..9da561a559 100644
--- a/sysdeps/x86/tst-get-cpu-features.c
+++ b/sysdeps/x86/tst-get-cpu-features.c
@@ -203,6 +203,7 @@  do_test (void)
   CHECK_CPU_FEATURE_PRESENT (RAO_INT);
   CHECK_CPU_FEATURE_PRESENT (AVX_VNNI);
   CHECK_CPU_FEATURE_PRESENT (AVX512_BF16);
+  CHECK_CPU_FEATURE_PRESENT (LASS);
   CHECK_CPU_FEATURE_PRESENT (FZLRM);
   CHECK_CPU_FEATURE_PRESENT (FSRS);
   CHECK_CPU_FEATURE_PRESENT (FSRCS);