[3/3] gdb: rename offset to high bits in ymm registers
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Commit Message
The xsave_ymm_avx512_offset data structure contains the xsave
offset to the upper 128 bits of a ymm register. Similarly, for zmm this
offset is described by xsave_avx512_zmm_h_offset, h indicating the
high bits. This commit renames the xsave_ymm_avx512_offset to
xsave_ymm_h_avx512_offset - as well as the associated define from
XSAVE_YMM_AVX512_ADDR to XSAVE_YMM_H_AVX512_ADDR - to make this
more consistent.
Note, that the regnum defines already included the 'h' for ymm, like
I387_YMM16H_REGNUM and I387_YMMH_AVX512_END_REGNUM.
Co-authored-by: Nils-Christian Kempke <nils-christian.kempke@intel.com>
---
gdb/i387-tdep.c | 19 ++++++++++---------
1 file changed, 10 insertions(+), 9 deletions(-)
Comments
> -----Original Message-----
> From: Felix Willgerodt <felix.willgerodt@intel.com>
> Sent: Donnerstag, 23. Mai 2024 15:49
> To: gdb-patches@sourceware.org
> Subject: [PATCH 3/3] gdb: rename offset to high bits in ymm registers
>
> The xsave_ymm_avx512_offset data structure contains the xsave
> offset to the upper 128 bits of a ymm register. Similarly, for zmm this
> offset is described by xsave_avx512_zmm_h_offset, h indicating the
> high bits. This commit renames the xsave_ymm_avx512_offset to
> xsave_ymm_h_avx512_offset - as well as the associated define from
> XSAVE_YMM_AVX512_ADDR to XSAVE_YMM_H_AVX512_ADDR - to make this
> more consistent.
>
> Note, that the regnum defines already included the 'h' for ymm, like
> I387_YMM16H_REGNUM and I387_YMMH_AVX512_END_REGNUM.
>
> Co-authored-by: Nils-Christian Kempke <nils-christian.kempke@intel.com>
> ---
> gdb/i387-tdep.c | 19 ++++++++++---------
> 1 file changed, 10 insertions(+), 9 deletions(-)
Kindly pinging. This one is fairly straightforward. I already merged the other 2 patches.
Thanks,
Felix
Intel Deutschland GmbH
Registered Address: Am Campeon 10, 85579 Neubiberg, Germany
Tel: +49 89 99 8853-0, www.intel.de
Managing Directors: Sean Fennelly, Jeffrey Schneiderman, Tiffany Doon Silva
Chairperson of the Supervisory Board: Nicole Lau
Registered Office: Munich
Commercial Register: Amtsgericht Muenchen HRB 186928
> -----Original Message-----
> From: Willgerodt, Felix
> Sent: Donnerstag, 6. Juni 2024 11:13
> To: Felix Willgerodt <felix.willgerodt@intel.com>; gdb-patches@sourceware.org
> Subject: RE: [PATCH 3/3] gdb: rename offset to high bits in ymm registers
>
> > -----Original Message-----
> > From: Felix Willgerodt <felix.willgerodt@intel.com>
> > Sent: Donnerstag, 23. Mai 2024 15:49
> > To: gdb-patches@sourceware.org
> > Subject: [PATCH 3/3] gdb: rename offset to high bits in ymm registers
> >
> > The xsave_ymm_avx512_offset data structure contains the xsave
> > offset to the upper 128 bits of a ymm register. Similarly, for zmm this
> > offset is described by xsave_avx512_zmm_h_offset, h indicating the
> > high bits. This commit renames the xsave_ymm_avx512_offset to
> > xsave_ymm_h_avx512_offset - as well as the associated define from
> > XSAVE_YMM_AVX512_ADDR to XSAVE_YMM_H_AVX512_ADDR - to make this
> > more consistent.
> >
> > Note, that the regnum defines already included the 'h' for ymm, like
> > I387_YMM16H_REGNUM and I387_YMMH_AVX512_END_REGNUM.
> >
> > Co-authored-by: Nils-Christian Kempke <nils-christian.kempke@intel.com>
> > ---
> > gdb/i387-tdep.c | 19 ++++++++++---------
> > 1 file changed, 10 insertions(+), 9 deletions(-)
>
> Kindly pinging. This one is fairly straightforward. I already merged the other 2
> patches.
>
> Thanks,
> Felix
*Ping* v2
Thanks,
Felix
Intel Deutschland GmbH
Registered Address: Am Campeon 10, 85579 Neubiberg, Germany
Tel: +49 89 99 8853-0, www.intel.de
Managing Directors: Sean Fennelly, Jeffrey Schneiderman, Tiffany Doon Silva
Chairperson of the Supervisory Board: Nicole Lau
Registered Office: Munich
Commercial Register: Amtsgericht Muenchen HRB 186928
Felix Willgerodt <felix.willgerodt@intel.com> writes:
> The xsave_ymm_avx512_offset data structure contains the xsave
> offset to the upper 128 bits of a ymm register. Similarly, for zmm this
> offset is described by xsave_avx512_zmm_h_offset, h indicating the
> high bits. This commit renames the xsave_ymm_avx512_offset to
> xsave_ymm_h_avx512_offset - as well as the associated define from
> XSAVE_YMM_AVX512_ADDR to XSAVE_YMM_H_AVX512_ADDR - to make this
> more consistent.
>
> Note, that the regnum defines already included the 'h' for ymm, like
> I387_YMM16H_REGNUM and I387_YMMH_AVX512_END_REGNUM.
LGTM.
Approved-By: Andrew Burgess <aburgess@redhat.com>
Thanks,
Andrew
>
> Co-authored-by: Nils-Christian Kempke <nils-christian.kempke@intel.com>
> ---
> gdb/i387-tdep.c | 19 ++++++++++---------
> 1 file changed, 10 insertions(+), 9 deletions(-)
>
> diff --git a/gdb/i387-tdep.c b/gdb/i387-tdep.c
> index 45bd43a50a9..675ee8d2e81 100644
> --- a/gdb/i387-tdep.c
> +++ b/gdb/i387-tdep.c
> @@ -762,11 +762,11 @@ static int xsave_avxh_offset[] =
> (xsave + (tdep)->xsave_layout.avx_offset \
> + xsave_avxh_offset[regnum - I387_YMM0H_REGNUM (tdep)])
>
> -/* At xsave_ymm_avx512_offset[REGNUM] you'll find the relative offset
> +/* At xsave_ymm_h_avx512_offset[REGNUM] you'll find the relative offset
> within the ZMM region of the XSAVE extended state where the second
> 128bits of GDB register YMM16 + REGNUM is stored. */
>
> -static int xsave_ymm_avx512_offset[] =
> +static int xsave_ymm_h_avx512_offset[] =
> {
> 16 + 0 * 64, /* %ymm16 through... */
> 16 + 1 * 64,
> @@ -786,9 +786,9 @@ static int xsave_ymm_avx512_offset[] =
> 16 + 15 * 64 /* ... %ymm31 (128 bits each). */
> };
>
> -#define XSAVE_YMM_AVX512_ADDR(tdep, xsave, regnum) \
> +#define XSAVE_YMM_H_AVX512_ADDR(tdep, xsave, regnum) \
> (xsave + (tdep)->xsave_layout.zmm_offset \
> - + xsave_ymm_avx512_offset[regnum - I387_YMM16H_REGNUM (tdep)])
> + + xsave_ymm_h_avx512_offset[regnum - I387_YMM16H_REGNUM (tdep)])
>
> /* At xsave_xmm_avx512_offset[REGNUM] you'll find the relative offset
> within the ZMM region of the XSAVE extended state where the first
> @@ -1187,7 +1187,7 @@ i387_supply_xsave (struct regcache *regcache, int regnum,
> regcache->raw_supply (regnum, zero);
> else
> regcache->raw_supply (regnum,
> - XSAVE_YMM_AVX512_ADDR (tdep, regs, regnum));
> + XSAVE_YMM_H_AVX512_ADDR (tdep, regs, regnum));
> return;
>
> case avx512_xmm_avx512:
> @@ -1314,7 +1314,8 @@ i387_supply_xsave (struct regcache *regcache, int regnum,
> for (i = I387_YMM16H_REGNUM (tdep);
> i < I387_YMMH_AVX512_END_REGNUM (tdep);
> i++)
> - regcache->raw_supply (i, XSAVE_YMM_AVX512_ADDR (tdep, regs, i));
> + regcache->raw_supply (i,
> + XSAVE_YMM_H_AVX512_ADDR (tdep, regs, i));
> for (i = I387_XMM16_REGNUM (tdep);
> i < I387_XMM_AVX512_END_REGNUM (tdep);
> i++)
> @@ -1644,7 +1645,7 @@ i387_collect_xsave (const struct regcache *regcache, int regnum,
> memset (XSAVE_AVX512_ZMM16_H_ADDR (tdep, regs, i), 0, 32);
> for (i = I387_YMM16H_REGNUM (tdep);
> i < I387_YMMH_AVX512_END_REGNUM (tdep); i++)
> - memset (XSAVE_YMM_AVX512_ADDR (tdep, regs, i), 0, 16);
> + memset (XSAVE_YMM_H_AVX512_ADDR (tdep, regs, i), 0, 16);
> for (i = I387_XMM16_REGNUM (tdep);
> i < I387_XMM_AVX512_END_REGNUM (tdep); i++)
> memset (XSAVE_XMM_AVX512_ADDR (tdep, regs, i), 0, 16);
> @@ -1750,7 +1751,7 @@ i387_collect_xsave (const struct regcache *regcache, int regnum,
> i < I387_YMMH_AVX512_END_REGNUM (tdep); i++)
> {
> regcache->raw_collect (i, raw);
> - p = XSAVE_YMM_AVX512_ADDR (tdep, regs, i);
> + p = XSAVE_YMM_H_AVX512_ADDR (tdep, regs, i);
> if (memcmp (raw, p, 16) != 0)
> {
> xstate_bv |= X86_XSTATE_ZMM;
> @@ -1911,7 +1912,7 @@ i387_collect_xsave (const struct regcache *regcache, int regnum,
>
> case avx512_ymmh_avx512:
> /* This is an upper YMM16-31 register. */
> - p = XSAVE_YMM_AVX512_ADDR (tdep, regs, regnum);
> + p = XSAVE_YMM_H_AVX512_ADDR (tdep, regs, regnum);
> if (memcmp (raw, p, 16) != 0)
> {
> xstate_bv |= X86_XSTATE_ZMM;
> --
> 2.34.1
>
> Intel Deutschland GmbH
> Registered Address: Am Campeon 10, 85579 Neubiberg, Germany
> Tel: +49 89 99 8853-0, www.intel.de
> Managing Directors: Sean Fennelly, Jeffrey Schneiderman, Tiffany Doon Silva
> Chairperson of the Supervisory Board: Nicole Lau
> Registered Office: Munich
> Commercial Register: Amtsgericht Muenchen HRB 186928
> -----Original Message-----
> From: Andrew Burgess <aburgess@redhat.com>
> Sent: Montag, 17. Juni 2024 14:39
> To: Willgerodt, Felix <felix.willgerodt@intel.com>; gdb-
> patches@sourceware.org
> Subject: Re: [PATCH 3/3] gdb: rename offset to high bits in ymm registers
>
> Felix Willgerodt <felix.willgerodt@intel.com> writes:
>
> > The xsave_ymm_avx512_offset data structure contains the xsave
> > offset to the upper 128 bits of a ymm register. Similarly, for zmm this
> > offset is described by xsave_avx512_zmm_h_offset, h indicating the
> > high bits. This commit renames the xsave_ymm_avx512_offset to
> > xsave_ymm_h_avx512_offset - as well as the associated define from
> > XSAVE_YMM_AVX512_ADDR to XSAVE_YMM_H_AVX512_ADDR - to make
> this
> > more consistent.
> >
> > Note, that the regnum defines already included the 'h' for ymm, like
> > I387_YMM16H_REGNUM and I387_YMMH_AVX512_END_REGNUM.
>
> LGTM.
>
> Approved-By: Andrew Burgess <aburgess@redhat.com>
>
> Thanks,
> Andrew
Thanks, I pushed this.
Felix
Intel Deutschland GmbH
Registered Address: Am Campeon 10, 85579 Neubiberg, Germany
Tel: +49 89 99 8853-0, www.intel.de
Managing Directors: Sean Fennelly, Jeffrey Schneiderman, Tiffany Doon Silva
Chairperson of the Supervisory Board: Nicole Lau
Registered Office: Munich
Commercial Register: Amtsgericht Muenchen HRB 186928
@@ -762,11 +762,11 @@ static int xsave_avxh_offset[] =
(xsave + (tdep)->xsave_layout.avx_offset \
+ xsave_avxh_offset[regnum - I387_YMM0H_REGNUM (tdep)])
-/* At xsave_ymm_avx512_offset[REGNUM] you'll find the relative offset
+/* At xsave_ymm_h_avx512_offset[REGNUM] you'll find the relative offset
within the ZMM region of the XSAVE extended state where the second
128bits of GDB register YMM16 + REGNUM is stored. */
-static int xsave_ymm_avx512_offset[] =
+static int xsave_ymm_h_avx512_offset[] =
{
16 + 0 * 64, /* %ymm16 through... */
16 + 1 * 64,
@@ -786,9 +786,9 @@ static int xsave_ymm_avx512_offset[] =
16 + 15 * 64 /* ... %ymm31 (128 bits each). */
};
-#define XSAVE_YMM_AVX512_ADDR(tdep, xsave, regnum) \
+#define XSAVE_YMM_H_AVX512_ADDR(tdep, xsave, regnum) \
(xsave + (tdep)->xsave_layout.zmm_offset \
- + xsave_ymm_avx512_offset[regnum - I387_YMM16H_REGNUM (tdep)])
+ + xsave_ymm_h_avx512_offset[regnum - I387_YMM16H_REGNUM (tdep)])
/* At xsave_xmm_avx512_offset[REGNUM] you'll find the relative offset
within the ZMM region of the XSAVE extended state where the first
@@ -1187,7 +1187,7 @@ i387_supply_xsave (struct regcache *regcache, int regnum,
regcache->raw_supply (regnum, zero);
else
regcache->raw_supply (regnum,
- XSAVE_YMM_AVX512_ADDR (tdep, regs, regnum));
+ XSAVE_YMM_H_AVX512_ADDR (tdep, regs, regnum));
return;
case avx512_xmm_avx512:
@@ -1314,7 +1314,8 @@ i387_supply_xsave (struct regcache *regcache, int regnum,
for (i = I387_YMM16H_REGNUM (tdep);
i < I387_YMMH_AVX512_END_REGNUM (tdep);
i++)
- regcache->raw_supply (i, XSAVE_YMM_AVX512_ADDR (tdep, regs, i));
+ regcache->raw_supply (i,
+ XSAVE_YMM_H_AVX512_ADDR (tdep, regs, i));
for (i = I387_XMM16_REGNUM (tdep);
i < I387_XMM_AVX512_END_REGNUM (tdep);
i++)
@@ -1644,7 +1645,7 @@ i387_collect_xsave (const struct regcache *regcache, int regnum,
memset (XSAVE_AVX512_ZMM16_H_ADDR (tdep, regs, i), 0, 32);
for (i = I387_YMM16H_REGNUM (tdep);
i < I387_YMMH_AVX512_END_REGNUM (tdep); i++)
- memset (XSAVE_YMM_AVX512_ADDR (tdep, regs, i), 0, 16);
+ memset (XSAVE_YMM_H_AVX512_ADDR (tdep, regs, i), 0, 16);
for (i = I387_XMM16_REGNUM (tdep);
i < I387_XMM_AVX512_END_REGNUM (tdep); i++)
memset (XSAVE_XMM_AVX512_ADDR (tdep, regs, i), 0, 16);
@@ -1750,7 +1751,7 @@ i387_collect_xsave (const struct regcache *regcache, int regnum,
i < I387_YMMH_AVX512_END_REGNUM (tdep); i++)
{
regcache->raw_collect (i, raw);
- p = XSAVE_YMM_AVX512_ADDR (tdep, regs, i);
+ p = XSAVE_YMM_H_AVX512_ADDR (tdep, regs, i);
if (memcmp (raw, p, 16) != 0)
{
xstate_bv |= X86_XSTATE_ZMM;
@@ -1911,7 +1912,7 @@ i387_collect_xsave (const struct regcache *regcache, int regnum,
case avx512_ymmh_avx512:
/* This is an upper YMM16-31 register. */
- p = XSAVE_YMM_AVX512_ADDR (tdep, regs, regnum);
+ p = XSAVE_YMM_H_AVX512_ADDR (tdep, regs, regnum);
if (memcmp (raw, p, 16) != 0)
{
xstate_bv |= X86_XSTATE_ZMM;