mbox series

[v6,0/2] sim: riscv: Compressed instruction simulation

Message ID 20240111052822.1576345-1-jaydeep.patil@imgtec.com
Headers
Series sim: riscv: Compressed instruction simulation |

Message

Jaydeep Patil Jan. 11, 2024, 5:28 a.m. UTC 
  From: Jaydeep Patil <jaydeep.patil@imgtec.com>

Hi Mike, Andrew,

Addressed review comments.
 - Restored opcodes/riscv-dis.c
 - Commit message changed to "sim: riscv:"

Jaydeep Patil (2):
  sim: riscv: Fix crash during instruction decoding
  sim: riscv: Add support for compressed integer instructions

 sim/riscv/model_list.def        |   9 +
 sim/riscv/sim-main.c            | 339 ++++++++++++++++++++++++++++++--
 sim/testsuite/riscv/allinsn.exp |   2 +-
 sim/testsuite/riscv/c-ext.s     |  95 +++++++++
 sim/testsuite/riscv/jalr.s      |   2 +-
 sim/testsuite/riscv/m-ext.s     |   2 +-
 sim/testsuite/riscv/pass.s      |   2 +-
 7 files changed, 436 insertions(+), 15 deletions(-)
 create mode 100644 sim/testsuite/riscv/c-ext.s