ppc: testsuite: test for arch_pwr7 with -mvsx in fold-vec-insert-double
Commit Message
gcc.target/powerpc/fold-vec-insert-double.c is compiled with -mvsx,
while the expected asm output depends on target has_arch_pwr7, which
is tested for without -mvsx.
In some of our configurations, that have altivec and vsx disabled by
default, the former defines up to _ARCH_PWR7, while the latter defines
only up to _ARCH_PWR4, i.e., we compile for power7, and test for
non-power7.
This patch, admittedly ugly, enables us to test for asm output
according the actual compile target given the explicitly specified
flag.
I suppose it may be possible to turn this "magic" into a reusable proc
that sets a named variable to the result of a wrapped scan test, but
I'm not sure I'm up to the task, with the need to deal with additional
scoping, so I'm hoping this can be acceptable as is.
Tested with gcc-11 targeting ppc64-vx7r2. Ok to install?
for gcc/testsuite/ChangeLog
* gcc.target/powerpc/fold-vec-insert-double.c: Test for asm
according to the arch selected by -mvsx.
---
.../gcc.target/powerpc/fold-vec-insert-double.c | 48 ++++++++++++++++----
1 file changed, 39 insertions(+), 9 deletions(-)
Comments
On Mon, Apr 11, 2022 at 08:59:41PM -0300, Alexandre Oliva wrote:
>
> gcc.target/powerpc/fold-vec-insert-double.c is compiled with -mvsx,
> while the expected asm output depends on target has_arch_pwr7, which
> is tested for without -mvsx.
>
> In some of our configurations, that have altivec and vsx disabled by
> default, the former defines up to _ARCH_PWR7, while the latter defines
> only up to _ARCH_PWR4, i.e., we compile for power7, and test for
> non-power7.
You cannot use -mvsx if you do not have -mcpu=power7 (or higher). If
-mvsx is allowed (i.e. when powerpc_vsx_ok is satisfied) you always are
compiling for power7 or higher.
What goes wrong?
Segher
On Apr 12, 2022, Segher Boessenkool <segher@kernel.crashing.org> wrote:
> On Mon, Apr 11, 2022 at 08:59:41PM -0300, Alexandre Oliva wrote:
>>
>> gcc.target/powerpc/fold-vec-insert-double.c is compiled with -mvsx,
>> while the expected asm output depends on target has_arch_pwr7, which
>> is tested for without -mvsx.
>>
>> In some of our configurations, that have altivec and vsx disabled by
>> default, the former defines up to _ARCH_PWR7, while the latter defines
>> only up to _ARCH_PWR4, i.e., we compile for power7, and test for
>> non-power7.
> You cannot use -mvsx if you do not have -mcpu=power7 (or higher). If
> -mvsx is allowed (i.e. when powerpc_vsx_ok is satisfied) you always are
> compiling for power7 or higher.
> What goes wrong?
What goes wrong is that, because target has_arch_pwr7 runs the compiler
without -mvsx, it gets only power4, so we test for the asm associated
with target { ! has_arch_pwr7 }, which is not what's generated.
Now, since -mvsx requires power7, it looks like the scan-assembler tests
with target { ! has_arch_pwr7 } could be dropped, since they can
(should) never run, and so could the target { has_arch_pwr7 }
conditionals, since they can (should) be taken for granted.
That makes for a much nicer patch. Tested on x86_64-linux-gnu cross to
ppc64-vx7r2. Ok to install?
ppc: testsuite: drop pwr7 conds in fold-vec-insert-double-insert-double
gcc.target/powerpc/fold-vec-insert-double.c is compiled with -mvsx,
which implies power7, but there are scan-assembler checks that depend
on target has_arch_pwr7, negated or not, and that target conditional
is tested for running the compiler without -mvsx.
In some of our configurations, that have altivec and vsx disabled by
default, the former defines up to _ARCH_PWR7, while the latter defines
only up to _ARCH_PWR4, i.e., we compile for power7, and test for
non-power7.
Since -mvsx implies power7, the tests for target has_arch_pwr7 would
be redundant if performed with -mvsx, so I'm dropping the checks
guarded by ! has_arch_pwr7, and dropping has_arch_pwr7 from the
others.
for gcc/testsuite/ChangeLog
* gcc.target/powerpc/fold-vec-insert-double.c: Constant-fold
has_arch_pwr7, implied by -mvsx.
---
.../gcc.target/powerpc/fold-vec-insert-double.c | 16 ++++++----------
1 file changed, 6 insertions(+), 10 deletions(-)
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-insert-double.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-insert-double.c
index afd7f7e9924e8..e99d5f40b2da9 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-insert-double.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-insert-double.c
@@ -24,15 +24,11 @@ testd_cst (double d, vector double vd)
/* { dg-final { scan-assembler-times {\mrldic\M|\mrlwinm\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mstxvd2x\M|\mstxv\M|\mstvx\M} 1 { target { ! has_arch_pwr7 } } } } */
-/* { dg-final { scan-assembler-times {\mstfdx\M|\mstfd\M} 1 { target { ! has_arch_pwr7 } } } } */
-/* { dg-final { scan-assembler-times {\mlxvd2x\M|\mlxv\M|\mlvx\M} 1 { target { ! has_arch_pwr7 } } } } */
+/* { dg-final { scan-assembler-times {\mstxvd2x\M|\mstxv\M|\mstvx\M} 0 { target { lp64 } } } } */
+/* { dg-final { scan-assembler-times {\mstfdx\M|\mstfd\M} 0 { target { lp64 } } } } */
-/* { dg-final { scan-assembler-times {\mstxvd2x\M|\mstxv\M|\mstvx\M} 0 { target { has_arch_pwr7 && lp64 } } } } */
-/* { dg-final { scan-assembler-times {\mstfdx\M|\mstfd\M} 0 { target { has_arch_pwr7 && lp64 } } } } */
-
-/* { dg-final { scan-assembler-times {\mlxvd2x\M|\mlxv\M|\mlvx\M} 0 { target { has_arch_pwr7 && lp64 } } } } */
-/* { dg-final { scan-assembler-times {\mlxvd2x\M|\mlxv\M|\mlvx\M} 0 { target { has_arch_pwr7 && ilp32 } } } } */
-/* { dg-final { scan-assembler-times {\mstxvd2x\M|\mstxv\M|\mstvx\M} 0 { target { has_arch_pwr7 && ilp32 } } } } */
-/* { dg-final { scan-assembler-times {\mstfdx\M|\mstfd\M} 0 { target { has_arch_pwr7 && ilp32 } } } } */
+/* { dg-final { scan-assembler-times {\mlxvd2x\M|\mlxv\M|\mlvx\M} 0 { target { lp64 } } } } */
+/* { dg-final { scan-assembler-times {\mlxvd2x\M|\mlxv\M|\mlvx\M} 0 { target { ilp32 } } } } */
+/* { dg-final { scan-assembler-times {\mstxvd2x\M|\mstxv\M|\mstvx\M} 0 { target { ilp32 } } } } */
+/* { dg-final { scan-assembler-times {\mstfdx\M|\mstfd\M} 0 { target { ilp32 } } } } */
@@ -18,21 +18,51 @@ testd_cst (double d, vector double vd)
{
return vec_insert (d, vd, 1);
}
+
+/* The expected asm output varies depending on target arch_has_pwr7, but the
+ -mvsx option used for the test may implicitly enable the macro that target
+ arch_has_pwr7 tests for, while target arch_has_pwr7 doesn't take the option,
+ so we may end up compiling for one target variant and testing for another.
+ The following dejagnu magic sets $macro_is_defined to 1 or 0 depending on
+ whether ARCH_PWR7_is_defined appears in the assembly output. */
+#ifdef _ARCH_PWR7
+int ARCH_PWR7_is_defined = 1;
+/* { dg-final { set asm_pattern_to_search_for "ARCH_PWR7_is_defined" } } */
+#endif
+
+/* { dg-final { global macro_is_defined } } */
+/* { dg-final { set macro_is_defined -1 } } */
+/* { dg-final { rename pass macro-save-pass } } */
+/* { dg-final { rename fail macro-save-fail } } */
+/* { dg-final { proc pass { args } { global macro_is_defined; set macro_is_defined 1 } } } */
+/* { dg-final { proc fail { args } { global macro_is_defined; set macro_is_defined 0 } } } */
+/* { dg-final { scan-assembler "$asm_pattern_to_search_for" } } */
+/* { dg-final { rename pass macro-dropme-pass } } */
+/* { dg-final { rename macro-save-pass pass } } */
+/* { dg-final { rename fail macro-dropme-fail } } */
+/* { dg-final { rename macro-save-fail fail } } */
+/* { dg-final { if { $macro_is_defined < 0 } { fail "macro detection" } } } */
+/* { dg-final { if { $macro_is_defined < 0 } { return } } } */
+
+/* { dg-final { set has_arch_pwr7 $macro_is_defined } } */
+/* This is the end of the magic.
+ We can now run tests conditionally on $has_arch_pwr7. */
+
/* The number of xxpermdi instructions varies between
P7,P8,P9, ensure at least one hit. */
/* { dg-final { scan-assembler {\mxxpermdi\M} } } */
/* { dg-final { scan-assembler-times {\mrldic\M|\mrlwinm\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mstxvd2x\M|\mstxv\M|\mstvx\M} 1 { target { ! has_arch_pwr7 } } } } */
-/* { dg-final { scan-assembler-times {\mstfdx\M|\mstfd\M} 1 { target { ! has_arch_pwr7 } } } } */
-/* { dg-final { scan-assembler-times {\mlxvd2x\M|\mlxv\M|\mlvx\M} 1 { target { ! has_arch_pwr7 } } } } */
+/* { dg-final { if { ! $has_arch_pwr7 } { scan-assembler-times {\mstxvd2x\M|\mstxv\M|\mstvx\M} 1 } } } */
+/* { dg-final { if { ! $has_arch_pwr7 } { scan-assembler-times {\mstfdx\M|\mstfd\M} 1 } } } */
+/* { dg-final { if { ! $has_arch_pwr7 } { scan-assembler-times {\mlxvd2x\M|\mlxv\M|\mlvx\M} 1 } } } */
-/* { dg-final { scan-assembler-times {\mstxvd2x\M|\mstxv\M|\mstvx\M} 0 { target { has_arch_pwr7 && lp64 } } } } */
-/* { dg-final { scan-assembler-times {\mstfdx\M|\mstfd\M} 0 { target { has_arch_pwr7 && lp64 } } } } */
+/* { dg-final { if { $has_arch_pwr7 } { scan-assembler-times {\mstxvd2x\M|\mstxv\M|\mstvx\M} 0 { target { lp64 } } } } } */
+/* { dg-final { if { $has_arch_pwr7 } { scan-assembler-times {\mstfdx\M|\mstfd\M} 0 { target { lp64 } } } } } */
-/* { dg-final { scan-assembler-times {\mlxvd2x\M|\mlxv\M|\mlvx\M} 0 { target { has_arch_pwr7 && lp64 } } } } */
-/* { dg-final { scan-assembler-times {\mlxvd2x\M|\mlxv\M|\mlvx\M} 0 { target { has_arch_pwr7 && ilp32 } } } } */
-/* { dg-final { scan-assembler-times {\mstxvd2x\M|\mstxv\M|\mstvx\M} 0 { target { has_arch_pwr7 && ilp32 } } } } */
-/* { dg-final { scan-assembler-times {\mstfdx\M|\mstfd\M} 0 { target { has_arch_pwr7 && ilp32 } } } } */
+/* { dg-final { if { $has_arch_pwr7 } { scan-assembler-times {\mlxvd2x\M|\mlxv\M|\mlvx\M} 0 { target { lp64 } } } } } */
+/* { dg-final { if { $has_arch_pwr7 } { scan-assembler-times {\mlxvd2x\M|\mlxv\M|\mlvx\M} 0 { target { ilp32 } } } } } */
+/* { dg-final { if { $has_arch_pwr7 } { scan-assembler-times {\mstxvd2x\M|\mstxv\M|\mstvx\M} 0 { target { ilp32 } } } } } */
+/* { dg-final { if { $has_arch_pwr7 } { scan-assembler-times {\mstfdx\M|\mstfd\M} 0 { target { ilp32 } } } } } */