diff mbox series

Add -mevex512 into invoke.texi

Message ID 20240110023452.2312519-1-haochen.jiang@intel.com
State New
Headers
Series Add -mevex512 into invoke.texi |

Checks

Context Check Description
linaro-tcwg-bot/tcwg_gcc_build--master-arm success Testing passed
linaro-tcwg-bot/tcwg_gcc_build--master-aarch64 success Testing passed
linaro-tcwg-bot/tcwg_gcc_check--master-arm success Testing passed
linaro-tcwg-bot/tcwg_gcc_check--master-aarch64 success Testing passed

Commit Message

Jiang, Haochen Jan. 10, 2024, 2:34 a.m. UTC 
  Hi Richard,

It seems that I send out a not updated patch. This patch should what
I want to send.

Thx,
Haochen

gcc/ChangeLog:

	* doc/invoke.texi: Add -mevex512.
---
 gcc/doc/invoke.texi | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

Comments

Richard Biener Jan. 10, 2024, 9:41 a.m. UTC | #1 
On Wed, Jan 10, 2024 at 3:35 AM Haochen Jiang <haochen.jiang@intel.com> wrote:
>
> Hi Richard,
>
> It seems that I send out a not updated patch. This patch should what
> I want to send.

OK

> Thx,
> Haochen
>
> gcc/ChangeLog:
>
>         * doc/invoke.texi: Add -mevex512.
> ---
>  gcc/doc/invoke.texi | 7 ++++++-
>  1 file changed, 6 insertions(+), 1 deletion(-)
>
> diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
> index 68d1f364ac0..6d4f92f1101 100644
> --- a/gcc/doc/invoke.texi
> +++ b/gcc/doc/invoke.texi
> @@ -1463,7 +1463,7 @@ See RS/6000 and PowerPC Options.
>  -mamx-tile  -mamx-int8  -mamx-bf16 -muintr -mhreset -mavxvnni
>  -mavx512fp16 -mavxifma -mavxvnniint8 -mavxneconvert -mcmpccxadd -mamx-fp16
>  -mprefetchi -mraoint -mamx-complex -mavxvnniint16 -msm3 -msha512 -msm4 -mapxf
> --musermsr -mavx10.1 -mavx10.1-256 -mavx10.1-512
> +-musermsr -mavx10.1 -mavx10.1-256 -mavx10.1-512 -mevex512
>  -mcldemote  -mms-bitfields  -mno-align-stringops  -minline-all-stringops
>  -minline-stringops-dynamically  -mstringop-strategy=@var{alg}
>  -mkl -mwidekl
> @@ -35272,6 +35272,11 @@ r8-r15 registers so that the call and jmp instruction length is 6 bytes
>  to allow them to be replaced with @samp{lfence; call *%r8-r15} or
>  @samp{lfence; jmp *%r8-r15} at run-time.
>
> +@opindex mevex512
> +@item -mevex512
> +@itemx -mno-evex512
> +Enables/disables 512-bit vector. It will be default on if AVX512F is enabled.
> +
>  @end table
>
>  These @samp{-m} switches are supported in addition to the above
> --
> 2.31.1
>
diff mbox series

Patch

diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 68d1f364ac0..6d4f92f1101 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -1463,7 +1463,7 @@  See RS/6000 and PowerPC Options.
 -mamx-tile  -mamx-int8  -mamx-bf16 -muintr -mhreset -mavxvnni
 -mavx512fp16 -mavxifma -mavxvnniint8 -mavxneconvert -mcmpccxadd -mamx-fp16
 -mprefetchi -mraoint -mamx-complex -mavxvnniint16 -msm3 -msha512 -msm4 -mapxf
--musermsr -mavx10.1 -mavx10.1-256 -mavx10.1-512
+-musermsr -mavx10.1 -mavx10.1-256 -mavx10.1-512 -mevex512
 -mcldemote  -mms-bitfields  -mno-align-stringops  -minline-all-stringops
 -minline-stringops-dynamically  -mstringop-strategy=@var{alg}
 -mkl -mwidekl
@@ -35272,6 +35272,11 @@  r8-r15 registers so that the call and jmp instruction length is 6 bytes
 to allow them to be replaced with @samp{lfence; call *%r8-r15} or
 @samp{lfence; jmp *%r8-r15} at run-time.
 
+@opindex mevex512
+@item -mevex512
+@itemx -mno-evex512
+Enables/disables 512-bit vector. It will be default on if AVX512F is enabled.
+
 @end table
 
 These @samp{-m} switches are supported in addition to the above