From patchwork Wed Jan 10 02:34:52 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Jiang, Haochen" X-Patchwork-Id: 83715 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id A34DD3857B97 for ; Wed, 10 Jan 2024 02:35:34 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.12]) by sourceware.org (Postfix) with ESMTPS id 9644A38582B8 for ; Wed, 10 Jan 2024 02:34:56 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 9644A38582B8 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=intel.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 9644A38582B8 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=198.175.65.12 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1704854102; cv=none; b=P7JWP06Z4sW6KbHnP5BRrMB8vJ47B9CMSXpaYwyw9pPfhf6tfVaABST1m9YMS3fbhpezUUzIbgjD0SuSg2lCyNI31IsCmxShWN/ddeiGsouZ7k+/igT/h3EbbWAml055gmA4C97StSouFsc41F2kUTlW+rnD+jDcFKGqTocUTVk= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1704854102; c=relaxed/simple; bh=jnMtnyZ3q3Sf5yr3zWyQ5Us86hVXIc+NZZgfU10WHCI=; h=DKIM-Signature:From:To:Subject:Date:Message-Id:MIME-Version; b=Cf8mER1Va1JnSUXCVp8lvYmtxjjHHoKKKbCcIxHv3Iod0sIVUvghLBDEuITh3gPZYdwDWHB9e0x9tYIGQ1ozBvZt4akuNWFIkx0FZxdUP9WUlV0Qtl7hzTDQTDoHqpvaJ7lcJeKb4aC76F3FNENA2IZs+fuwtjoZLTR4dktpCOw= ARC-Authentication-Results: i=1; server2.sourceware.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1704854096; x=1736390096; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=jnMtnyZ3q3Sf5yr3zWyQ5Us86hVXIc+NZZgfU10WHCI=; b=RCgHqfK7ehbhmVKEbN9mArv7yPPw63//ea4ZJ3XjpSq1uZalA10mUI6L wD/CjdXtJn3N6E6JioL8AQSKigV3AOr9U3otKN9PpdxM79I7AoqAR4Ge8 mXeP/vMBmZphXrCNL/9RqFjxmxEf6D9Mhy2L8f5iBcOjVIVCbeNyWxMYv fvQjj7JYhIAM6F4+mk4bW4Wlo1LuMq/MlYwjdMnyjOg4Kn2SEibheohBA 9/uOD7lPp690J6aC9TUHq1VMFyv3e9nJcfwHoZ+YHYCfX84GCQKex/1VB 7vTcOQLLHHLdxSaDtRgrtUKZrk7Su6mqg3GQh5EZE9UiVW1/4pcG3vcXI w==; X-IronPort-AV: E=McAfee;i="6600,9927,10947"; a="5748313" X-IronPort-AV: E=Sophos;i="6.04,184,1695711600"; d="scan'208";a="5748313" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orvoesa104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Jan 2024 18:34:55 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10947"; a="905366291" X-IronPort-AV: E=Sophos;i="6.04,184,1695711600"; d="scan'208";a="905366291" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by orsmga004.jf.intel.com with ESMTP; 09 Jan 2024 18:34:53 -0800 Received: from shliclel4217.sh.intel.com (shliclel4217.sh.intel.com [10.239.240.127]) by shvmail03.sh.intel.com (Postfix) with ESMTP id 8651A10079D5 for ; Wed, 10 Jan 2024 10:34:52 +0800 (CST) From: Haochen Jiang To: gcc-patches@gcc.gnu.org Subject: [PATCH] Add -mevex512 into invoke.texi Date: Wed, 10 Jan 2024 10:34:52 +0800 Message-Id: <20240110023452.2312519-1-haochen.jiang@intel.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: References: MIME-Version: 1.0 X-Spam-Status: No, score=-11.9 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Hi Richard, It seems that I send out a not updated patch. This patch should what I want to send. Thx, Haochen gcc/ChangeLog: * doc/invoke.texi: Add -mevex512. --- gcc/doc/invoke.texi | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 68d1f364ac0..6d4f92f1101 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -1463,7 +1463,7 @@ See RS/6000 and PowerPC Options. -mamx-tile -mamx-int8 -mamx-bf16 -muintr -mhreset -mavxvnni -mavx512fp16 -mavxifma -mavxvnniint8 -mavxneconvert -mcmpccxadd -mamx-fp16 -mprefetchi -mraoint -mamx-complex -mavxvnniint16 -msm3 -msha512 -msm4 -mapxf --musermsr -mavx10.1 -mavx10.1-256 -mavx10.1-512 +-musermsr -mavx10.1 -mavx10.1-256 -mavx10.1-512 -mevex512 -mcldemote -mms-bitfields -mno-align-stringops -minline-all-stringops -minline-stringops-dynamically -mstringop-strategy=@var{alg} -mkl -mwidekl @@ -35272,6 +35272,11 @@ r8-r15 registers so that the call and jmp instruction length is 6 bytes to allow them to be replaced with @samp{lfence; call *%r8-r15} or @samp{lfence; jmp *%r8-r15} at run-time. +@opindex mevex512 +@item -mevex512 +@itemx -mno-evex512 +Enables/disables 512-bit vector. It will be default on if AVX512F is enabled. + @end table These @samp{-m} switches are supported in addition to the above