@@ -16662,13 +16662,15 @@ (define_insn "*bmi2_rorx<mode>3_1"
(set_attr "mode" "<MODE>")])
(define_insn "*<insn><mode>3_1"
- [(set (match_operand:SWI48 0 "nonimmediate_operand" "=rm,r")
+ [(set (match_operand:SWI48 0 "nonimmediate_operand" "=rm,r,r")
(any_rotate:SWI48
- (match_operand:SWI48 1 "nonimmediate_operand" "0,rm")
- (match_operand:QI 2 "nonmemory_operand" "c<S>,<S>")))
+ (match_operand:SWI48 1 "nonimmediate_operand" "0,rm,rm")
+ (match_operand:QI 2 "nonmemory_operand" "c<S>,<S>,c<S>")))
(clobber (reg:CC FLAGS_REG))]
- "ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
+ "ix86_binary_operator_ok (<CODE>, <MODE>mode, operands,
+ TARGET_APX_NDD)"
{
+ bool use_ndd = (which_alternative == 2);
switch (get_attr_type (insn))
{
case TYPE_ROTATEX:
@@ -16676,14 +16678,16 @@ (define_insn "*<insn><mode>3_1"
default:
if (operands[2] == const1_rtx
- && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun)))
+ && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun))
+ && !use_ndd)
return "<rotate>{<imodesuffix>}\t%0";
else
- return "<rotate>{<imodesuffix>}\t{%2, %0|%0, %2}";
+ return use_ndd ? "<rotate>{<imodesuffix>}\t{%2, %1, %0|%0, %1, %2}"
+ : "<rotate>{<imodesuffix>}\t{%2, %0|%0, %2}";
}
}
- [(set_attr "isa" "*,bmi2")
- (set_attr "type" "rotate,rotatex")
+ [(set_attr "isa" "*,bmi2,apx_ndd")
+ (set_attr "type" "rotate,rotatex,rotate")
(set (attr "preferred_for_size")
(cond [(eq_attr "alternative" "0")
(symbol_ref "true")]
@@ -16733,13 +16737,14 @@ (define_insn "*bmi2_rorxsi3_1_zext"
(set_attr "mode" "SI")])
(define_insn "*<insn>si3_1_zext"
- [(set (match_operand:DI 0 "register_operand" "=r,r")
+ [(set (match_operand:DI 0 "register_operand" "=r,r,r")
(zero_extend:DI
- (any_rotate:SI (match_operand:SI 1 "nonimmediate_operand" "0,rm")
- (match_operand:QI 2 "nonmemory_operand" "cI,I"))))
+ (any_rotate:SI (match_operand:SI 1 "nonimmediate_operand" "0,rm,rm")
+ (match_operand:QI 2 "nonmemory_operand" "cI,I,cI"))))
(clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT && ix86_binary_operator_ok (<CODE>, SImode, operands)"
{
+ bool use_ndd = (which_alternative == 2);
switch (get_attr_type (insn))
{
case TYPE_ROTATEX:
@@ -16747,14 +16752,16 @@ (define_insn "*<insn>si3_1_zext"
default:
if (operands[2] == const1_rtx
- && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun)))
+ && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun))
+ && !use_ndd)
return "<rotate>{l}\t%k0";
else
- return "<rotate>{l}\t{%2, %k0|%k0, %2}";
+ return use_ndd ? "<rotate>{l}\t{%2, %1, %k0|%k0, %1, %2}"
+ : "<rotate>{l}\t{%2, %k0|%k0, %2}";
}
}
- [(set_attr "isa" "*,bmi2")
- (set_attr "type" "rotate,rotatex")
+ [(set_attr "isa" "*,bmi2,apx_ndd")
+ (set_attr "type" "rotate,rotatex,rotate")
(set (attr "preferred_for_size")
(cond [(eq_attr "alternative" "0")
(symbol_ref "true")]
@@ -16798,19 +16805,25 @@ (define_split
(zero_extend:DI (rotatert:SI (match_dup 1) (match_dup 2))))])
(define_insn "*<insn><mode>3_1"
- [(set (match_operand:SWI12 0 "nonimmediate_operand" "=<r>m")
- (any_rotate:SWI12 (match_operand:SWI12 1 "nonimmediate_operand" "0")
- (match_operand:QI 2 "nonmemory_operand" "c<S>")))
+ [(set (match_operand:SWI12 0 "nonimmediate_operand" "=<r>m,r")
+ (any_rotate:SWI12 (match_operand:SWI12 1 "nonimmediate_operand" "0,rm")
+ (match_operand:QI 2 "nonmemory_operand" "c<S>,c<S>")))
(clobber (reg:CC FLAGS_REG))]
- "ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
+ "ix86_binary_operator_ok (<CODE>, <MODE>mode, operands,
+ TARGET_APX_NDD)"
{
+ bool use_ndd = which_alternative == 1;
if (operands[2] == const1_rtx
- && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun)))
+ && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun))
+ && !use_ndd)
return "<rotate>{<imodesuffix>}\t%0";
else
- return "<rotate>{<imodesuffix>}\t{%2, %0|%0, %2}";
+ return use_ndd
+ ? "<rotate>{<imodesuffix>}\t{%2, %1, %0|%0, %1, %2}"
+ : "<rotate>{<imodesuffix>}\t{%2, %0|%0, %2}";
}
- [(set_attr "type" "rotate")
+ [(set_attr "isa" "*,apx_ndd")
+ (set_attr "type" "rotate")
(set (attr "length_immediate")
(if_then_else
(and (match_operand 2 "const1_operand")
@@ -16867,31 +16880,37 @@ (define_split
;; Rotations through carry flag
(define_insn "rcrsi2"
- [(set (match_operand:SI 0 "register_operand" "=r")
+ [(set (match_operand:SI 0 "register_operand" "=r,r")
(plus:SI
- (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
+ (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0,rm")
(const_int 1))
(ashift:SI (ltu:SI (reg:CCC FLAGS_REG) (const_int 0))
(const_int 31))))
(clobber (reg:CC FLAGS_REG))]
""
- "rcr{l}\t%0"
- [(set_attr "type" "ishift1")
+ "@
+ rcr{l}\t%0
+ rcr{l}\t{%1, %0|%0, %1}"
+ [(set_attr "isa" "*,apx_ndd")
+ (set_attr "type" "ishift1")
(set_attr "memory" "none")
(set_attr "length_immediate" "0")
(set_attr "mode" "SI")])
(define_insn "rcrdi2"
- [(set (match_operand:DI 0 "register_operand" "=r")
+ [(set (match_operand:DI 0 "register_operand" "=r,r")
(plus:DI
- (lshiftrt:DI (match_operand:DI 1 "register_operand" "0")
+ (lshiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0,rm")
(const_int 1))
(ashift:DI (ltu:DI (reg:CCC FLAGS_REG) (const_int 0))
(const_int 63))))
(clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT"
- "rcr{q}\t%0"
- [(set_attr "type" "ishift1")
+ "@
+ rcr{q}\t%0
+ rcr{q}\t{%1, %0|%0, %1}"
+ [(set_attr "isa" "*,apx_ndd")
+ (set_attr "type" "ishift1")
(set_attr "length_immediate" "0")
(set_attr "mode" "DI")])
@@ -40,6 +40,14 @@ foo3_##OP_NAME##_##TYPE (TYPE a) \
return b; \
}
+#define FOO4(TYPE, OP_NAME, OP1, OP2, IMM1) \
+TYPE \
+__attribute__ ((noipa)) \
+foo4_##OP_NAME##_##TYPE (TYPE a) \
+{ \
+ TYPE b = (a OP1 IMM1 | a OP2 (8 * sizeof(TYPE) - IMM1)); \
+ return b; \
+}
#define F(TYPE, OP_NAME, OP) \
TYPE \
@@ -152,6 +160,16 @@ FOO3 (uint32_t, shr, >>, 7)
FOO (uint64_t, shr, >>)
FOO3 (uint64_t, shr, >>, 7)
+FOO4 (uint8_t, ror, >>, <<, 1)
+FOO4 (uint16_t, ror, >>, <<, 1)
+FOO4 (uint32_t, ror, >>, <<, 1)
+FOO4 (uint64_t, ror, >>, <<, 1)
+
+FOO4 (uint8_t, rol, <<, >>, 1)
+FOO4 (uint16_t, rol, <<, >>, 1)
+FOO4 (uint32_t, rol, <<, >>, 1)
+FOO4 (uint64_t, rol, <<, >>, 1)
+
/* { dg-final { scan-assembler-times "add(?:b|l|w|q)\[^\n\r]*1, \\(%rdi\\), %(?:|r|e)a(?:x|l)" 4 } } */
/* { dg-final { scan-assembler-times "lea(?:l|q)\[^\n\r]\\(%r(?:d|s)i,%r(?:d|s)i\\), %(?:|r|e)ax" 4 } } */
/* { dg-final { scan-assembler-times "add(?:b|l|w|q)\[^\n\r]%(?:|r|e)si(?:|l), \\(%rdi\\), %(?:|r|e)a(?:x|l)" 4 } } */
@@ -180,3 +198,5 @@ FOO3 (uint64_t, shr, >>, 7)
/* { dg-final { scan-assembler-times "sar(?:b|l|w|q)\[^\n\r]*7, %(?:|r|e)di(?:|l), %(?:|r|e)a(?:x|l)" 4 } } */
/* { dg-final { scan-assembler-times "shr(?:b|l|w|q)\[^\n\r]*1, \\(%rdi\\), %(?:|r|e)a(?:x|l)" 4 } } */
/* { dg-final { scan-assembler-times "shr(?:b|l|w|q)\[^\n\r]*7, %(?:|r|e)di(?:|l), %(?:|r|e)a(?:x|l)" 4 } } */
+/* { dg-final { scan-assembler-times "ror(?:b|l|w|q)\[^\n\r]*1, %(?:|r|e)di(?:|l), %(?:|r|e)a(?:x|l)" 4 } } */
+/* { dg-final { scan-assembler-times "rol(?:b|l|w|q)\[^\n\r]*1, %(?:|r|e)di(?:|l), %(?:|r|e)a(?:x|l)" 4 } } */