diff mbox series

[09/17,APX,NDD] Support APX NDD for not insn

Message ID	20231205022948.504790-10-hongyu.wang@intel.com
State	New
Headers	DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 28D90388622E From: Hongyu Wang <hongyu.wang@intel.com> To: gcc-patches@gcc.gnu.org Cc: ubizjak@gmail.com, hongtao.liu@intel.com, Kong Lingling <lingling.kong@intel.com> Subject: [PATCH 09/17] [APX NDD] Support APX NDD for not insn Date: Tue, 5 Dec 2023 10:29:40 +0800 Message-Id: <20231205022948.504790-10-hongyu.wang@intel.com> In-Reply-To: <20231205022948.504790-1-hongyu.wang@intel.com> References: <20231205022948.504790-1-hongyu.wang@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: softfail client-ip=192.55.52.136; envelope-from=wwwhhhyyy333@gmail.com; helo=mgamail.intel.com X-Spam_score_int: -5 X-Spam_score: -0.6 X-Spam_bar: / X-Spam_report: (-0.6 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, SPF_HELO_NONE=0.001, SPF_SOFTFAIL=0.665, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action Precedence: list Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org
Series	Support Intel APX NDD \| [v2,00/17] Support Intel APX NDD [01/17,APX,NDD] Support Intel APX NDD for legacy add insn [02/17,APX,NDD] Restrict TImode register usage when NDD enabled [03/17,APX,NDD] Support APX NDD for optimization patterns of add [04/17,APX,NDD] Disable seg_prefixed memory usage for NDD add [05/17,APX,NDD] Support APX NDD for adc insns [06/17,APX,NDD] Support APX NDD for sub insns [07/17,APX,NDD] Support APX NDD for sbb insn [08/17,APX,NDD] Support APX NDD for neg insn [09/17,APX,NDD] Support APX NDD for not insn [10/17,APX,NDD] Support APX NDD for and insn [11/17,APX,NDD] Support APX NDD for or/xor insn [12/17,APX,NDD] Support APX NDD for left shift insns [13/17,APX,NDD] Support APX NDD for right shift insns [14/17,APX,NDD] Support APX NDD for rotate insns [15/17,APX,NDD] Support APX NDD for shld/shrd insns [16/17,APX,NDD] Support APX NDD for cmove insns [17/17,APX,NDD] Support TImode shift for NDD

Commit Message

Hongyu Wang Dec. 5, 2023, 2:29 a.m. UTC

  From: Kong Lingling <lingling.kong@intel.com>

For *one_cmplsi2_2_zext, it will be splitted to xor, so its NDD form will be
added together with xor NDD support.

gcc/ChangeLog:

	* config/i386/i386.md (one_cmpl<mode>2): Add new constraints for NDD
	and adjust output template.
	(*one_cmpl<mode>2_1): Likewise.
	(*one_cmplqi2_1): Likewise.
	(*one_cmpl<dwi>2_doubleword): Likewise.
	(*one_cmpl<mode>2_2): Likewise.
	(*one_cmplsi2_1_zext): Likewise, and use nonimmediate_operand for
	operands[1] to accept memory input for NDD alternative.

gcc/testsuite/ChangeLog:

	* gcc.target/i386/apx-ndd.c: Add not test.
---
 gcc/config/i386/i386.md                 | 58 ++++++++++++++-----------
 gcc/testsuite/gcc.target/i386/apx-ndd.c | 11 +++++
 2 files changed, 44 insertions(+), 25 deletions(-)

diff mbox series

Patch

diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index 1a2fb116f01..050779273a7 100644
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -14001,57 +14001,63 @@  (define_expand "one_cmpl<mode>2"
   [(set (match_operand:SDWIM 0 "nonimmediate_operand")
 	(not:SDWIM (match_operand:SDWIM 1 "nonimmediate_operand")))]
   ""
-  "ix86_expand_unary_operator (NOT, <MODE>mode, operands); DONE;")
+  "ix86_expand_unary_operator (NOT, <MODE>mode, operands,
+			       TARGET_APX_NDD); DONE;")
 
 (define_insn_and_split "*one_cmpl<dwi>2_doubleword"
-  [(set (match_operand:<DWI> 0 "nonimmediate_operand" "=ro")
-	(not:<DWI> (match_operand:<DWI> 1 "nonimmediate_operand" "0")))]
-  "ix86_unary_operator_ok (NOT, <DWI>mode, operands)"
+  [(set (match_operand:<DWI> 0 "nonimmediate_operand" "=ro,r")
+	(not:<DWI> (match_operand:<DWI> 1 "nonimmediate_operand" "0,ro")))]
+  "ix86_unary_operator_ok (NOT, <DWI>mode, operands, TARGET_APX_NDD)"
   "#"
   "&& reload_completed"
   [(set (match_dup 0)
 	(not:DWIH (match_dup 1)))
    (set (match_dup 2)
 	(not:DWIH (match_dup 3)))]
-  "split_double_mode (<DWI>mode, &operands[0], 2, &operands[0], &operands[2]);")
+  "split_double_mode (<DWI>mode, &operands[0], 2, &operands[0], &operands[2]);"
+  [(set_attr "isa" "*,apx_ndd")])
 
 (define_insn "*one_cmpl<mode>2_1"
-  [(set (match_operand:SWI248 0 "nonimmediate_operand" "=rm,?k")
-	(not:SWI248 (match_operand:SWI248 1 "nonimmediate_operand" "0,k")))]
-  "ix86_unary_operator_ok (NOT, <MODE>mode, operands)"
+  [(set (match_operand:SWI248 0 "nonimmediate_operand" "=rm,r,?k")
+	(not:SWI248 (match_operand:SWI248 1 "nonimmediate_operand" "0,rm,k")))]
+  "ix86_unary_operator_ok (NOT, <MODE>mode, operands, TARGET_APX_NDD)"
   "@
    not{<imodesuffix>}\t%0
+   not{<imodesuffix>}\t{%1, %0|%0, %1}
    #"
-  [(set_attr "isa" "*,<kmov_isa>")
-   (set_attr "type" "negnot,msklog")
+  [(set_attr "isa" "*,apx_ndd,<kmov_isa>")
+   (set_attr "type" "negnot,negnot,msklog")
    (set_attr "mode" "<MODE>")])
 
 (define_insn "*one_cmplsi2_1_zext"
-  [(set (match_operand:DI 0 "register_operand" "=r,?k")
+  [(set (match_operand:DI 0 "register_operand" "=r,r,?k")
 	(zero_extend:DI
-	  (not:SI (match_operand:SI 1 "register_operand" "0,k"))))]
-  "TARGET_64BIT && ix86_unary_operator_ok (NOT, SImode, operands)"
+	  (not:SI (match_operand:SI 1 "nonimmediate_operand" "0,rm,k"))))]
+  "TARGET_64BIT && ix86_unary_operator_ok (NOT, SImode, operands,
+					   TARGET_APX_NDD)"
   "@
    not{l}\t%k0
+   not{l}\t{%1, %k0|%k0, %1}
    #"
-  [(set_attr "isa" "x64,avx512bw_512")
-   (set_attr "type" "negnot,msklog")
-   (set_attr "mode" "SI,SI")])
+  [(set_attr "isa" "x64,apx_ndd,avx512bw_512")
+   (set_attr "type" "negnot,negnot,msklog")
+   (set_attr "mode" "SI,SI,SI")])
 
 (define_insn "*one_cmplqi2_1"
-  [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,r,?k")
-	(not:QI (match_operand:QI 1 "nonimmediate_operand" "0,0,k")))]
-  "ix86_unary_operator_ok (NOT, QImode, operands)"
+  [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,r,r,?k")
+	(not:QI (match_operand:QI 1 "nonimmediate_operand" "0,0,rm,k")))]
+  "ix86_unary_operator_ok (NOT, QImode, operands, TARGET_APX_NDD)"
   "@
    not{b}\t%0
    not{l}\t%k0
+   not{b}\t{%1, %0|%0, %1}
    #"
-  [(set_attr "isa" "*,*,avx512f")
-   (set_attr "type" "negnot,negnot,msklog")
+  [(set_attr "isa" "*,*,apx_ndd,avx512f")
+   (set_attr "type" "negnot,negnot,negnot,msklog")
    (set (attr "mode")
 	(cond [(eq_attr "alternative" "1")
 		 (const_string "SI")
-		(and (eq_attr "alternative" "2")
+		(and (eq_attr "alternative" "3")
 		     (match_test "!TARGET_AVX512DQ"))
 		 (const_string "HI")
 	       ]
@@ -14081,14 +14087,16 @@  (define_insn_and_split "*one_cmpl<mode>_1_slp"
 
 (define_insn "*one_cmpl<mode>2_2"
   [(set (reg FLAGS_REG)
-	(compare (not:SWI (match_operand:SWI 1 "nonimmediate_operand" "0"))
+	(compare (not:SWI (match_operand:SWI 1 "nonimmediate_operand" "0,rm"))
 		 (const_int 0)))
-   (set (match_operand:SWI 0 "nonimmediate_operand" "=<r>m")
+   (set (match_operand:SWI 0 "nonimmediate_operand" "=<r>m,r")
 	(not:SWI (match_dup 1)))]
   "ix86_match_ccmode (insn, CCNOmode)
-   && ix86_unary_operator_ok (NOT, <MODE>mode, operands)"
+   && ix86_unary_operator_ok (NOT, <MODE>mode, operands,
+			      TARGET_APX_NDD)"
   "#"
   [(set_attr "type" "alu1")
+   (set_attr "isa" "*,apx_ndd")
    (set_attr "mode" "<MODE>")])
 
 (define_split
diff --git a/gcc/testsuite/gcc.target/i386/apx-ndd.c b/gcc/testsuite/gcc.target/i386/apx-ndd.c
index c351f71265e..2bd551614c4 100644
--- a/gcc/testsuite/gcc.target/i386/apx-ndd.c
+++ b/gcc/testsuite/gcc.target/i386/apx-ndd.c
@@ -76,6 +76,15 @@  F (int, neg, -)
 F1 (int, neg, -)
 F (long, neg, -)
 F1 (long, neg, -)
+
+F (char, not, ~)
+F1 (char, not, ~)
+F (short, not, ~)
+F1 (short, not, ~)
+F (int, not, ~)
+F1 (int, not, ~)
+F (long, not, ~)
+F1 (long, not, ~)
 /* { dg-final { scan-assembler-times "add(?:b|l|w|q)\[^\n\r]*1, \\(%rdi\\), %(?:|r|e)a(?:x|l)" 4 } } */
 /* { dg-final { scan-assembler-times "lea(?:l|q)\[^\n\r]\\(%r(?:d|s)i,%r(?:d|s)i\\), %(?:|r|e)ax" 4 } } */
 /* { dg-final { scan-assembler-times "add(?:b|l|w|q)\[^\n\r]%(?:|r|e)si(?:|l), \\(%rdi\\), %(?:|r|e)a(?:x|l)" 4 } } */
@@ -84,3 +93,5 @@  F1 (long, neg, -)
 /* { dg-final { scan-assembler-times "negb\[^\n\r]\\(%rdi\\), %(?:|r|e)al" 1 } } */
 /* { dg-final { scan-assembler-times "neg(?:l|w|q)\[^\n\r]\\(%rdi\\), %(?:|r|e)ax" 3 } } */
 /* { dg-final { scan-assembler-times "neg(?:l|w|q)\[^\n\r]%(?:|r|e)di, %(?:|r|e)ax" 4 } } */
+/* { dg-final { scan-assembler-times "not(?:b|l|w|q)\[^\n\r]\\(%rdi\\), %(?:|r|e)a(?:x|l)" 4 } } */
+/* { dg-final { scan-assembler-times "not(?:l|w|q)\[^\n\r]%(?:|r|e)di, %(?:|r|e)ax" 4 } } */