diff mbox series

[1/2] Improve do_store_flag for single bit when there is no non-zero bits

Message ID 20230605055331.2864335-1-apinski@marvell.com
State Committed
Commit e60593f3881c72a96a3fa4844d73e8a2cd14f670
Headers
Series [1/2] Improve do_store_flag for single bit when there is no non-zero bits |

Checks

Context Check Description
linaro-tcwg-bot/tcwg_gcc_build--master-arm success Testing passed
linaro-tcwg-bot/tcwg_gcc_check--master-aarch64 success Testing passed
linaro-tcwg-bot/tcwg_gcc_check--master-arm success Testing passed
linaro-tcwg-bot/tcwg_gcc_build--master-aarch64 success Testing passed

Commit Message

Andrew Pinski June 5, 2023, 5:53 a.m. UTC 
  In r14-1534-g908e5ab5c11c, I forgot you could turn off CCP or
turn off the bit tracking part of CCP so we would lose out
what TER was able to do before hand. This moves around the
TER code so that it is used instead of just the nonzerobits.
It also makes it easier to remove the TER part of the code
later on too.

OK? Bootstrapped and tested on x86_64-linux-gnu.

Note it reintroduces PR 110117 (which was accidently fixed after
r14-1534-g908e5ab5c11c). The next patch in series will fix that.

gcc/ChangeLog:

	* expr.cc (do_store_flag): Rearrange the
	TER code so that it overrides the nonzero bits
	info if we had `a & POW2`.
---
 gcc/expr.cc | 28 +++++++++++-----------------
 1 file changed, 11 insertions(+), 17 deletions(-)

Comments

Jeff Law June 7, 2023, 2:54 a.m. UTC | #1 
On 6/4/23 23:53, Andrew Pinski via Gcc-patches wrote:
> In r14-1534-g908e5ab5c11c, I forgot you could turn off CCP or
> turn off the bit tracking part of CCP so we would lose out
> what TER was able to do before hand. This moves around the
> TER code so that it is used instead of just the nonzerobits.
> It also makes it easier to remove the TER part of the code
> later on too.
Given that we want to kill TER, that seems like a good idea :-)

> 
> OK? Bootstrapped and tested on x86_64-linux-gnu.
> 
> Note it reintroduces PR 110117 (which was accidently fixed after
> r14-1534-g908e5ab5c11c). The next patch in series will fix that.
> 
> gcc/ChangeLog:
> 
> 	* expr.cc (do_store_flag): Rearrange the
> 	TER code so that it overrides the nonzero bits
> 	info if we had `a & POW2`.
OK.
jeff
diff mbox series

Patch

diff --git a/gcc/expr.cc b/gcc/expr.cc
index 58f5fe76372..ca008cd453e 100644
--- a/gcc/expr.cc
+++ b/gcc/expr.cc
@@ -13164,38 +13164,32 @@  do_store_flag (sepops ops, rtx target, machine_mode mode)
       && (TYPE_PRECISION (ops->type) != 1 || TYPE_UNSIGNED (ops->type)))
     {
       wide_int nz = tree_nonzero_bits (arg0);
+      gimple *srcstmt = get_def_for_expr (arg0, BIT_AND_EXPR);
+      /* If the defining statement was (x & POW2), then use that instead of
+	 the non-zero bits.  */
+      if (srcstmt && integer_pow2p (gimple_assign_rhs2 (srcstmt)))
+	{
+	  nz = wi::to_wide (gimple_assign_rhs2 (srcstmt));
+	  arg0 = gimple_assign_rhs1 (srcstmt);
+	}
 
       if (wi::popcount (nz) == 1
 	  && (integer_zerop (arg1)
 	      || wi::to_wide (arg1) == nz))
 	{
-	  tree op0;
-	  int bitnum;
-	  gimple *srcstmt = get_def_for_expr (arg0, BIT_AND_EXPR);
-	  /* If the defining statement was (x & POW2), then remove the and
-	     as we are going to add it back. */
-	  if (srcstmt
-	      && integer_pow2p (gimple_assign_rhs2 (srcstmt)))
-	    {
-	      op0 = gimple_assign_rhs1 (srcstmt);
-	      bitnum = tree_log2 (gimple_assign_rhs2 (srcstmt));
-	    }
-	  else
-	    {
-	      op0 = arg0;
-	      bitnum = wi::exact_log2 (nz);
-	    }
+	  int bitnum = wi::exact_log2 (nz);
 	  enum tree_code tcode = EQ_EXPR;
 	  if ((code == NE) ^ !integer_zerop (arg1))
 	    tcode = NE_EXPR;
 
 	  type = lang_hooks.types.type_for_mode (mode, unsignedp);
 	  return expand_single_bit_test (loc, tcode,
-					 op0,
+					 arg0,
 					 bitnum, type, target, mode);
 	}
     }
 
+
   if (! get_subtarget (target)
       || GET_MODE (subtarget) != operand_mode)
     subtarget = 0;