From patchwork Mon Jun 5 05:53:30 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Pinski X-Patchwork-Id: 70580 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 9DE3A385662B for ; Mon, 5 Jun 2023 05:54:25 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 9DE3A385662B DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1685944465; bh=8ENLvHp9UqS+Lsdgk0t9HoL/4d4Xppd0saDIWAphxlY=; h=To:CC:Subject:Date:List-Id:List-Unsubscribe:List-Archive: List-Post:List-Help:List-Subscribe:From:Reply-To:From; b=tBrnLiP9jiYZ7RRRk1cX9jv5sylBtt59StEfFuw/2OuWnlFn0ymHKvJqeR6ATZKNB XnwltqtREGCcqfACcVdtzEHFsmucadDaC7zqnPVH0XAkVwIAbPogdLMy/68cZb6qxN EfJR3DfS6jceQFK+Eb1kYPBPHNITe4wCkyZseUtU= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by sourceware.org (Postfix) with ESMTPS id 634CD3858401 for ; Mon, 5 Jun 2023 05:53:57 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 634CD3858401 Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 354KeHLP015673 for ; Sun, 4 Jun 2023 22:53:56 -0700 Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3r02vpda1j-2 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Sun, 04 Jun 2023 22:53:56 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.48; Sun, 4 Jun 2023 22:53:55 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Sun, 4 Jun 2023 22:53:55 -0700 Received: from vpnclient.wrightpinski.org.com (unknown [10.69.242.187]) by maili.marvell.com (Postfix) with ESMTP id DFA0F3F704A; Sun, 4 Jun 2023 22:53:54 -0700 (PDT) To: CC: Andrew Pinski Subject: [PATCH 1/2] Improve do_store_flag for single bit when there is no non-zero bits Date: Sun, 4 Jun 2023 22:53:30 -0700 Message-ID: <20230605055331.2864335-1-apinski@marvell.com> X-Mailer: git-send-email 2.31.1 MIME-Version: 1.0 X-Proofpoint-GUID: oxDWcxofHo5L3OtPZ-Mju7SnL79a0nQe X-Proofpoint-ORIG-GUID: oxDWcxofHo5L3OtPZ-Mju7SnL79a0nQe X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.573,FMLib:17.11.176.26 definitions=2023-06-03_08,2023-06-02_02,2023-05-22_02 X-Spam-Status: No, score=-14.6 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_DNSWL_LOW, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Andrew Pinski via Gcc-patches From: Andrew Pinski Reply-To: Andrew Pinski Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" In r14-1534-g908e5ab5c11c, I forgot you could turn off CCP or turn off the bit tracking part of CCP so we would lose out what TER was able to do before hand. This moves around the TER code so that it is used instead of just the nonzerobits. It also makes it easier to remove the TER part of the code later on too. OK? Bootstrapped and tested on x86_64-linux-gnu. Note it reintroduces PR 110117 (which was accidently fixed after r14-1534-g908e5ab5c11c). The next patch in series will fix that. gcc/ChangeLog: * expr.cc (do_store_flag): Rearrange the TER code so that it overrides the nonzero bits info if we had `a & POW2`. --- gcc/expr.cc | 28 +++++++++++----------------- 1 file changed, 11 insertions(+), 17 deletions(-) diff --git a/gcc/expr.cc b/gcc/expr.cc index 58f5fe76372..ca008cd453e 100644 --- a/gcc/expr.cc +++ b/gcc/expr.cc @@ -13164,38 +13164,32 @@ do_store_flag (sepops ops, rtx target, machine_mode mode) && (TYPE_PRECISION (ops->type) != 1 || TYPE_UNSIGNED (ops->type))) { wide_int nz = tree_nonzero_bits (arg0); + gimple *srcstmt = get_def_for_expr (arg0, BIT_AND_EXPR); + /* If the defining statement was (x & POW2), then use that instead of + the non-zero bits. */ + if (srcstmt && integer_pow2p (gimple_assign_rhs2 (srcstmt))) + { + nz = wi::to_wide (gimple_assign_rhs2 (srcstmt)); + arg0 = gimple_assign_rhs1 (srcstmt); + } if (wi::popcount (nz) == 1 && (integer_zerop (arg1) || wi::to_wide (arg1) == nz)) { - tree op0; - int bitnum; - gimple *srcstmt = get_def_for_expr (arg0, BIT_AND_EXPR); - /* If the defining statement was (x & POW2), then remove the and - as we are going to add it back. */ - if (srcstmt - && integer_pow2p (gimple_assign_rhs2 (srcstmt))) - { - op0 = gimple_assign_rhs1 (srcstmt); - bitnum = tree_log2 (gimple_assign_rhs2 (srcstmt)); - } - else - { - op0 = arg0; - bitnum = wi::exact_log2 (nz); - } + int bitnum = wi::exact_log2 (nz); enum tree_code tcode = EQ_EXPR; if ((code == NE) ^ !integer_zerop (arg1)) tcode = NE_EXPR; type = lang_hooks.types.type_for_mode (mode, unsignedp); return expand_single_bit_test (loc, tcode, - op0, + arg0, bitnum, type, target, mode); } } + if (! get_subtarget (target) || GET_MODE (subtarget) != operand_mode) subtarget = 0;